------------------------------------------------------------------
-- DRAW CONTROL_BOARD No.2 VHDL     version 3.1 boards Aug 2000 --
------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
ENTITY ab2 IS
PORT (
      tube             : IN std_logic_vector(5 DOWNTO 0);
      multi_sel        : IN std_logic;
      drw_sel          : IN std_logic;
      data_in          : IN std_logic;
      rxw              : IN std_logic;
      enable           : IN std_logic;
      clock            : IN std_logic;
      dly_en           : OUT std_logic;
      sel              : OUT std_logic_vector(36 DOWNTO 25);
      p                : OUT std_logic_vector(7 DOWNTO 0) );
END ab2;

architecture logic_layout of ab2 is
      SIGNAL shft_q    : std_logic_vector(12 DOWNTO 0);
      SIGNAL shft_d    : std_logic_vector(12 DOWNTO 0);
      SIGNAL shft_clk  : std_logic;
      SIGNAL ltch_q    : std_logic_vector(7 DOWNTO 0);
      SIGNAL ltch_d    : std_logic_vector(7 DOWNTO 0);
      SIGNAL ltch_clk  : std_logic;
      SIGNAL shift_in  : std_logic;
      SIGNAL latch_ext : std_logic;

BEGIN
    sel(25) <= drw_sel when (tube = "011001") else '0';
    sel(26) <= drw_sel when (tube = "011010") else '0';
    sel(27) <= drw_sel when (tube = "011011") else '0';
    sel(28) <= drw_sel when (tube = "011100") else '0';
    sel(29) <= drw_sel when (tube = "011101") else '0';
    sel(30) <= drw_sel when (tube = "011110") else '0';
    sel(31) <= drw_sel when (tube = "011111") else '0';
    sel(32) <= drw_sel when (tube = "100000") else '0';
    sel(33) <= drw_sel when (tube = "100001") else '0';
    sel(34) <= drw_sel when (tube = "100010") else '0';
    sel(35) <= drw_sel when (tube = "100011") else '0';
    sel(36) <= drw_sel when (tube = "100100") else '0';
	shift_in <= (drw_sel or multi_sel) when (tube = "111010") else '0';
	latch_ext <= (drw_sel or multi_sel) when (tube = "111011") else '0';
    shft_clk <= '1' when ((shift_in = '1') and (clock = '1')) else '0';
    shft_d(0) <= shft_q(12) when (rxw = '1') else data_in;
    process(shft_clk) begin
      if( falling_edge(shft_clk) ) then
        shft_d(12 downto 1) <= shft_q(11 downto 0);
      end if;
    end process;
    process(shft_clk) begin
      if( rising_edge(shft_clk) ) then
          shft_q(12 downto 0) <= shft_d(12 downto 0);
      end if;
     end process;
     ltch_clk <= '1' when ((enable = '1') and (shift_in = '1')) else '0';
     process (ltch_clk) begin
       if( falling_edge(ltch_clk) ) then
         ltch_d(7 downto 0) <= shft_q(10 downto 3);
       end if;
     end process;
     process (ltch_clk) begin
        if( rising_edge(ltch_clk) ) then
          ltch_q(7 downto 0) <= ltch_d(7 downto 0);
        end if;
     end process;
     p(7 downto 0) <= ltch_q(7 downto 0);
     dly_en <= latch_ext;
end logic_layout;