Version 1 of the Tilecal digitizer and S-LINK interface has been tested for data integrity.  Data was collected using the 3-in-1 card with charge injection (CIS) signals. A number of problems were detected in the structure of the data and this note describes the observed pattern of failure.

Readout protocol of the first generation digitizer

A complete data package for an L1A event includes the following information.

A control word indicates the beginning of the data package for each event. After the control word is a data block that contains the data from all channels of every digitizer board present. A second control word concludes the data package for each event.

In the data block, there are data frames. The number of the data frames depends on how many digitizer boards are present in the system. Each 6-channel digitizer board adds two data frames, say Data frame A and Data frame B. Data frame A consists data from channels 1, 3, and 5 of the board, while Data frame B consists of data from channels 2, 4, 6. The data block begins with Data frame A of first digitizer board, then the Data frame B of the first digitizer board, and so on for all remaining boards.

Each data frame begins with a header word containing information about the frame. The highest bit bit31 of the DWORD header word is 1, so the header word can be distinguished from the data words which all have high order bits 0. The header word is followed by a number of data words. The number is predefined by the initialization process. A checksum word ends the data frame.

The data words are 32-bit, unsigned long integers. The highest order bit is the dataword flag which is 0. Bit30 is an even-parity bit, bit29-bit20, bit19-bit10, bit9-bit0 are data from the 10-bit ADC channels 1, 3, 5 for Data frame A or 2, 4, 6 for Data frame B respectively.

During the test, the 3-in-1 card was connected to the ADC input on digitizer board and the CIS signal was enabled. Two digitizer boards were read out. The digitizer boards were set up in run mode, with 15 samples, and pipeline length 100. A set of 22 successive events was collected and printed.

From the data acquired, the parity check is correct among all more than one thousand data words. This suggests that the data received are correct. For some events the number of words received is less than the number expected, and the possibility of loss of different type data varies. The first control word was most likely to be lost. We list the losses in the table below.

Reasons for data loss

The reason for the data loss is internal to the design and logic of the digitizer boards and S-LINK interface board.

We have investigated the output digital signals from the digitizer boards at the input port of S-LINK interface card, using an HP 1670 250MHZ logic analyzer. The result shows that some of those signals are far from stable, and some data pulses are only half the width of normal data pulses.

Also, flaws in the S-LINK interface card design could make the data package susceptible to losses.