Mezzanine card progress, status and who works on what
- Oct. 2001: decided to follow CMC standards and be compatible with SLINK mezzanine cards (TL);
- Nov. 2001: setup a mezzanine card teststand at UC using one hotlink evaluation board from Cypress (TL and Natalia);
- Dec. 2001: Initial design work (schematics) for hotlink mezzanine cards started (Natalia and Mircea), mezzanine card firmware
VHDL coding started (Natalia);
- Jan. 2002: Finishing up schematics(Natalia and Mircea), initial layout started (Mircea),
mezzanine card board level simulation (QuickSim) started (Natalia);
- April 2002: Schematics finalized (Natalia and Mircea), Board level simulation (QuickSim) from Tx to Rx mezzanine cards done (Natalia).
Layout finished (Mircea). PCB design for both holtink Tx and Rx were sent out early April. First prototype for both Tx and Rx
expected later April;
- May 2002: Both Tx and Rx hotlink mezzanine cards fully loaded. Initial testing on going (Natalia, Peter and Mircea). Found out that in the
hotlink Tx case, the PECL signals from hotlink chip to the optical transimitter are reversed, but the fix
is simple. After that, initial testing has been succesful... more testing is on-going (Natalia and Peter).
- June 2002: more testing is on going (Natalia, with help from Peter). finished all testing by the end of June (Natalia/Peter).
- Oct.: simplified the hotlink mezzanine cards design a lot, and new design without any FPGA (Rev B hotlink Tx/Rx) done (Mircea/TL), and simulated with motherboard
with QuickSim(Sakari). This is a very simple design with much simpler interface to the motherboard and better performance (better decoupling for the hotlink chips, to reduce the
Bit-Error-Rate, which is about 1 error per ~ a few hour on the 1st prototype). Received Rev B hotlink mezzanine cards on Oct. 25th and initial standalone test in BIST mode at UC(Mircea), and
successfully tested with motherboard on Oct.28th at FNAL (Sakari/TL).
Tested with hotlink evaluation board
for Bit-Error-Rate for more than 40 hours and no single error(TL). will test for longer period
later. Taxi mezzanine cards schematics finalized (Mircea/TL) and layout
on going (Mircea).
Last updated by Ted Liu on $Date: 2002/06/20 3:08:10 $ (UTC)