Pulsar board

Pulsar board progress, status and who works on what

Oct. 2001: First proposed as a tester board at Level 2 group meeting (TL);
Nov. 2001: Initial design work for Pulsar started (TL and Mircea);
Dec. 2001: Presented at the Level 2 review meeting as test stand tool (TL);
Jan. 2002: Initial overall firmware design and VHDL coding for SLINK merger case for Pulsar started (TL). decided to use LeonardoSpectrum for synthesis, and use Quartus II for place and route. Pulsar project is funded;
Feb. 2002: Presented at Level 2 group meeting (functional requirements as test stand tool). core firmware VHDL code in SLINK merger case working in Quartus II simulation (TL). Initial firmware design (Peter and TL) for teststand and VHDL coding (Peter) for hotlink transmitter (pulser) case started.
March 2002: Optimized Pulsar design based on what learned from firmware work (TL and MB), IO pin assigment for all three FPGAs are done (TL). Pulsr firmware in CVS !(set up and nicely managed by Peter);
April 2002: Finishing up Pulsar schematics (TL and Mircea). Initial Board level simulation (QuickSim) as SLINK merger successful (TL). Initial component placement started (Mircea). VHDL code for hotlink transmitter case working in Quartus II simulation (Peter); More intensive board level simulation in progress (TL).
May 2002: Pulsar schematics finalized (TL and Mircea). Made all P2 CDF control signals visible to Pulsar, and added a hook for the 53Mhz RF clock. Removed the buffers to P3 and have the Control FPGA directly interface with P3 connector. Extensive Board level simulation (QuickSim) successfully done on most part of the board (Sakari, supervised by TL). This includes VME access to all three FPGAs (with access to registers, internal RAMs and spy FIFOs), *every* single connector pin to and from FPGAs (as input or output), more simulation in SLINK merger case, VME interface to the two SRAMs. More intensive board level simulation in progress (Sakari)... initial VME address map in place (TL and Sakari). Every signal pin for each FPGA (502 user IO pins per FPGA) has been checked by hand as well for connectivity (TL).
June 2002: Changing and Optimizing Pulsar component placement (TL and Mircea). Documenting board level simulation details (Sakari). Initial code for receiving hotlink mezzanine card raw data (i.e. without FIFOs on mezzanine card case) and converting into SLINK format is working (Sakari and TL). Work on multi-board simulation is on going (Sakari and TL). Initial SLINK to PCI software for testing Pulsar prototype is ready, more work is in progress (Derek, with help from Peter). Changed and Optimized Pulsar component placement. actual routing started (Mircea, see new layout: Pulsar top placement, Pulsar top layer , Pulsar bottom placement, Pulsar bottom layer , Pulsar all layers ). documenting board level simulation details (Sakari). Work on multi-board simulation is on going(Sakari and TL) . Inital Multi-board simulation is successful: Pulsar now can receive data from 4 hotlink Rx mezzanine cards driven by 4 hotlink Tx mezzanine cards. This was done with 9 boards in the simulation (one Pulsar, 4 Rx mezzanine cards and 4 Tx mezzanine cards). The mezzanine cards used in the simulation do not have FIFOs, all FIFOs are implemented in the motherboard to keep things simple for the simulation (see multi-board simulation setup: Pulsar and his eight daughters ) Initial routing finished, trace analysis starts (Mircea).
July 2002: Trace analysis in progress (MB). Trace analysis show that the L1 input/output strobe needs improvement. decided to separate the strobes for L1 input and output (changes to Control FPGA schematics and L1 input, output, top level schematics, July 11th, 2002) to improve the signals (MB/TL)... Trace analysis results indicate that there are quite a few other signals (integrity) need to be improved...done(MB). Pulsar Mini-review as L2 teststand tool. Initial S-LINK to PCI software for testing Pulsar prototype is ready, using SSPCI and SPCIS (Derek). See S-LINK teststand setup, another view. Pulsar self test-mode firmware (without mezzanine cards) ready and simulated at board level (Sakari).
Aug. 1st: L2 review committee asked us to discuss the possibility of using Pulsar for L2 trigger upgrade for Run2b at L2 Review. Mircea finished crosstalk analysis (as suggested by Mini-review committe), Pulsar PCB (X 4) ordered on Aug. 9th. Work on documentation on going... prepare firmware and VME software for initial prototype testing (Sakari). More trace analysis on going(Mircea), now using IS MultiBoard tool from Mentor Graphics. Received 4 PCBs, and initial simple tests on one PCB performed and no problem found (Mircea). 2 PCBs (see Pulsar PCB top view and bottom view) and parts were sent out on Aug. 29th, expect the boards back by Sept.18th.
Sept.: Work on L2 upgrade proposal (see draft, work in progress (Peter and TL, with help from many) ), and board and device level description of Pulsar (see content of the documentation (TL for initial draft)) ). Prepare for initial prototype testing work on going (Sakari). Taxi version mezzanine card work started (Mircea/TL). Received one S32PCI64 from CERN, sent to Upenn on Sept. 13th. Paul at Upenn will work on this. Kristian will also start working on Pulsar project. Received 2 Pulsar prototypes on Sept. 21. First two days "smoke test" at UC (Mircea/TL/Sakari). Teststand setup at FNAL (Peter/Cheng-Ju/Arnd) the week after. Pulsar prototype testing moved to FNAL on Sept.23rd and intensive Pulsar prototype testing/debugging started (Sakari and TL).
Oct.: Pulsar prototype testing continues at B0(Sakari/TL). Rev B hotlink mezzanine cards design (without FPGAs) finished (Mircea/TL) and simulated with motherboard (Sakari) with QuickSim. Received Rev B hotlink mezzanine cards on Oct. 25th, standalone testing in BIST mode at UC (Mircea), and tested with Pulsar mohterboard at FNAL(Sakari/TL). Tested Pulsar with Gigabit Ethernet interface (with Bob Blair and John Dawson) on 29th. Finished initial check-out of Pulsar prototype by the end of Oct. and have tested every single interface (including spare lines) of the two prototypes (Sakari/TL). Finalized Taxi mezzanine cards schematics (Mircea/TL), layout on going (Mircea).
Nov.: Sakari went back to Finland on Nov. 6th. Pulsar AUX card schematics started (Mircea/TL). Taxi mezzanine cards layout finished (Mircea). Hotlink Bit-Error-Rate test on going (TL). tested for 4 days continuously, zero error. Nov. 11th: Fixed the problems on two pairs of new hotlink mezzanine cards (colder solder joints), now have the full path working: Tx Pulsar with 4 Tx hotlink mezzanine cards sending data (driven by L1As) into Rx Pulsar with 4 Rx mezzanine cards and log data into PC (TL).

Last updated by Ted Liu on $Date: 2002/11/08 3:08:10 $ (UTC)