Pulsar board level simulation

There are a few steps for Board board level simulation. First of all, simulation at FPGA level (use each FPGA schematics), then at board level, then combine with mezzanine cards. It is important to apply all forces directly from the input connector pins, and check all output from output connector pins. Certain chips may not have models in QuickSim, a list should be made (may write simple model for them) and that part of schematics should be very carefully checked.

Pulsar board level simulation

Here is a list of things (at least) need to be done (some of them already done).

The FPGA level simulation was done first. This has been done succesfully for all FPGAs with SLINK merger firmware, to verify FPGA IO pin assignments and core firmware. But more intensive simulation will be at board level. This has been and will be done in the following steps:

(0) Use QuickSim and simple VHDL code to check all connections (from the physical connector pins to FPGA and then to output connector pins). Will send "walking one" type of patterns. This has been down in middle May for the whole board for all connections and turns out to be very useful! (found and fixed a few bugs this way, esp. the path from P2 backplane to FPGAs).

(1) simulation in SLINK merger mode. The firmware is such it exercises the following connections: all 4 J1 mezzanine connector to DataIO FPGAs, CDF control signals to all FPGAs, L1 trigger input connection to all FPGAs, internal connection from DataIO FPGAs to Control FPGA, and Control FPGA output to P3 (two SLINK ports). This has been done successfully in middle April.

(2) VME access to all FPGAs. The VME access for each FPGA has been simulated, and the standalone simulation for the UC VMEchip is done. the next step is to simulate the whole VME pass from P1 and P2 connectors to all FPGAs. This is on going. (comments: this has been done already early May).

(3) SVT input and output, TS input and output connections have been simulated in QuartusII, will simulate at board level soon (this has already been done early May).

(4) will need to simulate the SRAM interface for DataIO FPGAs next once the VME pass is working. (comment: this is on going, would like to finish this later May).

(5) will need to simulate the 4 J3 mezzanine card connections to each DataIO FPGA, this will be done at multi-board simulation, in both hotlink Tx and Hotlink Rx mode (note: the J1 and J3 connections have been checked in QuickSim for connectivity, see (0) ).

(6) need to combine all the above together to simulate the whole board at the same time...

Pulsar and mezzanine cards multi-board level simulation

This will be more involved. The firmware should be designed in such a way that they can be used for debugging the prototypes as well. current plan is to have one DataIO FPGA to drive one Hotlink Tx mezzanine card (which are connected to one Rx mezzanine card) and receive one Hotlink mezzanine card. The same for the other DataIO FPGA. The firmware effort for this is on-going.

Last updated on by Ted Liu on 05/20/02.