Pulsar is designed to have all the interfaces Level 2 decision crate has. This includes the VME and CDF control interface (see VME_INTERFACE block), Hotlink and Taxi optical IO (see Mezzanine connections), SVT/XTRP input (see SVT-XTRPin block), SVT/XTRP output (see SVT/XTRP out block), L1 input (see L1 in block), L1 output (see L1 Out block), and L2-TS interfaces (see TS I_O block). In addition, Pulsar has SLINK IO to P3 (see P3 connection). Clock distribution can be found in ClockBlock and Power distribution in Power block. There is a long Jtag chain which allows user to configure the main three FPGAs via one Jtag connector on the front panel. Each Pulsar board is identified by 6 bits dip-switch.

Two DataIO FPGAs (see DataIO FPGA block) are used to interface with 4 mezzanine cards, L1 input, SVT/XTRP input. These two FPGAs are identical (but firmware could be different). One bit (FPGA_ID) is used to tell the difference between the two (e.g. via VME access). the first DataIO FPGA has FPGA_ID set (hardwired) to 0, while the 2rd one has FPGA_ID set to 1.

The output of DataIO (in receiving mode) is sent into Control FPGA, where data can be merged. In addition to L1 input and SVT/XTRP input, Control FPGA also has SVT/XTRP output, as well as interface with Trigger Supervisor (connection to Level 2 global module in TS crate and another connection from Alpha processor). Note that the TS interface connections are not really essential for L2 teststand case. In the recorder mode, Pulsar will simply record data from upstream upon L1A. In the pulser mode, Pulsar will simply act as a L1 board to send data into L2 decision crate upon L1A while Alpha will handshake with TS directly. The reason TS interface connections are added on Pulsar board is (just) in case we want to use Pulsar as a prototype for possible L2 upgrade for Run2b.

Control FPGA has two SLINK ports to P3 (bi-directional), with 25 spare lines to P3 (optional SVT/XTRP input, or user defined input and output, such as NIM signals on AUX card).

VME and CDF control interface are visible to all three FPGAs. For CDF control signals, almost all of the CDF control signals are made available to either DataIO FPGA or Control FPGA. For details, see each FPGA section.

The three main FPGAs can be configured via three independent Jtag chains where Jtag connectors will be inside the board (note VME interface FPGA has its own Jtag). This may make the debugging of the board easier (also probably easier to use the SignalTap functionality for debugging). There is an option for user to (via a set of jumpers) chain all three Jtag chain together so that one can configure all three FPGAs via one Jtag connector on the front panel.

we also made the 53Mhz machine RF clock available to Pulsar, in case we need that for other applications (see clock block)..

all clock lines and some signal lines are terminated... will base on trace analysis results to finalize the termination...

more details here.

add documents here.

Last updated by Ted Liu (thliu@fnal.gov) on 2002/06/15