Pulsar will have the following clocks:

(1) algorithm clock: this is the clock used for all three FPGAs to process the data. This clock will go into each FPGA via dedicated clock pin (even with PLL). the FPGA will use this clock for algorithm, to clock data out from SVT/XTRP FIFO, to communicate with SRAM, and mezzanine cards (WRclk). The clocks will come from an osc (by default set at 60MHz but can be higher), each FPGA will get one (buffered version) clock via MCLKBus(2:0). Note there is one option to get this clock from the 53Mhz RF machine clock. In that case, one can use a 53Mhz oscillator. If the 53MHz RF clock fail, then the 53MHz oscillator can take over automatically within a few clock period. The chip does this is ICS581, see data sheet can be found at: Zero-Delay Glitch-Free clock multiplexer. The reason to have the 53Mhz RF clock input is to make the board more flexible (L2 does not need it).

(2) CDF_CLK: this is CDF specific clock (comes from P2). each FPGA will use CDF_CLK to latch L1A, L1 trigger data etc. each custom mezzanine card will also receive one CDF_CLK (for example, muon hotlink Rx mezzanine card will use this clock to get cdf_clk x4 via Robo Jr. and then use it as the Refclock to "lock" onto the incoming hotlink data). so there will be 7 cdf_clks out of the clock block.

(3) SLINK 40 Mhz clock: this clock is used for SLINK. each FPGA receives this clock via dedicated clock pin. DataIO FPGA can use this clock to send data to LSC (but most likely we will not use this feature). Control FPGA will use this clock to send SLINK data to P3. In addition, two more clocks are added as optional clocks to drive two SLINK output to P3. In the output (to P3) case, the actual SLINK clock (to P3) can either come from Control FPGA, or directly from this clock. Robo Clock is used to derive this clock from an 40Mhz osc. and user can adjust the timing of the clocks wrt the SLINK clock into Control FPGA via a few jumpers. put more details here... add data sheet for Robo clock.

add documents here. Last updated by Ted Liu (thliu@fnal.gov) on 2002/05/16