Pulsar VMEinterface block schematics description
Overall description
The VME interface part is based on the existing design from other UC CDF boards,
most of the modifications were done to P2 CDF control signals (add many more signals).
The VMEchip FPGA is directly from existing design from other UC CDF boards.
more details will be available later.
VME interface
The actual VME interface chip is based on the existing VME chip from other CDF boards
built at UC. The VME interface firmware is written in AHDL and this is the only part of
firmware which is not VHDL. The VME chip translate the raw VME commands from P1/P2 backplane
into local (board level) commands (to each of the three main FPGAs).
P2 backplane CDF control signals.
Essentially ALL used CDF control signals from P2 backplane
are made visible to Pulsar (either to Control FPGA or DataIO FPGA, or both).
In addition, there are 5 P2 use-defined (bused) signals dedicated for
Pulsar inter-communication via P2 backplane, the same as as that of SVT.
Any Pulsar board can drive or listen to any of these five lines.
There is a control bit (P2_OE) which can enable/disable buffer chips for the
CDF control signals. This bit is controlled by the Control FPGA. For L2 application,
this bit should be always enabled. In principle, the direction of the buffer
chips can be also changed by user (via a jumper). Again, for L2 application,
this jumper will not be loaded, and the direction will be set always for
input (to listen to P2 backplane). The reason to have these two control bits is
to make the board more flexible (at low cost).
Last updated on $Date: 2002/05/15 3:08:10 $ (UTC)