Pulsar P3 connection description

Pulsar P3 uses P2 style 5-row connector, just as in the Passive S-LINK to VME64x transition module. The SLINK signal map on P3 for Pulsar follows see page 2 for the pin map for P3 which has one LDC on upper half and one LSC slot on lower half. What we want is to have both slots bi-directional. There will be some changes to the signal map. for example, for the LSC slot, A31 is NC(3) not connected in the pin map, but we may want to connect it so that we can also use this line for LDC (as LDERR#).

another difference is that we will map 25 spare signals (from Control FPGA) S0_SP(24:0) to B row as user defined signal lines (to be defined on AUX card in the back. one possibility is to use these lines to bring in one SVT input on the AUX (transitional module we will build) into Control FPGA. will decide on this later.

Pin B1, B13, B32 and D32 are tied to 3.3V on the motherboard. This may be used to power the AUX card in the back... but need more thinking. will design the AUX later. for now, make sure the motherboard design is compatible with the AUX card from CERN, as we will use CERN AUX for prototype testing.

note: the original design had buffers to P3. we decided to remove the buffers and have the Control FPGA directly interface with P3.

note that the S1_IO is swaped with S2_IO. the reason is very simple: on Control FPGA, the IO pin assignment was such that it prefers the swap... since the IO pin is already assigned, it is simpler to just swap the two SLINK Ports here... this will make the routing much easier and keep all the signal traces close to P3.

Last updated by Ted Liu (thliu@fnal.gov) on 2002/05/17