Pulsar SVT/XTRP input description

Pulsar has one SVT/XTRP input connector. The input data is made visible to all three FPGAs via three identical sets of (external) FIFOs. The external FIFO approach follows that of SVT boards, but we use three of them so that each FPGA can read its own FIFO independently. The flow control is done in such a way that if any one of them is full, the back presure is on (hold is an "OR" of three hold_feps). Note that there is also one optional SVT/XTRP input via P3 spare lines. the SVT/XTRP connector will be on the transition module (AUX). in that case, no external FIFO will be used on AUX card.

add documents here. Last updated by Ted Liu (thliu@fnal.gov) on 2002/04/19