the Level 1 input is visible to all three FPGAs. The signal map is based on the Fred output to the Level 1 interface side (view from L1 interface board). put documentation here. The 64 trigger bits are sent to FPGAs as L1_IN(63:0), while buffer bits (1:0) (come from two cables) are L1_IN(65:64), and data strobe 2 and 1 (from two cables) are L1_IN(67:66).

Note that the Level 1 output signal map is based on PreFred signals on the PreFred side (due to historic reason: PreFred was built at UC). Thus to drive Fred data out to L1 output, one needs to take care the signal assignment in firmware as they are different. (note: The Level 1 output signal map has been changed to Fred signals on the Fred side on July 12th, 2002. The older one with PreFred signal can be found at old version for L1 output).

To save FPGA IO pins, the Level 1 input and output share the same IO pins on each FPGA (note that this made the component placement and routing harder). There is an enable (L1_IN(68)) to control the direction, this enable should be driven only by Control FPGA (in firmware). this enable is also made visible to DataIO FPGAs. DataIO FPGAs could check this enable bit (should always define it as input) to make sure it is receiving data from L1 input connector.

based on trace analysis results, we have to change the schematics to separate the data strobes for L1 input and output, in order to improve these signals. This was done July 12th, 2002. and re-routing is in progress... will perform trace analysis again after this.(as of July 15, 2002).

Last updated by Ted Liu (thliu@fnal.gov) on 2002/07/15