Pulsar Schematics ( sheet 1 to sheet 25 in one file pdf format)

• Sheet 1: Top Level ( ps or pdf ) and description - This is the Pulsar Board Top Level schematics. The schematics contains total of 25 sheets.

• Sheet 2: DataIO FPGA1 ( ps or pdf ) and description - This is the Data IO FPGA1 schematics.

• Sheet 5: DataIO FPGA2 ( ps or pdf ) and description - This is the Data IO FPGA2 schematics. The two DataIO FPGAs schematics are identical and the firmware can be identical in some cases and can be different in others.

• Sheet 15: Control FPGA ( ps or pdf ) and description - This is the Control FPGA schematics. The name control is somewhat misleading, as it also acts as a data Merger.

• Sheet 3: Mezzanine card 0 connection ( ps or pdf ) and description

• Sheet 4: Mezzanine card 1 connection ( ps or pdf ) and description

• Sheet 6: Mezzanine card 2 connection ( ps or pdf ) and description

• Sheet 12: Mezzanine card 3 connection ( ps or pdf ) and description

• Sheet 13: Level 1 trigger input connection ( ps or pdf ) and description

• Sheet 16: Level 1 trigger output connection ( ps or pdf ) and description

• Sheet 17: Trigger Supervisor interface ( ps or pdf ) and description

• Sheet 19: SVT/XTRP output ( ps or pdf ) and description

• Sheet 21: SVT/XTRP input ( ps or pdf ) and description

• Sheet 22: SVT/XTRP input FIFO 0 ( ps or pdf ) and description

• Sheet 23: SVT/XTRP input FIFO 1 ( ps or pdf ) and description

• Sheet 24: SVT/XTRP input FIFO 2 ( ps or pdf ) and description

• Sheet 7: VME/CDF control interface block ( ps or pdf ) and description

• Sheet 8: VME bus P1 ( ps or pdf ) and description

• Sheet 9: VME bus P0 ( ps or pdf ) and description

• Sheet 10: UC VME interface FPGA ( ps or pdf ) and description

• Sheet 11: VME/CDF control bus P2 ( ps or pdf ) and description

• Sheet 14: P3 connection ( ps or pdf ) and description

• Sheet 20: Clock block ( ps or pdf ) and description

• Sheet 18: Power block ( ps or pdf ) and description

• Sheet 25: Jtag Chain ( ps or pdf ) and description