Pulsar Hardware Design Consideration
Pulsar Overall Design Consideration
As an universal tester board for Level 2, the minimum hardware requirement
for Pulsar is to have all the
interfaces
Level 2 decision crate
has. The only way to absorb all the interfaces on one 9U VME board is
to use mezzanine cards to take care of the optical data paths (transimitter and
receiver). More details can be found in a recent
talk:
Pulsar Mezzanine Card connector choice
The connector choice is very important. We decided to follow CMC standard,
and this also makes the mezzanine card slots compatible with S-LINK
mezzanine cards. This feature allows multiple Pulsar boards to communicate
with high bandwidth links ("Lego" style).
Pulsar Mezzanine Card Identification issues
Since we will have hotlink, taxi and GLINK transimitter and receiver custom mezzanine cards,
it is important for the motherboard to identify what type of mezzanine cards are
plugged in. There are 4 bits reserved for this purpose (on J3 connector), each type of
mezzanine card will have its own CARD_ID(3:0). At power up, motherboard DataIO FPGAs will first
check the CARD_ID and make sure it is compatible with the firmware.... more details here.
Pulsar FPGA choice
Altera APEX20K400BC-652-1XV (BGA) FPGAs are used for both DataIO and Control FPGAs. For VME interface, we use the
VMEchip from the existing UC design for other CDF board, and the FPGA is Altera EPM7128S-160-7...
Pulsar FPGA IO pin assignment issues
There are two dedicated clock pins (one with PLL) for APEX20K400, and 4 dedicated
input pins. These pins are assigned by the compiler with working (core) VHDL
code. The assignment looks reasonable. Many other IO pins are assigned by hand
to make routing easier. For example, the signal pins from mezzanine card connectors
will stay on the side facing the mezzanine cards, and the signal traces will not
cross each other... etc. The SRAM related signals are close to each other
on the side facing the SRAM. The output signal pins from DataIO FPGA to Control FPGA
and the output signal pins from Control FPGA to P3 are all assigned by hand.
Pulsar SRAM choice
SRAM CY7C1350-100 (FLP) is chosen (128K x 36 bits). This SRAM costs about $20 and has
simulation model.
Pulsar clock distribution consideration
The clock distribution needs some explanation... see schematics part. add more details
here once finalized.
Pulsar power distribution consideration
Pulsar trace analysis
will check this once routing is close to final.
Pulsar AUX card design issues
Last updated by Ted Liu $Date: 2002/04/18 3:08:10 $ (UTC)