As a teststand tool and upgrade path for CDF Level 2 trigger system (also see Level 2 Operation Page and Level 2 elog), Pulsar is designed to be able to not only test each individul interface board (source data), but also to record data from upstream for each trigger data path. In principle, it can be also used to test the Level 2 decision crate as a system. CDF Level 2 trigger decision crate has many interfaces. Pulsar is designed to have all the interfaces Level 2 decision crate has, and is capable to sink and source data for each trigger data path (Pulsar stands for Pulser And Recorder).
First of all, Pulsar needs to have the general CDF DAQ crate interfaces:
In addition, Pulsar needs to have all the Level 2 trigger related interfaces:
For historical reasons, each Level 2 trigger input data path interface was somehow implemented in a different way, this was the main difficulty for Pulsar design. The only way to have all these interfaces on one type of 9U VME board is to use mezzanine cards to absorb some of the differences for the optical paths and to have both sink and source capabilities. As a general Level 2 teststand tool, Pulsar baseline design has 4 mezzanine card connections for optical data IO and can either source or sink data for each optical data path (depends on what type of mezzanine card plugged in). In addition to the 4 mezzanine card connections, there are three different types of cable connectors ( TS connector, L1 connector and SVT/XTRP connector) to interface with other trigger paths(with both input and output connections on board). All three FPGAs will be Atlera APEX 20K400BC652 with 26KB internal RAM capability and 502 user IO pins (BGA package). Each Optical DataIO FPGA will also have one external SRAM attached to allow user to either download or record large number of events.
With a few minor modifications to the baseline design, one can make Pulsar a more general purpose tool with much enhanced capabilities. With this design, the Level 1 trigger input and SVT/XTRP input are made available to all three FPGAs (instead of just one). In addition, Pulsar will have two S-LINK ports (bi-directional) via P3 backplane (through a transition module in the back similar to the simple transition module made at CERN). This allows Pulsar to communicate directly with a PC or VME processor (both directions) via high bandwidth commercially available S-LINK to PCI/PMC interface cards (note: it doesn't have to be SLINK, one cn re-define the LINK to interface with on the AUX card or simple mezzanine card if needed). The Hotlink and Taxi mezzanine card design will follow CMC(Common Mezzanine Card) standard similar to the 32-bit S-LINK mezzanine card standard. Unlike 32-bit S-LINK mezzanine cards which only use one CMC connector (J1), our custom Hotlink and Taxi mezzanine cards (each has up to 4 fiber channels) need two CMC connectors and the actual implementation follows the specification for S-LINK 64-bit extension to use both J1 and J3 CMC connectors. This way the mezzanine card connector is still compatible with 32-bit S-LINK mezzanine cards and both our custom mezzanine cards and S-LINK mezzanine cards can be plugged onto Pulsar via the same mezzanine card connectors. This feature makes Pulsar a much more general purpose board. This will be a very useful feature for Pulsar as a teststand tool as well. In addition, this feature makes it possible to test the Pulsar prototype by using the commercially available S-LINK test tools, namely SLIDAS (S-LINK Infinite Data Source) and SLIDAD (S-LINK Infinite Data Drain). Because one can also plug in 4 S-LINK mezzanine cards in the front, Pulsar can also be used as a S-LINK merger. This feature could be useful as up to 4 Pulsar S-LINK outputs can be merged into one data stream in S-LINK format through one additional Pulsar board and then interface directly with a PC. With the flexible S-LINK interface capability, Pulsar could also be used as a general purpose diagnostic tool, a simple DAQ system, or an upgrade path for our Level 2 trigger system.
S-LINK is a CERN specification for an easy-to-use FIFO-like data-link which can be used to connect front-end to read-out at any stage in a dataflow environment. S-LINK cards, PCI/PMC interfaces and test tools are all commercially available. S-LINK has been used by many experiments within and outside High Energy Physics, and will be used extensively by many LHC experiments with high data bandwidth requirements in the future, including ATLAS, CMS and LHCb. S-LINK is part of the High Speed Interconnect project at CERN.
