Pulsar as a general purpose tool

General description on Pulsar as a general purpose tool (work in progress)

The capability to interface with S-LINK (and thus PC) makes Pulsar a much more powerful diagnostic tool. Although Pulsar is designed primarily as a teststand tool for CDF Level 2 trigger system, the flexible "Lego style" design philosophy makes it possible to use Pulsar as a more general purpose tool within Level 2 trigger or outside Level 2 trigger system, within CDF or even outside CDF.

Pulsar can convert any input data into SLINK format. SLINK format is very flexible since the specification is designed for an easy-to-use FIFO-like data-link which can be used to connect front-end to read-out at any stage in a dataflow environment. One example is the ATLAS SLINK format (for details see document on event format in the ATLAS DAQ/EF prototype in pdf format or in postscript format). The SLINK data package can be sent out via P3 connector into a S-LINK interface LSC card (Link Source Card) which is mounted on a simple VME64x transition module similar to S2VME64x. The output data (from the LSC mezzanine card) can be sent to a LDC card (Link Destination Card), and can then be sent into a PC via SLINK to PCI card. In what follows, we will use a few examples in the Level 2 system to show some details. Note that the capability to record data into a PC (spy data) should be very useful for Level 2 teststand, since one can record real trigger data this way and the recorded data can be played back in a teststand environment. This is an advanced feature and can be implmented at a later stage.

Pulsar as a general purpose monitoring tool for Level 2 trigger system (work in progress)

Level 2 Muon trigger data is transfered via 16 hotlink fibers into Level 2 decision crate. Each meaningful muon word is packed into 4 hotlink 8-bit words with only 24 bits are useful data. One Pulsar board can receive all 16 fibers with 4 mezzanine cards. Each DataIO FPGA can receive data from two mezzanine cards, and DataIO FPGA can convert the input data into SLINK format in such a way that the data will identify itself to downstream (which fiber it belongs to etc). The data from two DataIO FPGAs can be mergered into a single data stream and output to P3. The SLINK format will be similar to the ATLAS SLINK format , but can be made much simpler (i.e. only a few words are needed for header and trailer).

Note that although each DataIO FPGA doesn't have to pack the data into SLINK format before sending them to Control FPGA, there are some advantages to this approach. First of all, this makes the firmware design in both DataIO and control FPGAs very similar; secondly, the data will identify itself to downstream and one can pack other information in the header and trailer at each stage to allow more robust error checking. The other way to do this is to have each DataIO FPGA directly write data into a FIFO inside Control FPGA and only Control FPGA will pack the data in SLINK format. Either way, the change will be only in the firmware. Note also that although the Control FPGA SLINK output clock runs at 40Mhz (to match with the LDC or LSC mezzanine cards), the internal algorithm clock for both DataIO and Control FPGAs can be much higher. The output clock from DataIO to Control FPGA can be higher than 40Mhz as well.

This is similar to the muon case. The main differences are that now the data is of varialbe length, one cluster information is spreaded over 6 fibers and there is one LVDS cable in addition to hotlink fibers. CLIST (i.e. cluster trigger) data is transfered to Level 2 decision crate via 6 hotlink fibers and one LVDS cable. One cluster information is encoded into 6 hotlink 8-bit words per fiber over total of 6 fibers. The information from LVDS cable marks the end of the event (i.e. data is variable length). One Pulsar board can receive the data via two mezzanine cards and all CLIST data will be visible to one DataIO FPGA. The DataIO FPGA can then convert the data into SLINK format. Isolation data path case is similar, with 6 taxi fibers carry the data, and one Taxi fiber carries the control information (end-of-event information etc). The other DataIO FPGA can receive the Isolation trigger via two Taxi mezzanine cards. The control (or merger) FPGA can then combine the two paths together. Each FPGA can check the L1A buffer number, CLIST or Isolation data buffer numbers to make sure they all belong to the same event. If there is any mismatch, an error will be flaged in the trailer word of the SLINK package.

Useful Links (work in progress)



Last updated by Ted Liu $Date: 2002/04/11 3:08:10 $ (UTC)