Pulsar Firmware (VHDL code)

Pulsar Firmware Overall Design Considerations

Initial VHDL design and coding effort started in early Jan. by TL, with the goal to optimize Pulsar hardware design (number of FPGAs, type of FPGAs etc) through actual implementation of the core VHDL. Since the plan was to have SLINK interface capability, and receiver mode firmware will likely need more FPGA resource, it was decided to start with SLINK merger case firmware, and at the same time to implement other general common stuff for all FPGAs. The receiver firmware was designed in such a way that it is similar to all FPGAs, and it is similar in all receiver cases. This made the actual firmware coding much easier. The actual SLINK formating code is based on firmware code developed at CERN for ATLAS written by Christophe Schwick (who kindly gave us the permission to use his code).

Tools involved for Pulsar firmware development

Pulsar Firmware VHDL projects (only active ones listed)

This version of firmwaree was first implemented and has been first used for board level simulation in April (TL). It has SLINK merger and VME interface implemented. It is for the case when 4 SLINK LDC mezzanine cards plugged into Pulsar and Pulsar can merger the 4 data pathes into SLINK format then send the data to P3 backplane. The input stage is implemented as a few input FIFOs: (1) L1A FIFO or queue, which latches L1A from P2 backplane and queue the L1A requests (up to 4 of them at a time) waiting to be processed. This FIFO will also contain buffer numbers etc. (2) L1 trigger input FIFO (64 bits, 4 words deep); (3) mezzanine card1 input FIFO; (4) mezzanine card2 input FIFO; (5) SVT/XTRP input FIFO. The core code is a statemachine which watches the L1A queue, and service each L1A by reading the data (belongs to that L1A) from other FIFOs and merge them into an output FIFO. The statemachine will then inform the SLINK formatter (code from CERN) to start formatting the data in SLINK format with header and trailer information properly stamped.

Sakari later attached internal RAMs to each input FIFOs, so that one can download patterns into the RAMs via VME, and then "play" the data downstream upon L1A. One can test Pulsar board this way without the need for mezzanine cards.

Status: first simulated at board level in QuickSim in April (TL) and has been used extensively to simulate Pulsar at board level since (by Sakari). Has been used extensively for Pulsar prototype testing (Sakari/TL).

This firmware is based on the SLINK merger. By simply adding a few more input FIFOs to receive data from each hotlink fiber channel, one can turn the SLINK merger firmware into hotlink data to SLINK converter firmware. This code was used to simulate eight hotlink mezzanine cards with one Pulsar motherboard board (Sakari). This version is potentially useful when Pulsar acts as a data recorder.

Status: has been used extensively for multi-board level simulation (Sakari) to verify Pulsar design and Rev B hotlink mezzanine cards design, and has been used extensively for Pulsar and Rev B hotlink mezzanine cards protoype testing in Oct.

This firmware has been used extensively to verify the Pulsar design by checking all signal connections for the Pulsar board with board level simulation.

Status: This firmware was later integrated into the SLINK merger/hotlink to SLINK converter by Sakari, and has been used extensively for the Pulsar protoype testing.

This firmware is for hotlink Tx for initial Pulsar prototype testing. This version has been improved by Tomi (joined us in Jun 2003) as actual Tx for muon path.

Status: simulated at multi-board level, and has been used for Pulsar and Rev B hotlink mezzanine cards testing.and used extensively for muon path commissionning.

Sakari and Tomi are now the dedicated people writing firmware for all other cases (as of Oct. 2003), under supervision of TL. This firmware was for Tx mode for Pulsar as a teststand tool (data source). This was intended to be the advanced version for the hotlink Tx case, to allow user take care of each event latency, data size, data gap within event... etc.

Status: Inactive. early initial version simulation at FPGA level in May 2002. has not been simulated at board level.not used on board.

Pulsar VME address Map (work in progress)

documentation in progress...

Last updated by Ted Liu $Date: 2002/10/30 3:08:10 $ (UTC)