The simplest way to design the hotlink and taxi mezzanine cards is to not use any FIFOs or FPGAs on the mezzanine cards. This way, motherboard will "see" the raw hotlink (or taxi) signals directly. In the receiver case, the raw hotlink(taxi) data is pushed into the FIFOs on the motherboard (DataIO FPGAs), while in the tx case, the raw data is pushed directly from motherboard FPGA (FIFOs) into hotlink (or taxi) chips. This also reduce the number of IO pins required on the CMC connectors as all of the FIFO related signals are not needed (they are all internal to the motherboard FPGA). From functionality point of view, there is not much difference (having or not having FPGA/FIFOs on the mezzanine cards). In fact, the multi-board simulation (with one Pulsar and eight mezzanine cards) was done in such a way that only simplified mezzanine card schematics were used in the simulation (with all FPGAs removed from mezzanine card schematics).
It was decided earlier that small FPGAs to be used on the mezzanine card prototypes. The motivation back then was simple: having small FPGAs on the mezzanine cards would allow more flexibility to test the prototypes since the motherboard will likely not available at the time the mezzanine card prototypes were built. This has been shown to be useful at the prototyping testing stage, although extra work was needed to deal with the FPGAs since the design was more involved compared to the case without FPGAs on mezzanine cards. See 1st Hotlink Mezzanine cards (with FPGAs) prototype schematics, layout and component list (obsolete). Natalia wrote a draft to document the mezzanine card design with FPGAs and one can find it here (note others on the author list have not had time to read and comment on the draft).
In Oct. 2002, we decided to simplify the hotlink mezzanine cards design, and submitted Rev B in which all the FPGAs have been removed from the design (also with better decopuling for the Hotlink chips to improve Bit-Error-Rate). Taxi mezzanine cards will be done the same way (i.e. without FPGAs).