This is a firmware to test the Pulsar board functionality. It receives data from different inputs, merges the data, and sends it out in SLINK format.
Incoming data to the Pulsar board can come in to the board in two different ways. It can be uploaded to the FPGAs using VME interface or it can came from the input data connectors on the board. This firmware reads data from the Level 1 trigger data inputs, Level 1 accept data inputs, and from the four mezzanine card inputs.
The firmware for the DataIO FPGAs has input RAMs for the mezzanine card inputs and for the Level 1 accept data input. These RAMs can be uploaded and enabled trough VME interface. The firmware waits for the Level 1 accept signal. When the Level 1 accept comes, the firmware waits for incoming data from the real inputs or from enabled input RAMs. When data from the Level 1 trigger data inputs, Level 1 accept data inputs and from the two mezzanine card inputs is received, the data is merged and converted into SLINK format. End of event mark, in every one of the incoming data, tells the firmware when all of the data is received. After the data is received from all of the inputs it is then send to the Control FPGA in SLINK format.
Control FPGA waits for the data from the two DataIO FPGAs. After all of the data is received the firmware merges these two incoming data to one, and packs it again into SLINK format. Then this data is send out from the P3 connection.
VME address map for the SLINK firmware.
Simulation results
Memory input files as data inputs
In this simulation input FIFO RAMs are filled with memory input files. Only Level 1 trigger data comes from the on board connectors.Notes
QuickSim simulation results
QuickSim scripts
