Pulsar Board Simulation Results

Design test simulations

Pulsar board design has been carefully checked by performing extensive board level simulations, using QuickSim-II from Mentor Graphics. The simulation includes a few parts: (1) ALL signal connections of Pulsar board to the external world; (2) VME access to Pulsar board; (3) full algorithm simulation; (4) actual interface with all mezzanine cards;

The details of each part are described below (divided into six sections):

Interfaces

This part tests the connectivity of ALL the interfaces of the Pulsar board.

VME

This part tests various VME accesses to all three main FPGAs and attached SRAMs.

SLINK merger

This part tests the Pulsar boards functionality assuming SLINK mezzanine card inputs(i.e. in SLINK merger case).

Test mode

This part is similar to the SLINK merger case, except that the input data are from internal RAMs (at the inputs of input FIFOs) instead of mezzanine cards. This is designed to test the Pulsar board without the need of mezzanine cards.

Hotlink communication between transmitter and receiver

This part is to prepare for the multi-board simulation (see below). It simulates the hotlink communication between transmitter and receiver using simplified hotlink mezzanine card schematics (i.e. without FPGAs).

One Pulsar with eight Hotlink mezzanine cards

This part simulates one Pulsar board (in Rx mode) with eight hotlink mezzanine cards. Four Hotlink transmitter cards (with 16 fiber input channels) sending data to four Hotlink receiver mezzanine cards, the latter are then connected to one Pulsar board. The output from Pulsar (to P3) is in SLINK format which has all 16 fiber channel data mergered together.

Pulsar with 8 daugters

Prototype test firmware simulations

Simple test firmware

SLINK firmware