As of today (Sept. 25th, 2002), we successfully read back (via VME) the data 
in the SLINK spy buffer for the DataIO FPGA and the results look EXACTLY as 
simulation. This was done by using internal input RAMs with data patterns 
to mimic two mezzanine card data at Pulsar DataIO FPGA input stage, then 
drive Pulsar with L1A (see firmware block diagram). Upon L1A, the data 
patterns are "played" into the input FIFOs and then the state machine 
will start formating the data in SLINK format and stamp the header and 
trailer information. the output goes into a spy buffer so that we can read 
back the output data via VME afterwards.

see the result from the Pulsar prototype DataIO FPGA (with comments on what 
some of the words mean) and compare that with the simulation results 
(only the beginning and ending part of the data package are shown).