Documentation for SS Sorting

This document describes the basic functionality of HitSort.

Contents

Click here to see the entire HitSort.vhd file.

1   Data Flow

Input data => IN_HIT_DATA =>(feed into a fifo: FIFO_SORT_ALTERA)=> infifo_data => sent addra_RAW and addra_Column to LUT => +SSID_RAW + SSID_Column => indata_wSSID_reg0 =>(feed into a fifo: BUFIFO_SORT_ALTERA)=> indata_wSSID

indata_wSSID => use control signal + module header to count up int_nModRawPac Counting Modules

Feed into raw bucket:

indata_wSSID => RAWBucketArray(int_RAWBucketArray_WrPo(int_ssid_raw)) (int_ssid_raw)

RAWCounterArrayVector(0-3)(int_ssid_raw)

RAWDataExistVector(0-3)<= RAWDataExistVector(0-3) OR shifted_data_raw(21 downto 0)

int_module_id_rd_raw and int_module_id_wr_raw are both variable to iterate from 0 to 3.

Get int_prioraw_add from priority box: Priority Box

RAWBucketArray(int_RAWBucketArray_RdPo(int_prioraw_add))(int_prioraw_add)=> indata_wSSID_AfterRawSort

Feed into column bucket:

COLUMNBucketArray(int_COLUMNBucketArray_WrPo(int_ssid_column)) (int_ssid_column)<=indata_wSSID_AfterRAWSort

COLUMNCounterArrayVector(0-3)(int_ssid_column)

Get int_priocolumn_add from priority box:

indata_wSSID_AfterCOLUMNSort<=COLUMNBucketArray(int_COLUMNBucketArray_RdPo(int_priocolumn_add))(int_priocolumn_add)

MIAN SORTING CODE FOR RAW:


        if(int_nModRAWPac > 0 and stopraw_write/='1') then         -- start read out (There are more than 1 module in backet)
          -- set hit existing vector for a module
          -- setup the prio normal case
          if(reading_raw='0' and unsigned(RAWCounterArrayVector(int_module_id_rd_raw)(int_prioraw_add))/=1)then
            prioraw_in(21 downto 0) <= RAWDataExistVector(int_module_id_rd_raw);
            reading_raw<='1';
            -- setup the prio with SS0 is only header, skip SS0 to read with no delay 
          elsif(reading_raw='0' and unsigned(RAWCounterArrayVector(int_module_id_rd_raw)(int_prioraw_add))=1)then
            prioraw_in(21 downto 0) <= std_logic_vector(unsigned(RAWDataExistVector(int_module_id_rd_raw)) - 1);
            reading_raw<='1';
          -- read in the module
          elsif(reading_raw = '1' and unsigned(RAWCounterArrayVector(int_module_id_rd_raw)(int_prioraw_add))=1)then
            -- change bucket
            prioraw_in <= std_logic_vector(unsigned(prioraw_in) - unsigned(prioraw_add));
            if(int_prioraw_add=21) then
              reading_raw<='0';
              -- change module
              if(int_module_id_rd_raw=3) then
                int_module_id_rd_raw<=0;
              else  
                int_module_id_rd_raw<=int_module_id_rd_raw+1;
              end if;
            end if;
          end if;                       -- reading_raw 
          -- isolated trailer case. notime to find the upper. not good but no way
          if(reading_raw='0' and RAWCounterArrayVector(int_module_id_rd_raw)(int_prioraw_add)(0)='0')then
            indata_wSSID_AfterRAWSort_reg0<="000000000010111110111011111111101011001110"; --& X"beefface";
            indata_wSSID_AfterRAWSort_dv_reg0<='0';
          else
            -- output and read pointer for the bucket
            indata_wSSID_AfterRAWSort_reg0<=RAWBucketArray(int_RAWBucketArray_RdPo(int_prioraw_add))(int_prioraw_add);
            indata_wSSID_AfterRAWSort_dv_reg0<='1';
            -- read point
            RAWCounterArrayVector(int_module_id_rd_raw)(int_prioraw_add)
              <= std_logic_vector(unsigned(RAWCounterArrayVector(int_module_id_rd_raw)(int_prioraw_add))-1);
            if(int_RAWBucketArray_RdPo(int_prioraw_add)=c_RAW_depth) then
              int_RAWBucketArray_RdPo(int_prioraw_add)<=0;
            else
              int_RAWBucketArray_RdPo(int_prioraw_add)<=int_RAWBucketArray_RdPo(int_prioraw_add)+1;
            end if;

          end if;
        else 
          indata_wSSID_AfterRAWSort_reg0<="000000000000011101000111100001110100011110";--X"00000" & X"1d1e1d1e";
          indata_wSSID_AfterRAWSort_dv_reg0<='0';
        end if;    

2   Priority Box

Priority box makes it possible to locate only the coordinate with hit information and not waste time on not-hit area.

prioraw_in(21 downto 0) <= RAWDataExistVector(0-3)

prioraw_in => PRIORITYBOX => prioraw_add => int_prioraw_add


entity priority_encoder_raw is
generic(
output_width: integer := 24
);
port ( 
    Dec_addr: in  STD_LOGIC_VECTOR(output_width-1 downto 0);
    Addr : out STD_LOGIC_VECTOR(output_width-1 downto 0);
    Valid: out STD_LOGIC
);
end priority_encoder_raw;


architecture Behavioral of priority_encoder_raw is

signal int_valid : std_logic; 
  
begin

valid <= int_valid;

prior_enc_proc: process (dec_addr)
begin 
addr <= (others => '0');
int_valid <= '0';
L1 : for nn in 0 to output_width-1 loop
if dec_addr(nn) = '1' then
addr(nn) <= dec_addr(nn);
int_valid <= '1';
exit L1;
end if;
end loop;  -- nn
end process prior_enc_proc;                      
end Behavioral;



  int_prioraw_add <= 0 when prioraw_add = X"000000" else
                     0 when prioraw_add = X"000001" else
                     1 when prioraw_add = X"000002" else                  
                     2 when prioraw_add = X"000004" else
                     3 when prioraw_add = X"000008" else                  
                     4 when prioraw_add = X"000010" else
                     5 when prioraw_add = X"000020" else                  
                     6 when prioraw_add = X"000040" else
                     7 when prioraw_add = X"000080" else                  
                     8 when prioraw_add = X"000100" else
                     9 when prioraw_add = X"000200" else                  
                     10 when prioraw_add = X"000400" else
                     11 when prioraw_add = X"000800" else                  
                     12 when prioraw_add = X"001000" else
                     13 when prioraw_add = X"002000" else                  
                     14 when prioraw_add = X"004000" else
                     15 when prioraw_add = X"008000" else                  
                     16 when prioraw_add = X"010000" else
                     17 when prioraw_add = X"020000" else                  
                     18 when prioraw_add = X"040000" else
                     19 when prioraw_add = X"080000" else                  
                     20 when prioraw_add = X"100000" else  
                     21 when prioraw_add = X"200000" else  -- need to stop exact size. 
                     0;

  int_priocolumn_add <= 0 when priocolumn_add = X"0" else
                        0 when priocolumn_add = X"1" else
                        1 when priocolumn_add = X"2" else                  
                        2 when priocolumn_add = X"4" else
                        3 when priocolumn_add = X"8" else                  
                        0;

3   Almost Full Signal

Almost full signal is used to ensure there are maximum three modules in the bucket at any time.


int_RAWBucket_AFull_Counter( 0)<= c_RAW_depth + int_RAWBucketArray_WrPo( 0)  -  int_RAWBucketArray_RdPo( 0)
stopraw_read <='1'when ((int_nModRAWPac > 1) or
                          ( int_RAWBucket_AFull_Counter( 0) >= c_RAW_depth and int_RAWBucket_AFull_Counter( 0 ) > c_RAW_depth+c_RAW_depth-3 ) or
                          ( int_RAWBucket_AFull_Counter( 0) < c_RAW_depth and int_RAWBucket_AFull_Counter( 0 ) > c_RAW_depth-3  )

^repeat from 0 to 21 for RAW and 0 to 3 for COLUMN

int_RAWBucket_AFull_Counter(0-21), int_COLUMNBucket_AFull_Counter(0-3)

c_RAW_depth = 63, c_COLUMN_depth = 255

4   Counting Modules


---------------------------------------------------------------------
-- if trailer (40000000) or trailer and end event (40000 then 10 l1id) , count up module n and reset older one
--^^in Naoki's case, in our case, there's no trailer after each module, only end flag e0da0000.
---------------------------------------------------------------------
         if( ((indata_wSSID(31 downto 0)=X"e0da0000") ) and int_nModRAWPac > 1 ) then  --
            pre_write_done_RAW<='1';

          -- normal 
          elsif(( ((indata_wSSID(31 downto 0)=X"e0da0000") )and int_nModRAWPac < 2) or            
                 ( pre_write_done_RAW = '1' and int_nModRAWPac < 2) ) then
            pre_write_done_RAW<= '0';
            write_done_RAW<='1';
            if(write_done_RAW='1') then
              write_done_RAW_two<='1';
            end if;
            
            if(int_module_id_wr_raw = 3) then
              int_module_id_wr_raw <= 0;
              for jj in 0 to 21 loop
                RAWCounterArrayVector(0)(jj) <= "0000000000";
                RAWDataExistVector(0)<= (others =>'0');
              end loop;
            else
              int_module_id_wr_raw <= int_module_id_wr_raw+1;
              for jj in 0 to 21 loop
                RAWCounterArrayVector(int_module_id_wr_raw+1)(jj) <= "0000000000";
                RAWDataExistVector(int_module_id_wr_raw+1)<= (others =>'0');
              end loop;
            end if;
          -- not done
          else 
            write_done_RAW<='0';
--            RAWDataExistVector(int_module_id_wr_raw)<= RAWDataExistVector(int_module_id_wr_raw) OR shifted_data_raw(21 downto 0);
          end if;                       -- end of trailer



After raw sort.


-------------------------------------------------------------------------------
-- counter for the existing module for the each backet
-------------------------------------------------------------------------------        
        if( (write_done_RAW_two = '1' or write_done_RAW = '1') and read_done_RAW = '0') then
          int_nModRAWPac <= int_nModRAWPac + 1;
        elsif(write_done_RAW_two = '0' and write_done_RAW = '0' and read_done_RAW = '1') then
          int_nModRAWPac <= int_nModRAWPac - 1;
        end if;
        -- to back 0, soon after count. n.b. hold freeze confule that.
        if(write_done_RAW='1')then
          write_done_RAW<='0';
        end if;

        if(write_done_RAW_two='1') then
          write_done_RAW_two<='0';
        end if;