Source Clock(s) Destination Clock(s) Delay Added in ns
pll_main:pll_main_inst|pll_main_0002:pll_main_inst|altera_pll:altera_pll_i|outclk_wire[1] pll_main:pll_main_inst|pll_main_0002:pll_main_inst|altera_pll:altera_pll_i|outclk_wire[1] 5609.1
pll_main:pll_main_inst|pll_main_0002:pll_main_inst|altera_pll:altera_pll_i|outclk_wire[0] pll_main:pll_main_inst|pll_main_0002:pll_main_inst|altera_pll:altera_pll_i|outclk_wire[0] 102.2
altera_reserved_tck,I/O altera_reserved_tck 99.6
altera_reserved_tck altera_reserved_tck 52.5
DOVME_inst|b2v_inst|rldramii_inst|pll0|pll_afi_clk DOVME_inst|b2v_inst|rldramii_inst|pll0|pll_afi_clk 50.3
RxBlock_inst|road_inst|xcvr_inst|rx_4_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|rcvdclkpma RxBlock_inst|road_inst|xcvr_inst|rx_4_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|rcvdclkpma 44.0