Option Setting Default Value
Device 5AGXFB7H4F35C4  
Use smart compilation On Off
Maximum processors allowed for parallel compilation 3  
Minimum Core Junction Temperature 0  
Maximum Core Junction Temperature 85  
Device I/O Standard 3.0-V LVTTL  
Perform Physical Synthesis for Combinational Logic for Fitting On Off
Perform Physical Synthesis for Combinational Logic for Performance On Off
Perform Register Duplication for Performance On Off
Perform Register Retiming for Performance On Off
Perform Asynchronous Signal Pipelining On Off
Fitter Effort Fast Fit Auto Fit
Reserve all unused pins As output driving ground As input tri-stated with weak pull-up
Active Serial clock source FREQ_25MHz FREQ_100MHz
Enable parallel Assembler and TimeQuest Timing Analyzer during compilation On On
Enable compact report table Off Off
Router Timing Optimization Level Normal Normal
Perform Clocking Topology Analysis During Routing Off Off
Placement Effort Multiplier 1.0 1.0
Device initialization clock source INIT_INTOSC INIT_INTOSC
Optimize Hold Timing All Paths All Paths
Optimize Multi-Corner Timing On On
Auto RAM to MLAB Conversion On On
Equivalent RAM and MLAB Power Up Auto Auto
Equivalent RAM and MLAB Paused Read Capabilities Care Care
PowerPlay Power Optimization Normal compilation Normal compilation
SSN Optimization Off Off
Optimize Timing Normal compilation Normal compilation
Optimize Timing for ECOs Off Off
Regenerate full fit report during ECO compiles Off Off
Optimize IOC Register Placement for Timing Normal Normal
Final Placement Optimizations Automatically Automatically
Fitter Aggressive Routability Optimizations Automatically Automatically
Fitter Initial Placement Seed 1 1
Weak Pull-Up Resistor Off Off
Enable Bus-Hold Circuitry Off Off
Auto Packed Registers Auto Auto
Auto Delay Chains On On
Auto Delay Chains for High Fanout Input Pins Off Off
Treat Bidirectional Pin as Output Pin Off Off
Physical Synthesis Effort Level Normal Normal
Logic Cell Insertion - Logic Duplication Auto Auto
Auto Register Duplication Auto Auto
Auto Global Clock On On
Auto Global Register Control Signals On On
Synchronizer Identification Off Off
Enable Beneficial Skew Optimization On On
Optimize Design for Metastability On On
Force Fitter to Avoid Periphery Placement Warnings Off Off
Clamping Diode Off Off
Enable input tri-state on active configuration pins in user mode Off Off