Name Type Mode Clock Mode Port A Depth Port A Width Port B Depth Port B Width Port A Input Registers Port A Output Registers Port B Input Registers Port B Output Registers Size Implementation Port A Depth Implementation Port A Width Implementation Port B Depth Implementation Port B Width Implementation Bits M10K blocks MLAB cells MIF Location Mixed Width RDW Mode Port A RDW Mode Port B RDW Mode Fits in MLABs
DFSynchronization:DFSynchronization_inst|AFIFO32:headerfifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X51_Y26_N0, M10K_X59_Y26_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|AFIFO32:trailerfifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X59_Y28_N0, M10K_X51_Y28_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:0:ambroadcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X19_Y37_N0, M10K_X19_Y38_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:1:ambroadcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X27_Y39_N0, M10K_X19_Y39_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:2:ambroadcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X27_Y36_N0, M10K_X19_Y36_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:3:ambroadcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X19_Y34_N0, M10K_X19_Y35_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:0:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X75_Y34_N0, M10K_X75_Y33_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:1:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X51_Y90_N0, M10K_X59_Y90_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:2:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X51_Y87_N0, M10K_X43_Y87_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:3:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X75_Y92_N0, M10K_X75_Y91_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:4:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X101_Y95_N0, M10K_X96_Y95_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:0:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X143_Y101_N0, M10K_X148_Y101_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:0:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X143_Y102_N0, M10K_X148_Y102_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:1:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X111_Y98_N0, M10K_X120_Y98_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:1:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X111_Y97_N0, M10K_X120_Y97_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:2:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X96_Y92_N0, M10K_X101_Y92_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:2:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X101_Y90_N0, M10K_X111_Y90_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:3:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X111_Y88_N0, M10K_X101_Y88_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:3:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X111_Y92_N0, M10K_X111_Y91_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:4:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X148_Y98_N0, M10K_X143_Y98_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:4:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X148_Y99_N0, M10K_X143_Y99_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:5:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X111_Y100_N0, M10K_X111_Y99_N0 Don't care New data New data No - Address Too Wide
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:5:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|dpram_op61:FIFOram|altsyncram_e3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X111_Y96_N0, M10K_X111_Y95_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:0:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X59_Y105_N0, M10K_X59_Y106_N0, M10K_X59_Y102_N0, M10K_X51_Y102_N0, M10K_X51_Y104_N0, M10K_X51_Y103_N0, M10K_X51_Y105_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:10:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X101_Y116_N0, M10K_X96_Y114_N0, M10K_X96_Y116_N0, M10K_X111_Y114_N0, M10K_X101_Y115_N0, M10K_X96_Y115_N0, M10K_X111_Y115_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:11:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X101_Y110_N0, M10K_X96_Y110_N0, M10K_X96_Y111_N0, M10K_X101_Y112_N0, M10K_X101_Y111_N0, M10K_X96_Y113_N0, M10K_X101_Y113_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:1:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X59_Y112_N0, M10K_X59_Y113_N0, M10K_X59_Y111_N0, M10K_X51_Y112_N0, M10K_X51_Y111_N0, M10K_X51_Y113_N0, M10K_X51_Y114_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:2:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X96_Y102_N0, M10K_X96_Y105_N0, M10K_X96_Y104_N0, M10K_X101_Y102_N0, M10K_X96_Y103_N0, M10K_X101_Y103_N0, M10K_X101_Y104_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:3:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X120_Y108_N0, M10K_X120_Y106_N0, M10K_X130_Y106_N0, M10K_X120_Y109_N0, M10K_X120_Y107_N0, M10K_X130_Y107_N0, M10K_X130_Y109_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:4:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X67_Y102_N0, M10K_X67_Y101_N0, M10K_X67_Y100_N0, M10K_X75_Y102_N0, M10K_X67_Y103_N0, M10K_X75_Y101_N0, M10K_X75_Y100_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:5:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X75_Y106_N0, M10K_X67_Y108_N0, M10K_X75_Y108_N0, M10K_X75_Y109_N0, M10K_X67_Y107_N0, M10K_X75_Y107_N0, M10K_X67_Y109_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:6:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X75_Y114_N0, M10K_X75_Y113_N0, M10K_X75_Y116_N0, M10K_X67_Y113_N0, M10K_X75_Y115_N0, M10K_X75_Y117_N0, M10K_X67_Y117_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:7:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X120_Y118_N0, M10K_X111_Y117_N0, M10K_X111_Y116_N0, M10K_X111_Y118_N0, M10K_X111_Y119_N0, M10K_X120_Y117_N0, M10K_X120_Y119_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:8:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X101_Y118_N0, M10K_X101_Y117_N0, M10K_X96_Y118_N0, M10K_X101_Y119_N0, M10K_X96_Y119_N0, M10K_X96_Y117_N0, M10K_X96_Y120_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:9:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X67_Y118_N0, M10K_X67_Y116_N0, M10K_X59_Y118_N0, M10K_X59_Y116_N0, M10K_X67_Y119_N0, M10K_X59_Y117_N0, M10K_X59_Y119_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_sct_streams:0:SCT_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X111_Y104_N0, M10K_X111_Y108_N0, M10K_X120_Y104_N0, M10K_X111_Y105_N0, M10K_X111_Y107_N0, M10K_X111_Y106_N0, M10K_X120_Y105_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_sct_streams:1:SCT_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X101_Y108_N0, M10K_X96_Y106_N0, M10K_X96_Y108_N0, M10K_X101_Y106_N0, M10K_X96_Y107_N0, M10K_X101_Y107_N0, M10K_X101_Y109_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_sct_streams:2:SCT_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X67_Y104_N0, M10K_X67_Y105_N0, M10K_X75_Y104_N0, M10K_X75_Y105_N0, M10K_X75_Y103_N0, M10K_X59_Y103_N0, M10K_X59_Y104_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_sct_streams:3:SCT_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X111_Y112_N0, M10K_X120_Y110_N0, M10K_X111_Y111_N0, M10K_X111_Y110_N0, M10K_X120_Y111_N0, M10K_X111_Y113_N0, M10K_X120_Y113_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_sct_streams:4:SCT_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|altsyncram_vl91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes yes 65536 2048 32 2048 32 65536 7 0 None M10K_X120_Y102_N0, M10K_X120_Y103_N0, M10K_X120_Y100_N0, M10K_X111_Y102_N0, M10K_X111_Y103_N0, M10K_X111_Y101_N0, M10K_X120_Y101_N0 Don't care New data New data No - Address Too Wide
DOProcessVMEInput:DOProcessVMEInput_inst|tx_fifo:road_fifo|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 32 512 32 16384 2 0 None M10K_X35_Y38_N0, M10K_X27_Y38_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:0:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X27_Y90_N0, M10K_X27_Y88_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:10:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X96_Y100_N0, M10K_X96_Y101_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:11:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X96_Y96_N0, M10K_X75_Y96_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:12:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X96_Y94_N0, M10K_X75_Y97_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:13:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X101_Y98_N0, M10K_X96_Y97_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:14:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X75_Y98_N0, M10K_X75_Y99_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:15:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X67_Y86_N0, M10K_X59_Y86_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:16:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X67_Y90_N0, M10K_X75_Y90_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:17:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X51_Y86_N0, M10K_X43_Y86_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:18:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X43_Y98_N0, M10K_X43_Y97_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:19:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X35_Y99_N0, M10K_X35_Y100_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:1:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X27_Y94_N0, M10K_X27_Y91_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:20:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X35_Y98_N0, M10K_X35_Y97_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:21:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X43_Y99_N0, M10K_X43_Y100_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:22:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X51_Y100_N0, M10K_X51_Y97_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:23:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X59_Y98_N0, M10K_X67_Y98_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:24:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X51_Y99_N0, M10K_X59_Y96_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:25:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X51_Y98_N0, M10K_X59_Y97_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:26:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X59_Y100_N0, M10K_X67_Y96_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:27:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X59_Y101_N0, M10K_X67_Y97_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:28:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X59_Y99_N0, M10K_X67_Y99_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:29:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X51_Y101_N0, M10K_X43_Y101_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:2:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X35_Y90_N0, M10K_X35_Y87_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:3:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X35_Y91_N0, M10K_X35_Y89_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:4:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X43_Y94_N0, M10K_X35_Y92_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:5:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X43_Y90_N0, M10K_X43_Y91_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:6:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X51_Y94_N0, M10K_X43_Y92_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:7:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X96_Y98_N0, M10K_X96_Y99_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:8:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X101_Y100_N0, M10K_X101_Y99_N0 Don't care New data New data No - Address Too Wide
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:9:VMEBuffBlock_DO_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X101_Y96_N0, M10K_X101_Y97_N0 Don't care New data New data No - Address Too Wide
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_ipm1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 64 8 64 8 yes no yes yes 512 64 8 64 8 512 1 0 None M10K_X27_Y124_N0 Old data New data New data No - Unsupported Mixed Feed Through Setting
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_a_module:altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_a|altsyncram:the_altsyncram|altsyncram_oki1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 32 32 32 32 yes no yes no 1024 32 32 32 32 1024 1 0 None M10K_X5_Y132_N0 Don't care New data New data Yes
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_b_module:altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_register_bank_b|altsyncram:the_altsyncram|altsyncram_oki1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 32 32 32 32 yes no yes no 1024 32 32 32 32 1024 1 0 None M10K_X5_Y128_N0 Don't care New data New data Yes
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_mem_no_ifdef_params:sequencer_mem|altsyncram:the_altsyncram|altsyncram_m7j1:auto_generated|ALTSYNCRAM AUTO Single Port Single Clock 5376 32 -- -- yes no -- -- 172032 5376 32 -- -- 172032 32 0 RLDRAMII_s0_sequencer_mem.hex M10K_X27_Y127_N0, M10K_X19_Y128_N0, M10K_X27_Y126_N0, M10K_X19_Y125_N0, M10K_X5_Y129_N0, M10K_X5_Y125_N0, M10K_X43_Y128_N0, M10K_X27_Y131_N0, M10K_X35_Y126_N0, M10K_X35_Y127_N0, M10K_X35_Y129_N0, M10K_X27_Y125_N0, M10K_X43_Y127_N0, M10K_X27_Y129_N0, M10K_X35_Y131_N0, M10K_X43_Y129_N0, M10K_X19_Y129_N0, M10K_X43_Y131_N0, M10K_X43_Y126_N0, M10K_X43_Y130_N0, M10K_X35_Y125_N0, M10K_X35_Y128_N0, M10K_X35_Y130_N0, M10K_X19_Y126_N0, M10K_X19_Y127_N0, M10K_X27_Y130_N0, M10K_X27_Y128_N0, M10K_X19_Y131_N0, M10K_X5_Y131_N0, M10K_X5_Y126_N0, M10K_X19_Y130_N0, M10K_X5_Y127_N0 Don't care New data New data No - Address Too Wide
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_ac_ROM_no_ifdef_params:ac_ROM_i|altsyncram:altsyncram_component|altsyncram_q1u1:auto_generated|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 40 32 40 32 yes no no no 1280 40 28 40 28 1120 0 56 RLDRAMII_s0_AC_ROM.hex LAB_X20_Y135_N0, LAB_X15_Y135_N0, LAB_X20_Y134_N0, LAB_X15_Y134_N0        
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_cer1:auto_generated|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 36 8 36 yes no no no 288 8 36 8 36 288 0 36 None LAB_X12_Y134_N0, LAB_X15_Y132_N0        
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_inst_ROM_no_ifdef_params:inst_ROM_i|altsyncram:altsyncram_component|altsyncram_p8s1:auto_generated|ALTDPRAM_INSTANCE MLAB Simple Dual Port No clocks. 128 20 128 20 yes no no no 2560 128 20 128 20 2560 0 80 RLDRAMII_s0_inst_ROM.hex LAB_X12_Y135_N0, LAB_X3_Y135_N0, LAB_X3_Y136_N0, LAB_X12_Y136_N0        
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_read_datapath:read_datapath_i|rw_manager_pattern_fifo:pattern_fifo_i|altsyncram:altsyncram_component|altsyncram_aer1:auto_generated|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 32 9 32 9 yes no no no 288 32 9 32 9 288 0 9 None LAB_X8_Y136_N0        
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_e2v1:auto_generated|ALTDPRAM_INSTANCE MLAB Simple Dual Port Dual Clocks 16 32 16 32 yes no no yes 512 16 32 16 32 512 0 32 None LAB_X25_Y127_N0, LAB_X20_Y127_N0        
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_msr1:auto_generated|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 19 64 19 yes no no no 1216 64 19 64 19 1216 0 38 None LAB_X44_Y130_N0, LAB_X36_Y130_N0        
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|alt_rld_controller_top_ctl_bl_is_one:c0|alt_rld_controller_ctl_bl_is_one:controller_inst|memctl_wdata_rdata_logic:memctl_wdata_rdata_logic_inst|memctl_wdata_fifo:memctl_wdata_fifo_inst|scfifo:wdata_fifo|scfifo_4761:auto_generated|a_dpfifo_di51:dpfifo|dpram_6r61:FIFOram|altsyncram_k9q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 8 144 8 144 yes no yes no 1152 8 144 8 144 1152 4 0 None M10K_X27_Y132_N0, M10K_X27_Y134_N0, M10K_X27_Y133_N0, M10K_X27_Y135_N0 Don't care New data New data No - Latch Type Behaviour
DOVME:DOVME_inst|VMEBuffBlock:b2v_inst144|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X27_Y101_N0, M10K_X19_Y101_N0, M10K_X27_Y98_N0, M10K_X27_Y100_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|AMmapRAM:b2v_inst1|altsyncram:altsyncram_component|altsyncram_kn02:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 144 1024 144 yes no yes yes 147456 1024 144 1024 144 147456 15 0 None M10K_X59_Y20_N0, M10K_X51_Y22_N0, M10K_X43_Y20_N0, M10K_X67_Y20_N0, M10K_X51_Y21_N0, M10K_X67_Y19_N0, M10K_X67_Y17_N0, M10K_X67_Y21_N0, M10K_X67_Y18_N0, M10K_X67_Y22_N0, M10K_X59_Y22_N0, M10K_X59_Y19_N0, M10K_X67_Y16_N0, M10K_X67_Y15_N0, M10K_X51_Y19_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|HLMPIX:\HitListMemPix:0:Top_HitListMemPIX|altsyncram:altsyncram_component|altsyncram_a712:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes yes 32768 1024 32 1024 32 32768 4 0 None M10K_X51_Y115_N0, M10K_X51_Y116_N0, M10K_X51_Y117_N0, M10K_X51_Y118_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|HLMPIX:\HitListMemPix:1:Top_HitListMemPIX|altsyncram:altsyncram_component|altsyncram_a712:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes yes 32768 1024 32 1024 32 32768 4 0 None M10K_X67_Y85_N0, M10K_X75_Y86_N0, M10K_X67_Y84_N0, M10K_X75_Y85_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|HLMPIX:\HitListMemPix:2:Top_HitListMemPIX|altsyncram:altsyncram_component|altsyncram_a712:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes yes 32768 1024 32 1024 32 32768 4 0 None M10K_X19_Y97_N0, M10K_X27_Y96_N0, M10K_X27_Y97_N0, M10K_X19_Y96_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|HLMPIX:\HitListMemPix:3:Top_HitListMemPIX|altsyncram:altsyncram_component|altsyncram_a712:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes yes 32768 1024 32 1024 32 32768 4 0 None M10K_X27_Y111_N0, M10K_X27_Y110_N0, M10K_X27_Y112_N0, M10K_X27_Y113_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|HLMPIX:\HitListMemPix:4:Top_HitListMemPIX|altsyncram:altsyncram_component|altsyncram_a712:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes yes 32768 1024 32 1024 32 32768 4 0 None M10K_X130_Y111_N0, M10K_X143_Y110_N0, M10K_X130_Y110_N0, M10K_X143_Y111_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|HLMPIX:\HitListMemPix:5:Top_HitListMemPIX|altsyncram:altsyncram_component|altsyncram_a712:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes yes 32768 1024 32 1024 32 32768 4 0 None M10K_X67_Y114_N0, M10K_X59_Y114_N0, M10K_X59_Y115_N0, M10K_X67_Y115_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|HLMSCT:\HitListMemSCT:0:Top_HitListMemSCT|altsyncram:altsyncram_component|altsyncram_e712:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 16 1024 16 yes no yes yes 16384 1024 16 1024 16 16384 2 0 None M10K_X130_Y15_N0, M10K_X130_Y16_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|HLMSCT:\HitListMemSCT:1:Top_HitListMemSCT|altsyncram:altsyncram_component|altsyncram_e712:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 16 1024 16 yes no yes yes 16384 1024 16 1024 16 16384 2 0 None M10K_X162_Y103_N0, M10K_X148_Y103_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|HLMSCT:\HitListMemSCT:2:Top_HitListMemSCT|altsyncram:altsyncram_component|altsyncram_e712:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 16 1024 16 yes no yes yes 16384 1024 16 1024 16 16384 2 0 None M10K_X130_Y115_N0, M10K_X130_Y117_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|HLMSCT:\HitListMemSCT:3:Top_HitListMemSCT|altsyncram:altsyncram_component|altsyncram_e712:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 16 1024 16 yes no yes yes 16384 1024 16 1024 16 16384 2 0 None M10K_X75_Y14_N0, M10K_X67_Y14_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|HLMSCT:\HitListMemSCT:4:Top_HitListMemSCT|altsyncram:altsyncram_component|altsyncram_e712:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 16 1024 16 yes no yes yes 16384 1024 16 1024 16 16384 2 0 None M10K_X101_Y124_N0, M10K_X96_Y124_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|altshift_taps:fsm11L_read_sync0_rtl_0|shift_taps_vnu:auto_generated|altsyncram_nk91:altsyncram4|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 8 11 8 11 yes no yes yes 88 8 11 8 11 88 1 0 None M10K_X96_Y109_N0 Don't care New data New data Yes
DataOrganizer:inst129|DO11L:b2v_inst|altshift_taps:fsm11L_write_sync1_rtl_0|shift_taps_snu:auto_generated|altsyncram_fk91:altsyncram4|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 3 22 3 22 yes no yes yes 66 3 22 3 22 66 1 0 None M10K_X96_Y121_N0 Don't care New data New data Yes
DataOrganizer:inst129|DO11L:b2v_inst|altshift_taps:hit_EE_sync0_rtl_0|shift_taps_rnu:auto_generated|altsyncram_dk91:altsyncram4|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 4 11 4 11 yes no yes yes 44 4 11 4 11 44 1 0 None M10K_X111_Y109_N0 Don't care New data New data Yes
DataOrganizer:inst129|DO11L:b2v_inst|altshift_taps:hlc11L_hitlast_rtl_0|shift_taps_4ou:auto_generated|altsyncram_vk91:altsyncram4|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 3 39 3 39 yes no yes yes 117 3 39 3 39 117 1 0 None M10K_X96_Y112_N0 Don't care New data New data Yes
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:0:Top_HitCountMemPix|HCMPIX:\hcmpix8times:0:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X59_Y129_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:0:Top_HitCountMemPix|HCMPIX:\hcmpix8times:1:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X51_Y125_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:0:Top_HitCountMemPix|HCMPIX:\hcmpix8times:2:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X51_Y124_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:0:Top_HitCountMemPix|HCMPIX:\hcmpix8times:3:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X51_Y129_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:0:Top_HitCountMemPix|HCMPIX:\hcmpix8times:4:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X59_Y124_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:0:Top_HitCountMemPix|HCMPIX:\hcmpix8times:5:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X59_Y125_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:0:Top_HitCountMemPix|HCMPIX:\hcmpix8times:6:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X59_Y127_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:0:Top_HitCountMemPix|HCMPIX:\hcmpix8times:7:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X67_Y127_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:1:Top_HitCountMemPix|HCMPIX:\hcmpix8times:0:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X96_Y2_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:1:Top_HitCountMemPix|HCMPIX:\hcmpix8times:1:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X96_Y4_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:1:Top_HitCountMemPix|HCMPIX:\hcmpix8times:2:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X75_Y8_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:1:Top_HitCountMemPix|HCMPIX:\hcmpix8times:3:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X96_Y7_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:1:Top_HitCountMemPix|HCMPIX:\hcmpix8times:4:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X96_Y5_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:1:Top_HitCountMemPix|HCMPIX:\hcmpix8times:5:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X96_Y6_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:1:Top_HitCountMemPix|HCMPIX:\hcmpix8times:6:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X96_Y1_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:1:Top_HitCountMemPix|HCMPIX:\hcmpix8times:7:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X96_Y3_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:2:Top_HitCountMemPix|HCMPIX:\hcmpix8times:0:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X19_Y23_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:2:Top_HitCountMemPix|HCMPIX:\hcmpix8times:1:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X27_Y22_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:2:Top_HitCountMemPix|HCMPIX:\hcmpix8times:2:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X27_Y23_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:2:Top_HitCountMemPix|HCMPIX:\hcmpix8times:3:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X19_Y24_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:2:Top_HitCountMemPix|HCMPIX:\hcmpix8times:4:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X27_Y25_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:2:Top_HitCountMemPix|HCMPIX:\hcmpix8times:5:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X19_Y18_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:2:Top_HitCountMemPix|HCMPIX:\hcmpix8times:6:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X27_Y24_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:2:Top_HitCountMemPix|HCMPIX:\hcmpix8times:7:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X19_Y25_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:3:Top_HitCountMemPix|HCMPIX:\hcmpix8times:0:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X19_Y121_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:3:Top_HitCountMemPix|HCMPIX:\hcmpix8times:1:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X5_Y121_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:3:Top_HitCountMemPix|HCMPIX:\hcmpix8times:2:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X27_Y116_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:3:Top_HitCountMemPix|HCMPIX:\hcmpix8times:3:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X27_Y117_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:3:Top_HitCountMemPix|HCMPIX:\hcmpix8times:4:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X19_Y118_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:3:Top_HitCountMemPix|HCMPIX:\hcmpix8times:5:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X19_Y117_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:3:Top_HitCountMemPix|HCMPIX:\hcmpix8times:6:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X27_Y120_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:3:Top_HitCountMemPix|HCMPIX:\hcmpix8times:7:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X19_Y120_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:4:Top_HitCountMemPix|HCMPIX:\hcmpix8times:0:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X148_Y124_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:4:Top_HitCountMemPix|HCMPIX:\hcmpix8times:1:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X148_Y122_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:4:Top_HitCountMemPix|HCMPIX:\hcmpix8times:2:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X143_Y122_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:4:Top_HitCountMemPix|HCMPIX:\hcmpix8times:3:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X148_Y121_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:4:Top_HitCountMemPix|HCMPIX:\hcmpix8times:4:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X143_Y123_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:4:Top_HitCountMemPix|HCMPIX:\hcmpix8times:5:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X148_Y123_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:4:Top_HitCountMemPix|HCMPIX:\hcmpix8times:6:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X143_Y124_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:4:Top_HitCountMemPix|HCMPIX:\hcmpix8times:7:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X148_Y125_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:5:Top_HitCountMemPix|HCMPIX:\hcmpix8times:0:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X43_Y119_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:5:Top_HitCountMemPix|HCMPIX:\hcmpix8times:1:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X35_Y120_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:5:Top_HitCountMemPix|HCMPIX:\hcmpix8times:2:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X51_Y120_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:5:Top_HitCountMemPix|HCMPIX:\hcmpix8times:3:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X43_Y120_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:5:Top_HitCountMemPix|HCMPIX:\hcmpix8times:4:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X35_Y119_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:5:Top_HitCountMemPix|HCMPIX:\hcmpix8times:5:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X35_Y118_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:5:Top_HitCountMemPix|HCMPIX:\hcmpix8times:6:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X43_Y121_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmpixlayer:\HitCountMemPix:5:Top_HitCountMemPix|HCMPIX:\hcmpix8times:7:hcmpixsingle|altsyncram:altsyncram_component|altsyncram_tgs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 5 1024 5 yes no yes yes 5120 1024 5 1024 5 5120 1 0 None M10K_X43_Y118_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:0:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:0:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X143_Y12_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:0:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:1:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X130_Y13_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:0:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:2:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X130_Y14_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:0:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:3:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X130_Y11_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:0:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:4:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X130_Y12_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:0:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:5:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X130_Y9_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:0:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:6:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X130_Y10_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:0:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:7:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X130_Y8_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:1:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:0:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X162_Y109_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:1:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:1:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X162_Y108_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:1:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:2:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X162_Y110_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:1:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:3:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X148_Y112_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:1:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:4:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X162_Y111_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:1:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:5:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X162_Y112_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:1:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:6:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X162_Y113_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:1:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:7:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X148_Y111_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:2:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:0:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X130_Y118_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:2:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:1:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X143_Y114_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:2:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:2:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X120_Y114_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:2:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:3:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X130_Y116_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:2:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:4:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X120_Y116_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:2:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:5:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X130_Y114_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:2:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:6:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X120_Y115_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:2:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:7:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X143_Y112_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:3:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:0:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X51_Y10_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:3:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:1:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X51_Y9_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:3:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:2:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X51_Y8_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:3:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:3:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X43_Y11_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:3:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:4:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X43_Y14_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:3:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:5:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X43_Y9_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:3:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:6:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X43_Y13_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:3:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:7:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X43_Y12_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:4:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:0:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X101_Y130_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:4:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:1:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X96_Y131_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:4:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:2:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X101_Y131_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:4:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:3:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X101_Y132_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:4:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:4:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X111_Y130_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:4:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:5:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X111_Y131_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:4:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:6:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X111_Y129_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hcmsctlayer:\HitCountMemSCT:4:Top_HitCountMemSCT|HCMSCT:\hcmsct8times:7:hcmsctsingle|altsyncram:altsyncram_component|altsyncram_9hs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 3 2048 3 yes no yes yes 6144 2048 3 2048 3 6144 1 0 None M10K_X111_Y132_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 15 256 15 yes no no no 3840 256 15 256 15 3840 0 120 None LAB_X90_Y122_N0, LAB_X92_Y122_N0, LAB_X92_Y121_N0, LAB_X90_Y121_N0, LAB_X92_Y123_N0, LAB_X90_Y123_N0, LAB_X90_Y124_N0, LAB_X92_Y124_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 15 256 15 yes no no no 3840 256 15 256 15 3840 0 120 None LAB_X97_Y123_N0, LAB_X97_Y125_N0, LAB_X102_Y123_N0, LAB_X102_Y125_N0, LAB_X102_Y122_N0, LAB_X97_Y124_N0, LAB_X102_Y124_N0, LAB_X97_Y122_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 128 15 128 15 yes no no no 1920 128 15 128 15 1920 0 60 None LAB_X92_Y127_N0, LAB_X92_Y126_N0, LAB_X90_Y126_N0, LAB_X90_Y127_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 15 64 15 yes no no no 960 64 15 64 15 960 0 30 None LAB_X90_Y125_N0, LAB_X92_Y125_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|dpram_tmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 32 15 32 15 yes no no no 480 32 15 32 15 480 0 15 None LAB_X68_Y124_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|dpram_smb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 15 16 15 yes no no no 240 16 15 16 15 240 0 15 None LAB_X73_Y123_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|dpram_rmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 15 8 15 yes no no no 120 8 15 8 15 120 0 15 None LAB_X76_Y123_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|dpram_rmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 15 8 15 yes no no no 120 8 15 8 15 120 0 15 None LAB_X68_Y123_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 4 256 4 yes no no no 1024 256 4 256 4 1024 0 32 None LAB_X73_Y120_N0, LAB_X73_Y121_N0, LAB_X68_Y121_N0, LAB_X76_Y121_N0, LAB_X76_Y122_N0, LAB_X68_Y122_N0, LAB_X73_Y122_N0, LAB_X68_Y120_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 15 256 15 yes no no no 3840 256 15 256 15 3840 0 120 None LAB_X73_Y1_N0, LAB_X73_Y3_N0, LAB_X68_Y3_N0, LAB_X73_Y4_N0, LAB_X68_Y1_N0, LAB_X68_Y2_N0, LAB_X68_Y4_N0, LAB_X73_Y2_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 15 256 15 yes no no no 3840 256 15 256 15 3840 0 120 None LAB_X52_Y3_N0, LAB_X52_Y2_N0, LAB_X60_Y2_N0, LAB_X60_Y3_N0, LAB_X52_Y4_N0, LAB_X60_Y4_N0, LAB_X52_Y1_N0, LAB_X60_Y1_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 128 15 128 15 yes no no no 1920 128 15 128 15 1920 0 60 None LAB_X73_Y6_N0, LAB_X68_Y5_N0, LAB_X68_Y6_N0, LAB_X73_Y5_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 15 64 15 yes no no no 960 64 15 64 15 960 0 30 None LAB_X52_Y6_N0, LAB_X60_Y6_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|dpram_tmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 32 15 32 15 yes no no no 480 32 15 32 15 480 0 15 None LAB_X52_Y7_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|dpram_smb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 15 16 15 yes no no no 240 16 15 16 15 240 0 15 None LAB_X60_Y8_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|dpram_rmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 15 8 15 yes no no no 120 8 15 8 15 120 0 15 None LAB_X52_Y8_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|dpram_rmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 15 8 15 yes no no no 120 8 15 8 15 120 0 15 None LAB_X52_Y5_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 4 256 4 yes no no no 1024 256 4 256 4 1024 0 32 None LAB_X68_Y10_N0, LAB_X68_Y9_N0, LAB_X68_Y11_N0, LAB_X73_Y11_N0, LAB_X73_Y10_N0, LAB_X73_Y9_N0, LAB_X76_Y10_N0, LAB_X76_Y9_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 15 256 15 yes no no no 3840 256 15 256 15 3840 0 120 None LAB_X12_Y12_N0, LAB_X15_Y12_N0, LAB_X15_Y10_N0, LAB_X12_Y10_N0, LAB_X12_Y11_N0, LAB_X20_Y11_N0, LAB_X15_Y11_N0, LAB_X20_Y10_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 15 256 15 yes no no no 3840 256 15 256 15 3840 0 120 None LAB_X6_Y9_N0, LAB_X15_Y9_N0, LAB_X12_Y9_N0, LAB_X8_Y9_N0, LAB_X12_Y8_N0, LAB_X6_Y8_N0, LAB_X8_Y8_N0, LAB_X15_Y8_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 128 15 128 15 yes no no no 1920 128 15 128 15 1920 0 60 None LAB_X25_Y12_N0, LAB_X20_Y13_N0, LAB_X25_Y13_N0, LAB_X20_Y12_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 15 64 15 yes no no no 960 64 15 64 15 960 0 30 None LAB_X12_Y13_N0, LAB_X15_Y13_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|dpram_tmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 32 15 32 15 yes no no no 480 32 15 32 15 480 0 15 None LAB_X20_Y15_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|dpram_smb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 15 16 15 yes no no no 240 16 15 16 15 240 0 15 None LAB_X12_Y15_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|dpram_rmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 15 8 15 yes no no no 120 8 15 8 15 120 0 15 None LAB_X12_Y16_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|dpram_rmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 15 8 15 yes no no no 120 8 15 8 15 120 0 15 None LAB_X12_Y14_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 4 256 4 yes no no no 1024 256 4 256 4 1024 0 32 None LAB_X20_Y5_N0, LAB_X20_Y7_N0, LAB_X15_Y6_N0, LAB_X20_Y6_N0, LAB_X12_Y6_N0, LAB_X12_Y7_N0, LAB_X15_Y5_N0, LAB_X15_Y7_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 15 256 15 yes no no no 3840 256 15 256 15 3840 0 120 None LAB_X3_Y116_N0, LAB_X8_Y116_N0, LAB_X6_Y116_N0, LAB_X3_Y117_N0, LAB_X3_Y115_N0, LAB_X8_Y115_N0, LAB_X6_Y117_N0, LAB_X6_Y115_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 15 256 15 yes no no no 3840 256 15 256 15 3840 0 120 None LAB_X6_Y114_N0, LAB_X8_Y112_N0, LAB_X3_Y112_N0, LAB_X6_Y112_N0, LAB_X3_Y113_N0, LAB_X8_Y113_N0, LAB_X3_Y114_N0, LAB_X6_Y113_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 128 15 128 15 yes no no no 1920 128 15 128 15 1920 0 60 None LAB_X12_Y114_N0, LAB_X8_Y114_N0, LAB_X15_Y114_N0, LAB_X12_Y115_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 15 64 15 yes no no no 960 64 15 64 15 960 0 30 None LAB_X15_Y113_N0, LAB_X12_Y113_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|dpram_tmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 32 15 32 15 yes no no no 480 32 15 32 15 480 0 15 None LAB_X25_Y112_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|dpram_smb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 15 16 15 yes no no no 240 16 15 16 15 240 0 15 None LAB_X15_Y112_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|dpram_rmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 15 8 15 yes no no no 120 8 15 8 15 120 0 15 None LAB_X20_Y112_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|dpram_rmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 15 8 15 yes no no no 120 8 15 8 15 120 0 15 None LAB_X20_Y110_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 4 256 4 yes no no no 1024 256 4 256 4 1024 0 32 None LAB_X8_Y110_N0, LAB_X3_Y110_N0, LAB_X6_Y110_N0, LAB_X12_Y110_N0, LAB_X8_Y111_N0, LAB_X3_Y111_N0, LAB_X12_Y111_N0, LAB_X6_Y111_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 15 256 15 yes no no no 3840 256 15 256 15 3840 0 120 None LAB_X165_Y112_N0, LAB_X170_Y111_N0, LAB_X167_Y111_N0, LAB_X165_Y111_N0, LAB_X170_Y112_N0, LAB_X167_Y113_N0, LAB_X165_Y113_N0, LAB_X170_Y113_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 15 256 15 yes no no no 3840 256 15 256 15 3840 0 120 None LAB_X174_Y113_N0, LAB_X176_Y113_N0, LAB_X179_Y113_N0, LAB_X176_Y112_N0, LAB_X174_Y111_N0, LAB_X179_Y112_N0, LAB_X179_Y111_N0, LAB_X176_Y111_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 128 15 128 15 yes no no no 1920 128 15 128 15 1920 0 60 None LAB_X176_Y115_N0, LAB_X179_Y115_N0, LAB_X170_Y115_N0, LAB_X174_Y115_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 15 64 15 yes no no no 960 64 15 64 15 960 0 30 None LAB_X176_Y117_N0, LAB_X179_Y117_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|dpram_tmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 32 15 32 15 yes no no no 480 32 15 32 15 480 0 15 None LAB_X167_Y118_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|dpram_smb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 15 16 15 yes no no no 240 16 15 16 15 240 0 15 None LAB_X174_Y116_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|dpram_rmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 15 8 15 yes no no no 120 8 15 8 15 120 0 15 None LAB_X170_Y118_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|dpram_rmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 15 8 15 yes no no no 120 8 15 8 15 120 0 15 None LAB_X174_Y118_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 4 256 4 yes no no no 1024 256 4 256 4 1024 0 32 None LAB_X170_Y120_N0, LAB_X176_Y118_N0, LAB_X176_Y120_N0, LAB_X170_Y117_N0, LAB_X179_Y120_N0, LAB_X174_Y117_N0, LAB_X179_Y118_N0, LAB_X174_Y120_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 15 256 15 yes no no no 3840 256 15 256 15 3840 0 120 None LAB_X90_Y116_N0, LAB_X92_Y115_N0, LAB_X90_Y115_N0, LAB_X92_Y116_N0, LAB_X92_Y114_N0, LAB_X90_Y117_N0, LAB_X92_Y117_N0, LAB_X76_Y114_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 15 256 15 yes no no no 3840 256 15 256 15 3840 0 120 None LAB_X97_Y114_N0, LAB_X97_Y117_N0, LAB_X97_Y115_N0, LAB_X97_Y116_N0, LAB_X97_Y113_N0, LAB_X90_Y113_N0, LAB_X90_Y114_N0, LAB_X92_Y113_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 128 15 128 15 yes no no no 1920 128 15 128 15 1920 0 60 None LAB_X90_Y120_N0, LAB_X92_Y120_N0, LAB_X92_Y119_N0, LAB_X90_Y119_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 15 64 15 yes no no no 960 64 15 64 15 960 0 30 None LAB_X92_Y118_N0, LAB_X90_Y118_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|dpram_tmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 32 15 32 15 yes no no no 480 32 15 32 15 480 0 15 None LAB_X76_Y115_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|dpram_smb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 15 16 15 yes no no no 240 16 15 16 15 240 0 15 None LAB_X68_Y115_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|dpram_rmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 15 8 15 yes no no no 120 8 15 8 15 120 0 15 None LAB_X73_Y115_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|dpram_rmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 15 8 15 yes no no no 120 8 15 8 15 120 0 15 None LAB_X73_Y116_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 4 256 4 yes no no no 1024 256 4 256 4 1024 0 32 None LAB_X105_Y120_N0, LAB_X105_Y121_N0, LAB_X105_Y119_N0, LAB_X102_Y119_N0, LAB_X102_Y120_N0, LAB_X97_Y119_N0, LAB_X97_Y120_N0, LAB_X97_Y121_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 13 256 13 yes no no no 3328 256 13 256 13 3328 0 104 None LAB_X167_Y9_N0, LAB_X170_Y9_N0, LAB_X165_Y9_N0, LAB_X167_Y11_N0, LAB_X170_Y10_N0, LAB_X167_Y10_N0, LAB_X165_Y10_N0, LAB_X170_Y11_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 13 256 13 yes no no no 3328 256 13 256 13 3328 0 104 None LAB_X174_Y7_N0, LAB_X179_Y9_N0, LAB_X174_Y9_N0, LAB_X176_Y9_N0, LAB_X176_Y7_N0, LAB_X174_Y8_N0, LAB_X179_Y8_N0, LAB_X176_Y8_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 128 13 128 13 yes no no no 1664 128 13 128 13 1664 0 52 None LAB_X167_Y5_N0, LAB_X176_Y5_N0, LAB_X174_Y5_N0, LAB_X170_Y5_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|dpram_3nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 13 64 13 yes no no no 832 64 13 64 13 832 0 26 None LAB_X167_Y7_N0, LAB_X170_Y7_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|dpram_4nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 32 13 32 13 yes no no no 416 32 13 32 13 416 0 13 None LAB_X154_Y4_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|dpram_qmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 13 16 13 yes no no no 208 16 13 16 13 208 0 13 None LAB_X165_Y8_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|dpram_pmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 13 8 13 yes no no no 104 8 13 8 13 104 0 13 None LAB_X167_Y6_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|dpram_pmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 13 8 13 yes no no no 104 8 13 8 13 104 0 13 None LAB_X165_Y6_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 4 256 4 yes no no no 1024 256 4 256 4 1024 0 32 None LAB_X170_Y4_N0, LAB_X174_Y4_N0, LAB_X167_Y4_N0, LAB_X165_Y4_N0, LAB_X170_Y3_N0, LAB_X167_Y3_N0, LAB_X174_Y3_N0, LAB_X165_Y3_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|altshift_taps:analyze_sync1_rtl_0|shift_taps_vnu:auto_generated|altsyncram_nk91:altsyncram4|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 8 11 8 11 yes no yes yes 88 8 11 8 11 88 1 0 None M10K_X101_Y114_N0 Don't care New data New data Yes
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|altshift_taps:roadEE_sync3_rtl_0|shift_taps_unu:auto_generated|altsyncram_lk91:altsyncram5|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 5 22 5 22 yes no yes yes 110 5 22 5 22 110 1 0 None M10K_X120_Y112_N0 Don't care New data New data Yes
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 13 256 13 yes no no no 3328 256 13 256 13 3328 0 104 None LAB_X174_Y101_N0, LAB_X176_Y101_N0, LAB_X176_Y102_N0, LAB_X179_Y101_N0, LAB_X176_Y103_N0, LAB_X174_Y103_N0, LAB_X179_Y103_N0, LAB_X174_Y102_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 13 256 13 yes no no no 3328 256 13 256 13 3328 0 104 None LAB_X165_Y101_N0, LAB_X167_Y101_N0, LAB_X170_Y101_N0, LAB_X170_Y102_N0, LAB_X165_Y103_N0, LAB_X170_Y103_N0, LAB_X167_Y103_N0, LAB_X165_Y102_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 128 13 128 13 yes no no no 1664 128 13 128 13 1664 0 52 None LAB_X179_Y107_N0, LAB_X179_Y108_N0, LAB_X176_Y108_N0, LAB_X174_Y108_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|dpram_3nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 13 64 13 yes no no no 832 64 13 64 13 832 0 26 None LAB_X176_Y105_N0, LAB_X179_Y105_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|dpram_4nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 32 13 32 13 yes no no no 416 32 13 32 13 416 0 13 None LAB_X179_Y106_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|dpram_qmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 13 16 13 yes no no no 208 16 13 16 13 208 0 13 None LAB_X167_Y104_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|dpram_pmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 13 8 13 yes no no no 104 8 13 8 13 104 0 13 None LAB_X176_Y104_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|dpram_pmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 13 8 13 yes no no no 104 8 13 8 13 104 0 13 None LAB_X170_Y104_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 4 256 4 yes no no no 1024 256 4 256 4 1024 0 32 None LAB_X170_Y110_N0, LAB_X170_Y109_N0, LAB_X174_Y109_N0, LAB_X174_Y110_N0, LAB_X179_Y110_N0, LAB_X176_Y109_N0, LAB_X179_Y109_N0, LAB_X176_Y110_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 13 256 13 yes no no no 3328 256 13 256 13 3328 0 104 None LAB_X179_Y121_N0, LAB_X170_Y121_N0, LAB_X176_Y121_N0, LAB_X174_Y121_N0, LAB_X174_Y119_N0, LAB_X179_Y119_N0, LAB_X170_Y119_N0, LAB_X176_Y119_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 13 256 13 yes no no no 3328 256 13 256 13 3328 0 104 None LAB_X176_Y122_N0, LAB_X174_Y122_N0, LAB_X179_Y122_N0, LAB_X170_Y122_N0, LAB_X174_Y123_N0, LAB_X179_Y123_N0, LAB_X170_Y123_N0, LAB_X176_Y123_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 128 13 128 13 yes no no no 1664 128 13 128 13 1664 0 52 None LAB_X165_Y121_N0, LAB_X167_Y121_N0, LAB_X165_Y122_N0, LAB_X167_Y122_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|dpram_3nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 13 64 13 yes no no no 832 64 13 64 13 832 0 26 None LAB_X165_Y123_N0, LAB_X167_Y123_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|dpram_4nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 32 13 32 13 yes no no no 416 32 13 32 13 416 0 13 None LAB_X154_Y123_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|dpram_qmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 13 16 13 yes no no no 208 16 13 16 13 208 0 13 None LAB_X167_Y119_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|dpram_pmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 13 8 13 yes no no no 104 8 13 8 13 104 0 13 None LAB_X151_Y119_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|dpram_pmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 13 8 13 yes no no no 104 8 13 8 13 104 0 13 None LAB_X165_Y119_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 4 256 4 yes no no no 1024 256 4 256 4 1024 0 32 None LAB_X167_Y124_N0, LAB_X165_Y124_N0, LAB_X170_Y124_N0, LAB_X170_Y125_N0, LAB_X174_Y125_N0, LAB_X176_Y124_N0, LAB_X176_Y125_N0, LAB_X174_Y124_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 13 256 13 yes no no no 3328 256 13 256 13 3328 0 104 None LAB_X102_Y8_N0, LAB_X102_Y7_N0, LAB_X105_Y7_N0, LAB_X105_Y8_N0, LAB_X105_Y9_N0, LAB_X105_Y10_N0, LAB_X102_Y9_N0, LAB_X102_Y10_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 13 256 13 yes no no no 3328 256 13 256 13 3328 0 104 None LAB_X121_Y10_N0, LAB_X121_Y9_N0, LAB_X113_Y9_N0, LAB_X113_Y10_N0, LAB_X113_Y7_N0, LAB_X113_Y8_N0, LAB_X121_Y7_N0, LAB_X121_Y8_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 128 13 128 13 yes no no no 1664 128 13 128 13 1664 0 52 None LAB_X92_Y9_N0, LAB_X92_Y8_N0, LAB_X97_Y8_N0, LAB_X90_Y8_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|dpram_3nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 13 64 13 yes no no no 832 64 13 64 13 832 0 26 None LAB_X102_Y12_N0, LAB_X97_Y12_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|dpram_4nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 32 13 32 13 yes no no no 416 32 13 32 13 416 0 13 None LAB_X105_Y11_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|dpram_qmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 13 16 13 yes no no no 208 16 13 16 13 208 0 13 None LAB_X102_Y11_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|dpram_pmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 13 8 13 yes no no no 104 8 13 8 13 104 0 13 None LAB_X97_Y14_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|dpram_pmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 13 8 13 yes no no no 104 8 13 8 13 104 0 13 None LAB_X97_Y13_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 4 256 4 yes no no no 1024 256 4 256 4 1024 0 32 None LAB_X90_Y5_N0, LAB_X90_Y6_N0, LAB_X92_Y7_N0, LAB_X90_Y7_N0, LAB_X92_Y5_N0, LAB_X97_Y5_N0, LAB_X92_Y6_N0, LAB_X97_Y7_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 13 256 13 yes no no no 3328 256 13 256 13 3328 0 104 None LAB_X92_Y134_N0, LAB_X97_Y135_N0, LAB_X90_Y135_N0, LAB_X92_Y135_N0, LAB_X97_Y134_N0, LAB_X97_Y133_N0, LAB_X90_Y133_N0, LAB_X92_Y133_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 13 256 13 yes no no no 3328 256 13 256 13 3328 0 104 None LAB_X105_Y133_N0, LAB_X102_Y134_N0, LAB_X102_Y133_N0, LAB_X105_Y134_N0, LAB_X105_Y135_N0, LAB_X102_Y136_N0, LAB_X102_Y135_N0, LAB_X105_Y136_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 128 13 128 13 yes no no no 1664 128 13 128 13 1664 0 52 None LAB_X97_Y132_N0, LAB_X105_Y132_N0, LAB_X102_Y132_N0, LAB_X102_Y131_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|dpram_3nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 13 64 13 yes no no no 832 64 13 64 13 832 0 26 None LAB_X92_Y132_N0, LAB_X90_Y132_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|dpram_4nb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 32 13 32 13 yes no no no 416 32 13 32 13 416 0 13 None LAB_X90_Y131_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|dpram_qmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 13 16 13 yes no no no 208 16 13 16 13 208 0 13 None LAB_X90_Y129_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|dpram_pmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 13 8 13 yes no no no 104 8 13 8 13 104 0 13 None LAB_X92_Y131_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|dpram_pmb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 8 13 8 13 yes no no no 104 8 13 8 13 104 0 13 None LAB_X90_Y128_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 256 4 256 4 yes no no no 1024 256 4 256 4 1024 0 32 None LAB_X73_Y131_N0, LAB_X73_Y130_N0, LAB_X76_Y130_N0, LAB_X68_Y130_N0, LAB_X76_Y132_N0, LAB_X73_Y132_N0, LAB_X68_Y132_N0, LAB_X68_Y131_N0        
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:0:Top_HitListPointerPIX|HLPPIX:\hlppix8times:0:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X67_Y129_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:0:Top_HitListPointerPIX|HLPPIX:\hlppix8times:1:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X67_Y126_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:0:Top_HitListPointerPIX|HLPPIX:\hlppix8times:2:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X51_Y128_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:0:Top_HitListPointerPIX|HLPPIX:\hlppix8times:3:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X59_Y128_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:0:Top_HitListPointerPIX|HLPPIX:\hlppix8times:4:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X51_Y127_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:0:Top_HitListPointerPIX|HLPPIX:\hlppix8times:5:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X67_Y128_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:0:Top_HitListPointerPIX|HLPPIX:\hlppix8times:6:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X59_Y126_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:0:Top_HitListPointerPIX|HLPPIX:\hlppix8times:7:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X51_Y126_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:1:Top_HitListPointerPIX|HLPPIX:\hlppix8times:0:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X75_Y7_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:1:Top_HitListPointerPIX|HLPPIX:\hlppix8times:1:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X75_Y5_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:1:Top_HitListPointerPIX|HLPPIX:\hlppix8times:2:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X75_Y6_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:1:Top_HitListPointerPIX|HLPPIX:\hlppix8times:3:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X67_Y6_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:1:Top_HitListPointerPIX|HLPPIX:\hlppix8times:4:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X75_Y1_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:1:Top_HitListPointerPIX|HLPPIX:\hlppix8times:5:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X75_Y2_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:1:Top_HitListPointerPIX|HLPPIX:\hlppix8times:6:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X75_Y3_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:1:Top_HitListPointerPIX|HLPPIX:\hlppix8times:7:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X75_Y4_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:2:Top_HitListPointerPIX|HLPPIX:\hlppix8times:0:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X27_Y20_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:2:Top_HitListPointerPIX|HLPPIX:\hlppix8times:1:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X19_Y21_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:2:Top_HitListPointerPIX|HLPPIX:\hlppix8times:2:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X27_Y18_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:2:Top_HitListPointerPIX|HLPPIX:\hlppix8times:3:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X19_Y20_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:2:Top_HitListPointerPIX|HLPPIX:\hlppix8times:4:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X27_Y21_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:2:Top_HitListPointerPIX|HLPPIX:\hlppix8times:5:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X19_Y22_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:2:Top_HitListPointerPIX|HLPPIX:\hlppix8times:6:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X19_Y19_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:2:Top_HitListPointerPIX|HLPPIX:\hlppix8times:7:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X27_Y19_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:3:Top_HitListPointerPIX|HLPPIX:\hlppix8times:0:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X5_Y119_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:3:Top_HitListPointerPIX|HLPPIX:\hlppix8times:1:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X5_Y118_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:3:Top_HitListPointerPIX|HLPPIX:\hlppix8times:2:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X27_Y121_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:3:Top_HitListPointerPIX|HLPPIX:\hlppix8times:3:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X5_Y117_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:3:Top_HitListPointerPIX|HLPPIX:\hlppix8times:4:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X19_Y122_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:3:Top_HitListPointerPIX|HLPPIX:\hlppix8times:5:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X27_Y119_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:3:Top_HitListPointerPIX|HLPPIX:\hlppix8times:6:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X19_Y119_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:3:Top_HitListPointerPIX|HLPPIX:\hlppix8times:7:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X27_Y118_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:4:Top_HitListPointerPIX|HLPPIX:\hlppix8times:0:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X148_Y114_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:4:Top_HitListPointerPIX|HLPPIX:\hlppix8times:1:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X162_Y114_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:4:Top_HitListPointerPIX|HLPPIX:\hlppix8times:2:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X143_Y113_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:4:Top_HitListPointerPIX|HLPPIX:\hlppix8times:3:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X162_Y116_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:4:Top_HitListPointerPIX|HLPPIX:\hlppix8times:4:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X148_Y116_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:4:Top_HitListPointerPIX|HLPPIX:\hlppix8times:5:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X162_Y115_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:4:Top_HitListPointerPIX|HLPPIX:\hlppix8times:6:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X162_Y117_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:4:Top_HitListPointerPIX|HLPPIX:\hlppix8times:7:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X148_Y113_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:5:Top_HitListPointerPIX|HLPPIX:\hlppix8times:0:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X51_Y121_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:5:Top_HitListPointerPIX|HLPPIX:\hlppix8times:1:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X59_Y120_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:5:Top_HitListPointerPIX|HLPPIX:\hlppix8times:2:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X51_Y123_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:5:Top_HitListPointerPIX|HLPPIX:\hlppix8times:3:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X59_Y121_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:5:Top_HitListPointerPIX|HLPPIX:\hlppix8times:4:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X59_Y122_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:5:Top_HitListPointerPIX|HLPPIX:\hlppix8times:5:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X51_Y122_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:5:Top_HitListPointerPIX|HLPPIX:\hlppix8times:6:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X43_Y122_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlppixlayer:\HitListPointerPix:5:Top_HitListPointerPIX|HLPPIX:\hlppix8times:7:hlppixsingle|altsyncram:altsyncram_component|altsyncram_ljs1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 10 1024 10 yes no yes yes 10240 1024 10 1024 10 10240 1 0 None M10K_X51_Y119_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:0:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:0:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X143_Y11_N0, M10K_X148_Y11_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:0:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:1:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X143_Y10_N0, M10K_X148_Y10_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:0:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:2:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X148_Y13_N0, M10K_X143_Y13_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:0:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:3:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X148_Y12_N0, M10K_X148_Y15_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:0:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:4:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X143_Y9_N0, M10K_X143_Y8_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:0:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:5:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X148_Y14_N0, M10K_X143_Y14_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:0:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:6:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X143_Y15_N0, M10K_X143_Y17_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:0:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:7:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X148_Y9_N0, M10K_X148_Y8_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:1:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:0:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X162_Y106_N0, M10K_X162_Y105_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:1:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:1:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X143_Y106_N0, M10K_X148_Y106_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:1:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:2:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X148_Y105_N0, M10K_X143_Y105_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:1:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:3:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X148_Y109_N0, M10K_X143_Y109_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:1:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:4:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X143_Y107_N0, M10K_X148_Y110_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:1:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:5:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X148_Y108_N0, M10K_X143_Y108_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:1:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:6:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X148_Y104_N0, M10K_X148_Y107_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:1:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:7:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X162_Y107_N0, M10K_X162_Y104_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:2:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:0:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X130_Y113_N0, M10K_X130_Y112_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:2:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:1:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X143_Y118_N0, M10K_X148_Y118_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:2:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:2:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X143_Y121_N0, M10K_X143_Y117_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:2:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:3:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X148_Y117_N0, M10K_X143_Y116_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:2:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:4:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X143_Y120_N0, M10K_X148_Y120_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:2:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:5:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X148_Y119_N0, M10K_X143_Y119_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:2:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:6:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X130_Y120_N0, M10K_X130_Y119_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:2:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:7:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X148_Y115_N0, M10K_X143_Y115_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:3:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:0:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X75_Y10_N0, M10K_X67_Y10_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:3:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:1:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X59_Y13_N0, M10K_X51_Y13_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:3:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:2:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X59_Y10_N0, M10K_X59_Y9_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:3:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:3:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X59_Y11_N0, M10K_X51_Y11_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:3:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:4:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X51_Y14_N0, M10K_X51_Y12_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:3:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:5:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X59_Y12_N0, M10K_X59_Y14_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:3:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:6:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X67_Y13_N0, M10K_X67_Y12_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:3:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:7:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X75_Y11_N0, M10K_X67_Y11_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:4:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:0:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X96_Y127_N0, M10K_X101_Y127_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:4:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:1:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X111_Y126_N0, M10K_X111_Y127_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:4:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:2:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X101_Y126_N0, M10K_X96_Y126_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:4:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:3:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X96_Y125_N0, M10K_X101_Y125_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:4:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:4:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X101_Y122_N0, M10K_X101_Y123_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:4:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:5:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X96_Y129_N0, M10K_X101_Y129_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:4:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:6:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X111_Y125_N0, M10K_X111_Y124_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DO11L:b2v_inst|hlpsctlayer:\HitListPointerSCT:4:Top_HitListPointerSCT|HLPSCT:\hlpsct8times:7:hlpsctsingle|altsyncram:altsyncram_component|altsyncram_5ks1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 10 2048 10 yes no yes yes 20480 2048 10 2048 10 20480 2 0 None M10K_X101_Y128_N0, M10K_X111_Y128_N0 Don't care New data New data No - Address Too Wide
DataOrganizer:inst129|DOPrepAMInput:PrepAMInput_inst|fifo_32_to_256:VMEAMCBUFFER|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_ual1:auto_generated|altsyncram_m271:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 128 256 yes no yes yes 32768 1024 32 128 256 32768 7 0 None M10K_X43_Y18_N0, M10K_X51_Y16_N0, M10K_X51_Y15_N0, M10K_X43_Y17_N0, M10K_X51_Y18_N0, M10K_X51_Y17_N0, M10K_X43_Y15_N0 Don't care New data New data No - Mixed Width
DataOrganizer:inst129|ammapintram:b2v_inst4|roadFIFO:roadFIFO_inst|scfifo:scfifo_component|scfifo_3nb1:auto_generated|a_dpfifo_rr81:dpfifo|altsyncram_3uj1:FIFOram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 32 32 32 32 yes no yes yes 1024 32 9 32 9 288 1 0 None M10K_X67_Y106_N0 Don't care New data New data Yes
DataOrganizer:inst129|dcfifo:dcfifo_DOReadExtMem_inst|dcfifo_35l1:auto_generated|altsyncram_vn41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 32 10 32 10 yes no yes no 320 32 10 32 10 320 1 0 None M10K_X51_Y24_N0 Don't care New data New data No - Read Address Using Clock 1 on Port B
DataOrganizer:inst129|dcfifo:dcfifo_DOWriteExtMem_inst|dcfifo_4fk1:auto_generated|altsyncram_hr41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 32 154 32 154 yes no yes no 4928 32 154 32 154 4928 4 0 None M10K_X51_Y20_N0, M10K_X59_Y17_N0, M10K_X59_Y18_N0, M10K_X59_Y15_N0 Don't care New data New data No - Read Address Using Clock 1 on Port B
DataOrganizer:inst129|dcfifo:dcfifo_ExtMemDO_inst|dcfifo_j8l1:auto_generated|altsyncram_fr41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 32 144 32 144 yes no yes yes 4608 32 144 32 144 4608 4 0 None M10K_X59_Y24_N0, M10K_X75_Y21_N0, M10K_X75_Y22_N0, M10K_X75_Y19_N0 Don't care New data New data No - Read Address Using Clock 1 on Port B
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:0:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X178_Y100_N0, M10K_X178_Y97_N0 Don't care New data New data No - Address Too Wide
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:1:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X130_Y94_N0, M10K_X120_Y94_N0 Don't care New data New data No - Address Too Wide
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:2:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X162_Y90_N0, M10K_X162_Y89_N0 Don't care New data New data No - Address Too Wide
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:3:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X143_Y76_N0, M10K_X130_Y76_N0 Don't care New data New data No - Address Too Wide
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:4:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X148_Y96_N0, M10K_X143_Y96_N0 Don't care New data New data No - Address Too Wide
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:5:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X143_Y78_N0, M10K_X148_Y78_N0 Don't care New data New data No - Address Too Wide
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:0:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X43_Y22_N0, M10K_X35_Y22_N0 Don't care New data New data No - Address Too Wide
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:1:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X19_Y40_N0, M10K_X27_Y40_N0 Don't care New data New data No - Address Too Wide
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:2:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X27_Y32_N0, M10K_X19_Y32_N0 Don't care New data New data No - Address Too Wide
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:3:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X59_Y88_N0, M10K_X59_Y87_N0 Don't care New data New data No - Address Too Wide
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:4:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X101_Y36_N0, M10K_X96_Y36_N0 Don't care New data New data No - Address Too Wide
NewAMBRoundRobin:round_robin_inst|fifo_32_to_32_forDO:VMEAMCBUFFER|dcfifo:dcfifo_component|dcfifo_gal1:auto_generated|altsyncram_8271:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes yes 32768 1024 32 1024 32 32768 4 0 None M10K_X35_Y35_N0, M10K_X35_Y36_N0, M10K_X27_Y37_N0, M10K_X27_Y34_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|av_xrbasic_l2p_rom:l2pch|altsyncram:rom_l2p_ch_rtl_0|altsyncram_e812:auto_generated|ALTSYNCRAM M10K block True Dual Port Single Clock 128 32 128 32 yes no yes no 4096 128 32 128 32 4096 2 0 db/reconfig_map_0.mif M10K_X5_Y55_N0, M10K_X5_Y54_N0 Don't care New data New data Yes
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|av_xrbasic_l2p_rom:l2pch|altsyncram:rom_l2p_ch_rtl_0|altsyncram_7712:auto_generated|ALTSYNCRAM M10K block True Dual Port Single Clock 128 32 128 32 yes no yes no 4096 128 32 128 32 4096 2 0 db/reconfig_map_1.mif M10K_X162_Y18_N0, M10K_X162_Y21_N0 Don't care New data New data Yes
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|SimpleSimplexLDC:ldc_inst|dcfifo:fifo_inst|dcfifo_8ol1:auto_generated|altsyncram_ej91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes yes 16896 512 32 512 32 16384 2 0 None M10K_X5_Y49_N0, M10K_X5_Y48_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|SimpleSimplexLSC:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|altsyncram_qv61:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes yes 16896 512 33 512 33 16896 2 0 None M10K_X5_Y46_N0, M10K_X5_Y47_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|altsyncram_ul91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 33 1024 33 yes no yes yes 33792 1024 33 1024 33 33792 4 0 None M10K_X35_Y18_N0, M10K_X35_Y17_N0, M10K_X35_Y20_N0, M10K_X35_Y16_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|altsyncram_ul91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 33 1024 33 yes no yes yes 33792 1024 33 1024 33 33792 4 0 None M10K_X5_Y40_N0, M10K_X5_Y38_N0, M10K_X5_Y39_N0, M10K_X5_Y41_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|altsyncram_ul91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 33 1024 33 yes no yes yes 33792 1024 33 1024 33 33792 4 0 None M10K_X5_Y29_N0, M10K_X19_Y28_N0, M10K_X5_Y28_N0, M10K_X19_Y29_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|altsyncram_ul91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 33 1024 33 yes no yes yes 33792 1024 33 1024 33 33792 4 0 None M10K_X5_Y45_N0, M10K_X5_Y44_N0, M10K_X5_Y43_N0, M10K_X5_Y42_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:0:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|altsyncram_qv61:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes yes 16896 512 33 512 33 16896 2 0 None M10K_X5_Y3_N0, M10K_X5_Y4_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:1:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|altsyncram_qv61:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes yes 16896 512 33 512 33 16896 2 0 None M10K_X5_Y37_N0, M10K_X5_Y36_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:2:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|altsyncram_qv61:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes yes 16896 512 33 512 33 16896 2 0 None M10K_X5_Y27_N0, M10K_X19_Y27_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:3:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|altsyncram_qv61:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes yes 16896 512 33 512 33 16896 2 0 None M10K_X5_Y34_N0, M10K_X5_Y35_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|altsyncram_ul91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 33 1024 33 yes no yes yes 33792 1024 33 1024 33 33792 4 0 None M10K_X148_Y21_N0, M10K_X148_Y20_N0, M10K_X143_Y20_N0, M10K_X143_Y21_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|altsyncram_ul91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 33 1024 33 yes no yes yes 33792 1024 33 1024 33 33792 4 0 None M10K_X178_Y30_N0, M10K_X178_Y29_N0, M10K_X178_Y31_N0, M10K_X178_Y28_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|altsyncram_ul91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 33 1024 33 yes no yes yes 33792 1024 33 1024 33 33792 4 0 None M10K_X178_Y37_N0, M10K_X178_Y38_N0, M10K_X178_Y39_N0, M10K_X178_Y40_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|altsyncram_ul91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 33 1024 33 yes no yes yes 33792 1024 33 1024 33 33792 4 0 None M10K_X178_Y59_N0, M10K_X178_Y61_N0, M10K_X178_Y58_N0, M10K_X178_Y60_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:0:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|altsyncram_qv61:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes yes 16896 512 33 512 33 16896 2 0 None M10K_X162_Y12_N0, M10K_X162_Y13_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:1:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|altsyncram_qv61:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes yes 16896 512 33 512 33 16896 2 0 None M10K_X148_Y18_N0, M10K_X143_Y18_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:2:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|altsyncram_qv61:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes yes 16896 512 33 512 33 16896 2 0 None M10K_X178_Y47_N0, M10K_X178_Y46_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:3:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|altsyncram_qv61:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes yes 16896 512 33 512 33 16896 2 0 None M10K_X178_Y45_N0, M10K_X178_Y44_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|altsyncram_ul91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 33 1024 33 yes no yes yes 33792 1024 33 1024 33 33792 4 0 None M10K_X178_Y64_N0, M10K_X178_Y65_N0, M10K_X178_Y62_N0, M10K_X178_Y63_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|altsyncram_ul91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 33 1024 33 yes no yes yes 33792 1024 33 1024 33 33792 4 0 None M10K_X178_Y52_N0, M10K_X162_Y52_N0, M10K_X162_Y53_N0, M10K_X178_Y53_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|altsyncram_ul91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 33 1024 33 yes no yes yes 33792 1024 33 1024 33 33792 4 0 None M10K_X162_Y62_N0, M10K_X162_Y63_N0, M10K_X162_Y60_N0, M10K_X162_Y61_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|altsyncram_ul91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 33 1024 33 yes no yes yes 33792 1024 32 1024 32 32768 4 0 None M10K_X148_Y72_N0, M10K_X148_Y71_N0, M10K_X143_Y72_N0, M10K_X143_Y71_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:0:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|altsyncram_qv61:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes yes 16896 512 33 512 33 16896 2 0 None M10K_X178_Y56_N0, M10K_X178_Y57_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:1:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|altsyncram_qv61:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes yes 16896 512 33 512 33 16896 2 0 None M10K_X178_Y36_N0, M10K_X178_Y35_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:2:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|altsyncram_qv61:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes yes 16896 512 33 512 33 16896 2 0 None M10K_X178_Y1_N0, M10K_X178_Y3_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:3:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|altsyncram_qv61:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes yes 16896 512 33 512 33 16896 2 0 None M10K_X178_Y69_N0, M10K_X178_Y70_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|dcfifo:fifo_inst|dcfifo_gsl1:auto_generated|altsyncram_0m91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 33 2048 33 yes no yes yes 67584 2048 33 2048 33 67584 7 0 None M10K_X5_Y83_N0, M10K_X5_Y87_N0, M10K_X5_Y82_N0, M10K_X5_Y86_N0, M10K_X5_Y85_N0, M10K_X5_Y84_N0, M10K_X5_Y88_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|dcfifo:fifo_inst|dcfifo_gsl1:auto_generated|altsyncram_0m91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 33 2048 33 yes no yes yes 67584 2048 33 2048 33 67584 7 0 None M10K_X5_Y64_N0, M10K_X5_Y60_N0, M10K_X5_Y62_N0, M10K_X5_Y63_N0, M10K_X5_Y61_N0, M10K_X5_Y65_N0, M10K_X5_Y66_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|dcfifo:fifo_inst|dcfifo_gsl1:auto_generated|altsyncram_0m91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 33 2048 33 yes no yes yes 67584 2048 33 2048 33 67584 7 0 None M10K_X5_Y72_N0, M10K_X19_Y69_N0, M10K_X19_Y71_N0, M10K_X5_Y71_N0, M10K_X5_Y69_N0, M10K_X19_Y70_N0, M10K_X5_Y70_N0 Don't care New data New data No - Address Too Wide
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|dcfifo:fifo_inst|dcfifo_gsl1:auto_generated|altsyncram_0m91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 33 2048 33 yes no yes yes 67584 2048 33 2048 33 67584 7 0 None M10K_X19_Y11_N0, M10K_X27_Y11_N0, M10K_X19_Y9_N0, M10K_X19_Y8_N0, M10K_X27_Y8_N0, M10K_X19_Y10_N0, M10K_X27_Y10_N0 Don't care New data New data No - Address Too Wide
TFBlock:inst2|TFProcessVMEInputConsts:INPUTPROCESSORCONSTS|fifo_32_to_64:VMECONSTSBUFFER|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_o6l1:auto_generated|altsyncram_rv61:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 256 32 128 64 yes no yes yes 8192 256 32 128 64 8192 2 0 None M10K_X96_Y38_N0, M10K_X96_Y37_N0 Don't care New data New data No - Mixed Width
TFBlock:inst2|TFProcessVMEOutput:OUTPUTPROCESSOR|fifo_32_to_32_clockinterface:SLOWCONSTSFIFO|dcfifo:dcfifo_component|dcfifo_g6l1:auto_generated|altsyncram_kv61:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 128 32 128 32 yes no yes yes 4096 128 32 128 32 4096 1 0 None M10K_X43_Y54_N0 Don't care New data New data No - Read Address Using Clock 1 on Port B
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:0:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X120_Y50_N0, M10K_X120_Y52_N0, M10K_X120_Y51_N0, M10K_X111_Y48_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:0:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X120_Y48_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:10:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X148_Y56_N0, M10K_X143_Y57_N0, M10K_X143_Y59_N0, M10K_X148_Y57_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:10:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X148_Y54_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:11:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X75_Y35_N0, M10K_X75_Y39_N0, M10K_X101_Y39_N0, M10K_X101_Y37_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:11:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X96_Y39_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:12:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X101_Y40_N0, M10K_X111_Y38_N0, M10K_X111_Y37_N0, M10K_X111_Y39_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:12:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X111_Y40_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:13:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X101_Y42_N0, M10K_X96_Y45_N0, M10K_X96_Y43_N0, M10K_X101_Y45_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:13:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X96_Y42_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:14:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X111_Y42_N0, M10K_X101_Y41_N0, M10K_X96_Y41_N0, M10K_X120_Y37_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:14:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X111_Y41_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:15:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X75_Y36_N0, M10K_X75_Y37_N0, M10K_X75_Y40_N0, M10K_X101_Y38_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:15:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X96_Y40_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:16:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X120_Y43_N0, M10K_X120_Y42_N0, M10K_X120_Y45_N0, M10K_X120_Y44_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:16:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X120_Y41_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:17:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X130_Y46_N0, M10K_X143_Y44_N0, M10K_X130_Y43_N0, M10K_X143_Y45_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:17:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X130_Y44_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:18:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X130_Y47_N0, M10K_X130_Y49_N0, M10K_X148_Y49_N0, M10K_X143_Y49_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:18:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X130_Y45_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:19:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X148_Y48_N0, M10K_X148_Y51_N0, M10K_X143_Y48_N0, M10K_X143_Y51_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:19:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X130_Y48_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:1:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X148_Y55_N0, M10K_X143_Y55_N0, M10K_X148_Y53_N0, M10K_X143_Y53_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:1:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X148_Y52_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:20:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X111_Y45_N0, M10K_X111_Y43_N0, M10K_X101_Y44_N0, M10K_X101_Y43_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:20:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X111_Y44_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:21:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X111_Y46_N0, M10K_X101_Y47_N0, M10K_X96_Y46_N0, M10K_X96_Y44_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:21:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X101_Y46_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:22:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X59_Y42_N0, M10K_X67_Y42_N0, M10K_X75_Y38_N0, M10K_X59_Y36_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:22:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X75_Y42_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:23:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X67_Y36_N0, M10K_X67_Y35_N0, M10K_X67_Y39_N0, M10K_X67_Y38_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:23:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X67_Y40_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:24:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X59_Y37_N0, M10K_X59_Y35_N0, M10K_X59_Y41_N0, M10K_X59_Y38_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:24:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X59_Y39_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:25:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X67_Y41_N0, M10K_X75_Y43_N0, M10K_X67_Y37_N0, M10K_X67_Y43_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:25:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X75_Y41_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:26:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X51_Y36_N0, M10K_X51_Y35_N0, M10K_X51_Y39_N0, M10K_X51_Y38_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:26:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X59_Y40_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:27:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X75_Y45_N0, M10K_X67_Y46_N0, M10K_X59_Y46_N0, M10K_X75_Y44_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:27:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X75_Y46_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:28:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X111_Y49_N0, M10K_X75_Y49_N0, M10K_X75_Y47_N0, M10K_X111_Y50_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:28:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X96_Y49_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:29:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X96_Y51_N0, M10K_X96_Y47_N0, M10K_X101_Y50_N0, M10K_X101_Y48_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:29:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X96_Y48_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:2:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X120_Y49_N0, M10K_X120_Y46_N0, M10K_X111_Y51_N0, M10K_X120_Y47_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:2:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X111_Y47_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:30:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X111_Y52_N0, M10K_X96_Y52_N0, M10K_X101_Y49_N0, M10K_X101_Y51_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:30:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X101_Y52_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:31:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X111_Y53_N0, M10K_X101_Y53_N0, M10K_X111_Y70_N0, M10K_X101_Y56_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:31:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X96_Y56_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:32:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X96_Y58_N0, M10K_X67_Y62_N0, M10K_X96_Y69_N0, M10K_X59_Y69_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:32:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X75_Y58_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:33:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X75_Y52_N0, M10K_X75_Y55_N0, M10K_X67_Y54_N0, M10K_X75_Y54_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:33:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X67_Y55_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:34:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X67_Y63_N0, M10K_X75_Y63_N0, M10K_X75_Y70_N0, M10K_X75_Y67_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:34:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X75_Y59_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:35:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X67_Y59_N0, M10K_X59_Y63_N0, M10K_X59_Y68_N0, M10K_X67_Y60_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:35:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X67_Y56_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:36:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X59_Y62_N0, M10K_X67_Y65_N0, M10K_X67_Y61_N0, M10K_X75_Y57_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:36:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X67_Y58_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:37:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X96_Y53_N0, M10K_X96_Y55_N0, M10K_X96_Y71_N0, M10K_X96_Y68_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:37:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X75_Y56_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:38:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X101_Y59_N0, M10K_X101_Y57_N0, M10K_X111_Y56_N0, M10K_X120_Y60_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:38:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X101_Y60_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:39:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X120_Y62_N0, M10K_X130_Y60_N0, M10K_X120_Y67_N0, M10K_X111_Y67_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:39:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X111_Y60_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:3:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X130_Y51_N0, M10K_X130_Y53_N0, M10K_X143_Y50_N0, M10K_X148_Y50_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:3:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X130_Y50_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:40:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X120_Y64_N0, M10K_X130_Y64_N0, M10K_X111_Y68_N0, M10K_X130_Y67_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:40:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X101_Y64_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:41:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X130_Y65_N0, M10K_X130_Y66_N0, M10K_X130_Y63_N0, M10K_X120_Y63_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:41:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X101_Y63_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:42:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X101_Y61_N0, M10K_X96_Y59_N0, M10K_X101_Y67_N0, M10K_X96_Y57_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:42:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X96_Y61_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:43:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X75_Y51_N0, M10K_X96_Y50_N0, M10K_X75_Y53_N0, M10K_X96_Y54_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:43:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X75_Y50_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:44:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X51_Y50_N0, M10K_X59_Y52_N0, M10K_X67_Y50_N0, M10K_X59_Y53_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:44:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X59_Y50_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:45:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X67_Y44_N0, M10K_X59_Y48_N0, M10K_X67_Y45_N0, M10K_X67_Y48_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:45:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X75_Y48_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:46:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X59_Y51_N0, M10K_X67_Y47_N0, M10K_X59_Y49_N0, M10K_X67_Y49_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:46:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X67_Y51_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:47:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X43_Y48_N0, M10K_X43_Y49_N0, M10K_X35_Y49_N0, M10K_X51_Y48_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:47:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X51_Y49_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:48:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X67_Y57_N0, M10K_X67_Y52_N0, M10K_X75_Y71_N0, M10K_X67_Y69_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:48:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X67_Y53_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:49:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X120_Y54_N0, M10K_X111_Y54_N0, M10K_X120_Y53_N0, M10K_X101_Y55_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:49:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X101_Y54_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:4:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X143_Y52_N0, M10K_X143_Y56_N0, M10K_X130_Y56_N0, M10K_X130_Y55_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:4:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X130_Y52_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:50:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X111_Y57_N0, M10K_X101_Y58_N0, M10K_X120_Y55_N0, M10K_X111_Y59_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:50:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X111_Y55_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:51:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X120_Y57_N0, M10K_X120_Y59_N0, M10K_X120_Y58_N0, M10K_X120_Y56_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:51:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X111_Y58_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:52:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X130_Y59_N0, M10K_X130_Y61_N0, M10K_X120_Y61_N0, M10K_X120_Y65_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:52:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X111_Y61_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:53:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X59_Y59_N0, M10K_X51_Y59_N0, M10K_X67_Y71_N0, M10K_X59_Y67_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:53:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X59_Y55_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:54:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X43_Y43_N0, M10K_X35_Y39_N0, M10K_X43_Y39_N0, M10K_X35_Y41_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:54:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X51_Y43_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:55:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X43_Y38_N0, M10K_X51_Y37_N0, M10K_X43_Y42_N0, M10K_X43_Y45_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:55:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X51_Y45_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:56:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X59_Y44_N0, M10K_X59_Y45_N0, M10K_X59_Y43_N0, M10K_X43_Y47_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:56:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X59_Y47_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:57:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X43_Y44_N0, M10K_X43_Y41_N0, M10K_X51_Y41_N0, M10K_X51_Y42_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:57:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X51_Y44_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:58:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X43_Y36_N0, M10K_X27_Y35_N0, M10K_X35_Y44_N0, M10K_X35_Y43_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:58:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X51_Y47_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:59:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X35_Y37_N0, M10K_X43_Y40_N0, M10K_X35_Y40_N0, M10K_X43_Y37_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:59:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X51_Y40_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:5:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X130_Y57_N0, M10K_X143_Y54_N0, M10K_X130_Y68_N0, M10K_X130_Y58_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:5:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X130_Y54_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:60:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X67_Y67_N0, M10K_X75_Y65_N0, M10K_X67_Y64_N0, M10K_X67_Y68_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:60:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X75_Y61_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:61:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X75_Y66_N0, M10K_X96_Y60_N0, M10K_X101_Y71_N0, M10K_X75_Y68_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:61:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X75_Y60_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:62:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X101_Y62_N0, M10K_X101_Y68_N0, M10K_X96_Y66_N0, M10K_X96_Y64_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:62:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X96_Y62_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:63:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X67_Y66_N0, M10K_X75_Y64_N0, M10K_X96_Y70_N0, M10K_X75_Y69_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:63:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X75_Y62_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:64:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X59_Y60_N0, M10K_X51_Y60_N0, M10K_X59_Y70_N0, M10K_X51_Y67_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:64:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X59_Y56_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:65:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X43_Y55_N0, M10K_X43_Y57_N0, M10K_X43_Y59_N0, M10K_X51_Y54_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:65:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X51_Y55_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:66:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X35_Y50_N0, M10K_X35_Y53_N0, M10K_X43_Y50_N0, M10K_X35_Y51_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:66:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X43_Y53_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:67:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X27_Y60_N0, M10K_X51_Y63_N0, M10K_X43_Y63_N0, M10K_X43_Y64_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:67:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X51_Y56_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:68:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X35_Y52_N0, M10K_X43_Y52_N0, M10K_X51_Y51_N0, M10K_X43_Y51_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:68:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X51_Y52_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:69:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X43_Y61_N0, M10K_X27_Y57_N0, M10K_X43_Y67_N0, M10K_X43_Y68_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:69:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X51_Y53_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:6:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X143_Y61_N0, M10K_X143_Y58_N0, M10K_X148_Y61_N0, M10K_X148_Y59_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:6:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X148_Y58_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:70:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X35_Y60_N0, M10K_X35_Y58_N0, M10K_X35_Y57_N0, M10K_X35_Y59_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:70:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X43_Y56_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:71:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X35_Y63_N0, M10K_X27_Y55_N0, M10K_X35_Y66_N0, M10K_X35_Y67_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:71:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X35_Y55_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:72:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X35_Y64_N0, M10K_X27_Y59_N0, M10K_X43_Y70_N0, M10K_X35_Y68_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:72:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X35_Y56_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:73:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X43_Y62_N0, M10K_X35_Y65_N0, M10K_X35_Y62_N0, M10K_X35_Y61_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:73:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X43_Y58_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:74:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X51_Y61_N0, M10K_X59_Y61_N0, M10K_X59_Y71_N0, M10K_X43_Y69_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:74:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X59_Y57_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:75:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X27_Y58_N0, M10K_X51_Y62_N0, M10K_X43_Y65_N0, M10K_X43_Y66_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:75:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X51_Y58_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:76:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X59_Y66_N0, M10K_X59_Y64_N0, M10K_X51_Y64_N0, M10K_X51_Y69_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:76:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X59_Y58_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:77:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X51_Y57_N0, M10K_X27_Y61_N0, M10K_X51_Y70_N0, M10K_X51_Y68_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:77:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X59_Y54_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:7:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X143_Y64_N0, M10K_X143_Y63_N0, M10K_X143_Y67_N0, M10K_X143_Y68_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:7:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X143_Y60_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:8:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X148_Y63_N0, M10K_X148_Y64_N0, M10K_X148_Y65_N0, M10K_X143_Y65_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:8:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X148_Y60_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:9:ACONSTMEMSTITCHED|dualport_ram_2048x20:LARGERAM|altsyncram:altsyncram_component|altsyncram_fkr1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 2048 20 2048 20 yes no yes yes 40960 2048 20 2048 20 40960 4 0 None M10K_X148_Y66_N0, M10K_X143_Y66_N0, M10K_X143_Y62_N0, M10K_X130_Y62_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:9:ACONSTMEMSTITCHED|dualport_ram_512x20:SMALL|altsyncram:altsyncram_component|altsyncram_her1:auto_generated|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 512 20 512 20 yes no yes yes 10240 512 20 512 20 10240 1 0 None M10K_X148_Y62_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|scfifo:tf_eventtrailerfifo_inst|scfifo_blb1:auto_generated|a_dpfifo_d981:dpfifo|altsyncram_5uj1:FIFOram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 16 32 16 32 yes no yes yes 512 16 32 16 32 512 1 0 None M10K_X67_Y28_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|scfifo:tfeventheaderfifo_inst|scfifo_dlb1:auto_generated|a_dpfifo_d981:dpfifo|altsyncram_5uj1:FIFOram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 16 32 16 32 yes no yes yes 512 16 32 16 32 512 1 0 None M10K_X75_Y26_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|dualport_ram_14x8:SCTRAM0|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X120_Y66_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|dualport_ram_14x8:SCTRAM1|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X101_Y70_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|dualport_ram_14x8:SCTRAM2|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X101_Y69_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|dualport_ram_14x8:SCTRAM3|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X101_Y66_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|dualport_ram_14x8:SCTRAM4|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X101_Y65_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|dualport_ram_29x8:PIXRAM0|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X120_Y68_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|dualport_ram_29x8:PIXRAM1|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X120_Y72_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|dualport_ram_29x8:PIXRAM2|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X120_Y70_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitFIFO:FITFIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|altsyncram_e2m1:FIFOram|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 256 256 256 256 yes no yes yes 65536 256 256 256 256 65536 7 0 None M10K_X111_Y35_N0, M10K_X120_Y33_N0, M10K_X120_Y32_N0, M10K_X120_Y36_N0, M10K_X120_Y34_N0, M10K_X120_Y35_N0, M10K_X111_Y32_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFFullChiPartialCalculator:CHICALC|TFChiPartialCalculator:CHIPARTIALCALC5|parallel_add_33x8_36:SCTADDER4|parallel_add:parallel_add_component|par_add_mre:auto_generated|altshift_taps:dffe102_rtl_0|shift_taps_squ:auto_generated|altsyncram_fq91:altsyncram4|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 4 1200 4 1200 yes no yes yes 4800 4 1200 4 1200 4800 30 0 None M10K_X96_Y82_N0, M10K_X96_Y78_N0, M10K_X111_Y85_N0, M10K_X120_Y87_N0, M10K_X143_Y82_N0, M10K_X130_Y89_N0, M10K_X143_Y89_N0, M10K_X130_Y84_N0, M10K_X75_Y79_N0, M10K_X35_Y84_N0, M10K_X67_Y87_N0, M10K_X75_Y83_N0, M10K_X59_Y80_N0, M10K_X96_Y77_N0, M10K_X67_Y70_N0, M10K_X35_Y72_N0, M10K_X96_Y75_N0, M10K_X51_Y76_N0, M10K_X59_Y82_N0, M10K_X101_Y77_N0, M10K_X67_Y81_N0, M10K_X96_Y87_N0, M10K_X120_Y77_N0, M10K_X120_Y86_N0, M10K_X111_Y86_N0, M10K_X101_Y76_N0, M10K_X111_Y83_N0, M10K_X101_Y74_N0, M10K_X51_Y66_N0, M10K_X67_Y74_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X52_Y67_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X44_Y67_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X60_Y82_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X68_Y83_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X68_Y89_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X68_Y87_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X113_Y89_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X141_Y91_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X131_Y89_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:9:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 18 15 18 270 0 18 None LAB_X97_Y65_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X44_Y66_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X44_Y65_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X52_Y81_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X60_Y73_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X52_Y87_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X52_Y85_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X97_Y89_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X131_Y90_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X113_Y87_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:9:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 18 15 18 270 0 18 None LAB_X68_Y63_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X36_Y63_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X44_Y63_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X60_Y77_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X60_Y79_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X60_Y85_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X60_Y81_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X90_Y89_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X105_Y91_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X105_Y85_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:9:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 18 15 18 270 0 18 None LAB_X68_Y60_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X25_Y63_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X36_Y61_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X44_Y77_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X52_Y79_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X25_Y87_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X60_Y87_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X76_Y95_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X113_Y95_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X124_Y85_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:9:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 18 15 18 270 0 18 None LAB_X60_Y63_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X25_Y62_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X36_Y60_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X60_Y74_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X52_Y75_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X25_Y84_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X44_Y85_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X68_Y93_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X113_Y93_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X121_Y81_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:9:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 18 15 18 270 0 18 None LAB_X60_Y61_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X36_Y59_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X44_Y57_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X44_Y73_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X60_Y75_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X36_Y83_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X73_Y82_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X76_Y89_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X113_Y85_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 20 15 20 300 0 20 None LAB_X124_Y81_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:9:ASHIFTREG|shift_taps_jk41:auto_generated|dpram_3gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 15 20 15 20 yes no no no 300 15 18 15 18 270 0 18 None LAB_X76_Y62_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_mk41:auto_generated|dpram_7gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 18 20 18 20 yes no no no 360 18 20 18 20 360 0 20 None LAB_X36_Y55_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_mk41:auto_generated|dpram_7gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 18 20 18 20 yes no no no 360 18 20 18 20 360 0 20 None LAB_X36_Y53_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_mk41:auto_generated|dpram_7gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 18 20 18 20 yes no no no 360 18 14 18 14 252 0 14 None LAB_X25_Y51_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_mk41:auto_generated|dpram_7gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 18 20 18 20 yes no no no 360 18 20 18 20 360 0 20 None LAB_X52_Y57_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_mk41:auto_generated|dpram_7gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 18 20 18 20 yes no no no 360 18 20 18 20 360 0 20 None LAB_X44_Y55_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_mk41:auto_generated|dpram_7gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 18 20 18 20 yes no no no 360 18 14 18 14 252 0 14 None LAB_X44_Y53_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_mk41:auto_generated|dpram_7gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 18 20 18 20 yes no no no 360 18 20 18 20 360 0 20 None LAB_X25_Y57_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_mk41:auto_generated|dpram_7gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 18 20 18 20 yes no no no 360 18 20 18 20 360 0 20 None LAB_X25_Y55_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_mk41:auto_generated|dpram_7gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 18 20 18 20 yes no no no 360 18 14 18 14 252 0 14 None LAB_X25_Y53_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_SCT|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_mk41:auto_generated|dpram_7gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 18 20 18 20 yes no no no 360 18 20 18 20 360 0 20 None LAB_X44_Y83_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_SCT|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_mk41:auto_generated|dpram_7gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 18 20 18 20 yes no no no 360 18 20 18 20 360 0 20 None LAB_X68_Y85_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_SCT|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_mk41:auto_generated|dpram_7gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 18 20 18 20 yes no no no 360 18 20 18 20 360 0 20 None LAB_X105_Y81_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_SCT|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_mk41:auto_generated|dpram_7gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 18 20 18 20 yes no no no 360 18 20 18 20 360 0 20 None LAB_X73_Y57_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_SCT|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_mk41:auto_generated|dpram_7gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 18 20 18 20 yes no no no 360 18 10 18 10 180 0 10 None LAB_X68_Y57_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X25_Y70_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X25_Y66_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X25_Y65_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X36_Y64_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X12_Y64_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X12_Y62_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X12_Y61_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X25_Y58_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 2 21 2 42 0 2 None LAB_X15_Y57_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X25_Y67_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X20_Y67_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X20_Y63_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X15_Y63_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X20_Y59_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X25_Y59_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y67_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y65_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X20_Y61_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X25_Y61_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X20_Y57_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X36_Y57_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X52_Y83_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X52_Y80_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X44_Y79_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X52_Y78_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X44_Y78_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X44_Y76_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X44_Y75_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X36_Y72_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 2 21 2 42 0 2 None LAB_X36_Y71_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X44_Y81_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X25_Y81_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y81_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y77_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y73_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X25_Y73_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X60_Y83_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X25_Y79_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y79_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y75_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X25_Y75_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X25_Y71_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X44_Y89_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X44_Y88_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X20_Y90_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X6_Y89_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X8_Y87_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X12_Y86_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X12_Y85_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X15_Y84_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 2 21 2 42 0 2 None LAB_X25_Y85_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y91_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y87_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X25_Y91_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X15_Y87_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X20_Y87_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X25_Y83_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y89_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X25_Y89_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X20_Y89_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X12_Y87_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X15_Y85_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X20_Y85_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFRecChiSquareCalculator:ACHISQUARECALC|TFFullCoordsShiftRegister:GUESSEDHITSSR|shiftreg_20x16:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_c351:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Dual Clocks 16 20 16 20 yes no no yes 320 16 20 16 20 320 0 20 None LAB_X25_Y74_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFRecChiSquareCalculator:ACHISQUARECALC|TFFullCoordsShiftRegister:GUESSEDHITSSR|shiftreg_20x16:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_c351:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Dual Clocks 16 20 16 20 yes no no yes 320 16 20 16 20 320 0 20 None LAB_X36_Y78_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFRecChiSquareCalculator:ACHISQUARECALC|TFFullCoordsShiftRegister:GUESSEDHITSSR|shiftreg_20x16:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_c351:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Dual Clocks 16 20 16 20 yes no no yes 320 16 20 16 20 320 0 20 None LAB_X25_Y78_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFRecChiSquareCalculator:ACHISQUARECALC|TFFullCoordsShiftRegister:GUESSEDHITSSR|shiftreg_20x16:\gen_SHIFTREGISTERS:3:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_c351:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y82_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFRecChiSquareCalculator:ACHISQUARECALC|TFFullCoordsShiftRegister:GUESSEDHITSSR|shiftreg_20x16:\gen_SHIFTREGISTERS:4:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_c351:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X87_Y93_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFRecChiSquareCalculator:ACHISQUARECALC|TFFullCoordsShiftRegister:GUESSEDHITSSR|shiftreg_20x16:\gen_SHIFTREGISTERS:5:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_c351:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Dual Clocks 16 20 16 20 yes no no yes 320 16 20 16 20 320 0 20 None LAB_X90_Y90_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFRecChiSquareCalculator:ACHISQUARECALC|TFFullCoordsShiftRegister:GUESSEDHITSSR|shiftreg_20x16:\gen_SHIFTREGISTERS:6:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_c351:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Dual Clocks 16 20 16 20 yes no no yes 320 16 7 16 7 112 0 7 None LAB_X83_Y90_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFRecChiSquareCalculator:ACHISQUARECALC|shiftreg_20x6:OFLMAPSR|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_r151:auto_generated|dpram_ien1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 6 20 6 20 yes no no no 120 6 8 6 8 48 0 8 None LAB_X85_Y92_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X44_Y92_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X44_Y91_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X44_Y93_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X52_Y96_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X60_Y99_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X52_Y99_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X52_Y94_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X60_Y92_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 2 21 2 42 0 2 None LAB_X60_Y94_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X52_Y91_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X52_Y89_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X52_Y93_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X44_Y95_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X60_Y93_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X60_Y91_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X102_Y93_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X105_Y93_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X105_Y96_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X105_Y103_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X90_Y95_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X81_Y97_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X76_Y93_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X87_Y91_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 2 21 2 42 0 2 None LAB_X76_Y94_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X105_Y95_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X105_Y97_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X92_Y95_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X73_Y95_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X73_Y93_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X76_Y97_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X141_Y95_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X146_Y95_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X141_Y94_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X141_Y98_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X124_Y98_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X124_Y97_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X124_Y100_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X131_Y99_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 2 21 2 42 0 2 None LAB_X131_Y97_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X141_Y93_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X131_Y93_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X131_Y95_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X121_Y95_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X124_Y93_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X121_Y93_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X124_Y92_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X131_Y92_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X124_Y87_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X131_Y86_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X124_Y86_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X124_Y84_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X124_Y83_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X124_Y80_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 2 21 2 42 0 2 None LAB_X131_Y80_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X121_Y89_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X121_Y87_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X121_Y85_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X131_Y85_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X131_Y81_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X131_Y79_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X90_Y66_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X85_Y65_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X73_Y64_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X73_Y59_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X60_Y60_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X52_Y64_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X52_Y63_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X81_Y62_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 2 21 2 42 0 2 None LAB_X92_Y61_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X76_Y65_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X73_Y63_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X60_Y59_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X52_Y61_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X68_Y61_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X73_Y61_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|altshift_taps:ofl_tv_reg_rtl_0|shift_taps_hmu:auto_generated|altsyncram_rh91:altsyncram5|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 7 5 7 5 yes no yes yes 35 7 5 7 5 35 1 0 None M10K_X143_Y91_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitterOutputShiftRegister:RECOUTPUTSR|shiftreg_20x17:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_d351:auto_generated|dpram_6gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 17 20 17 20 yes no no no 340 17 20 17 20 340 0 20 None LAB_X60_Y76_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitterOutputShiftRegister:RECOUTPUTSR|shiftreg_20x17:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_d351:auto_generated|dpram_6gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Dual Clocks 17 20 17 20 yes no no yes 340 17 20 17 20 340 0 20 None LAB_X102_Y72_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitterOutputShiftRegister:RECOUTPUTSR|shiftreg_20x17:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_d351:auto_generated|dpram_6gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Dual Clocks 17 20 17 20 yes no no yes 340 17 4 17 4 68 0 4 None LAB_X92_Y92_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|altshift_taps:loose_reg_rtl_0|shift_taps_0ou:auto_generated|altsyncram_0l91:altsyncram5|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 45 2 45 2 yes no yes yes 90 45 2 45 2 90 1 0 None M10K_X5_Y50_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|altshift_taps:nom_chisquare_reg_rtl_0|shift_taps_qpu:auto_generated|altsyncram_jo91:altsyncram5|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 46 56 46 56 yes no yes yes 2576 46 56 46 56 2576 2 0 None M10K_X51_Y46_N0, M10K_X43_Y46_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|altshift_taps:rec_chisquare_reg_rtl_0|shift_taps_npu:auto_generated|altsyncram_9o91:altsyncram4|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 16 56 16 56 yes no yes yes 896 16 56 16 56 896 2 0 None M10K_X43_Y88_N0, M10K_X35_Y88_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 66 20 66 20 yes no no no 1320 66 20 66 20 1320 0 60 None LAB_X131_Y68_N0, LAB_X124_Y68_N0, LAB_X121_Y68_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 66 20 66 20 yes no no no 1320 66 20 66 20 1320 0 60 None LAB_X113_Y71_N0, LAB_X121_Y71_N0, LAB_X124_Y71_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 66 20 66 20 yes no no no 1320 66 20 66 20 1320 0 60 None LAB_X124_Y72_N0, LAB_X131_Y72_N0, LAB_X121_Y72_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:3:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 66 20 66 20 yes no no no 1320 66 20 66 20 1320 0 60 None LAB_X124_Y70_N0, LAB_X131_Y70_N0, LAB_X121_Y70_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:4:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 66 20 66 20 yes no no no 1320 66 20 66 20 1320 0 60 None LAB_X113_Y67_N0, LAB_X113_Y68_N0, LAB_X121_Y67_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:5:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 66 20 66 20 yes no no no 1320 66 20 66 20 1320 0 60 None LAB_X105_Y70_N0, LAB_X102_Y70_N0, LAB_X97_Y70_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:6:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 66 20 66 20 yes no no no 1320 66 20 66 20 1320 0 60 None LAB_X102_Y67_N0, LAB_X97_Y67_N0, LAB_X105_Y67_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 66 20 66 20 yes no no no 1320 66 20 66 20 1320 0 60 None LAB_X102_Y64_N0, LAB_X92_Y64_N0, LAB_X97_Y64_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 66 20 66 20 yes no no no 1320 66 20 66 20 1320 0 60 None LAB_X124_Y39_N0, LAB_X121_Y39_N0, LAB_X113_Y39_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:9:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 66 20 66 20 yes no no no 1320 66 13 66 13 858 0 39 None LAB_X124_Y46_N0, LAB_X121_Y46_N0, LAB_X113_Y46_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomRoadFIFO:NOMROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|altsyncram_o1m1:FIFOram|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 256 200 256 200 yes no yes yes 51200 256 200 256 200 51200 5 0 None M10K_X111_Y66_N0, M10K_X111_Y63_N0, M10K_X111_Y62_N0, M10K_X111_Y65_N0, M10K_X111_Y64_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|dualport_ram_14x8:SCTRAM0|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X96_Y27_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|dualport_ram_14x8:SCTRAM1|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X96_Y34_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|dualport_ram_14x8:SCTRAM2|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X101_Y34_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|dualport_ram_14x8:SCTRAM3|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X101_Y35_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|dualport_ram_14x8:SCTRAM4|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X111_Y33_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|dualport_ram_29x8:PIXRAM0|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X111_Y27_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|dualport_ram_29x8:PIXRAM1|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X101_Y27_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|altsyncram_e2m1:FIFOram|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 256 256 256 256 yes no yes yes 65536 256 256 256 256 65536 7 0 None M10K_X120_Y31_N0, M10K_X111_Y29_N0, M10K_X120_Y28_N0, M10K_X111_Y30_N0, M10K_X120_Y26_N0, M10K_X120_Y24_N0, M10K_X111_Y28_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X113_Y29_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X105_Y27_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X90_Y27_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X121_Y27_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X97_Y25_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 8 12 8 96 0 8 None LAB_X124_Y22_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X105_Y29_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X97_Y28_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X90_Y24_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X124_Y21_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X90_Y21_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 8 12 8 96 0 8 None LAB_X90_Y17_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_fk41:auto_generated|dpram_0gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 20 20 20 20 yes no no no 400 20 20 20 20 400 0 20 None LAB_X76_Y31_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_fk41:auto_generated|dpram_0gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 20 20 20 20 yes no no no 400 20 20 20 20 400 0 20 None LAB_X73_Y24_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_fk41:auto_generated|dpram_0gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 20 20 20 20 yes no no no 400 20 14 20 14 280 0 14 None LAB_X73_Y25_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericShiftRegister:GUESSEDHITSR_PIXCOL|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_qk41:auto_generated|dpram_dgn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 39 12 39 12 yes no no no 468 39 12 39 12 468 0 24 None LAB_X105_Y24_N0, LAB_X102_Y24_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericShiftRegister:GUESSEDHITSR_PIXROW|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_qk41:auto_generated|dpram_dgn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 39 12 39 12 yes no no no 468 39 12 39 12 468 0 24 None LAB_X105_Y22_N0, LAB_X113_Y22_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X97_Y22_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X102_Y20_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X102_Y19_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X113_Y19_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X124_Y20_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X124_Y18_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X124_Y17_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X92_Y16_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 2 21 2 42 0 2 None LAB_X113_Y17_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X105_Y19_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X105_Y23_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X113_Y23_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X124_Y23_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X124_Y19_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X121_Y19_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X105_Y17_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X105_Y21_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X121_Y21_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X131_Y21_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X121_Y17_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X102_Y17_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X113_Y25_N0, LAB_X105_Y25_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X113_Y28_N0, LAB_X113_Y27_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X105_Y26_N0, LAB_X102_Y26_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:3:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X92_Y24_N0, LAB_X97_Y24_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:4:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X92_Y34_N0, LAB_X90_Y34_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:5:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X97_Y31_N0, LAB_X102_Y31_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:6:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X97_Y33_N0, LAB_X102_Y33_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X113_Y33_N0, LAB_X105_Y33_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 7 64 7 448 0 14 None LAB_X121_Y24_N0, LAB_X124_Y24_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixRoadFIFO:PIXROADFIFO|fifo_188x256_128:FIFO|scfifo:scfifo_component|scfifo_kug1:auto_generated|a_dpfifo_bge1:dpfifo|altsyncram_m2m1:FIFOram|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 256 188 256 188 yes no yes yes 48128 256 173 256 173 44288 5 0 None M10K_X111_Y34_N0, M10K_X101_Y33_N0, M10K_X101_Y30_N0, M10K_X111_Y31_N0, M10K_X101_Y28_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|dualport_ram_14x8:SCTRAM0|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X75_Y32_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|dualport_ram_14x8:SCTRAM1|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X75_Y31_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|dualport_ram_14x8:SCTRAM2|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X75_Y30_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|dualport_ram_14x8:SCTRAM3|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X96_Y35_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|dualport_ram_14x8:SCTRAM4|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X96_Y32_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|dualport_ram_29x8:PIXRAM0|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X96_Y29_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|dualport_ram_29x8:PIXRAM1|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X96_Y31_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|altsyncram_e2m1:FIFOram|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 256 256 256 256 yes no yes yes 65536 256 256 256 256 65536 7 0 None M10K_X120_Y29_N0, M10K_X130_Y29_N0, M10K_X130_Y28_N0, M10K_X120_Y30_N0, M10K_X130_Y26_N0, M10K_X130_Y27_N0, M10K_X120_Y27_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X44_Y31_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X44_Y30_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X52_Y31_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X60_Y33_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X60_Y30_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 8 12 8 96 0 8 None LAB_X52_Y29_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X44_Y25_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X44_Y24_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X68_Y21_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X68_Y25_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X60_Y24_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 8 12 8 96 0 8 None LAB_X60_Y21_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_fk41:auto_generated|dpram_0gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 20 20 20 20 yes no no no 400 20 20 20 20 400 0 20 None LAB_X73_Y29_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_fk41:auto_generated|dpram_0gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 20 20 20 20 yes no no no 400 20 20 20 20 400 0 20 None LAB_X73_Y31_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_fk41:auto_generated|dpram_0gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 20 20 20 20 yes no no no 400 20 14 20 14 280 0 14 None LAB_X60_Y27_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericShiftRegister:GUESSEDHITSR_PIXCOL|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_qk41:auto_generated|dpram_dgn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 39 12 39 12 yes no no no 468 39 12 39 12 468 0 24 None LAB_X90_Y23_N0, LAB_X92_Y23_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericShiftRegister:GUESSEDHITSR_PIXROW|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_qk41:auto_generated|dpram_dgn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 39 12 39 12 yes no no no 468 39 12 39 12 468 0 24 None LAB_X90_Y25_N0, LAB_X92_Y25_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X44_Y26_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X44_Y23_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X44_Y22_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X44_Y20_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X68_Y22_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X60_Y23_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X52_Y22_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X60_Y20_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 2 21 2 42 0 2 None LAB_X36_Y21_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y31_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y27_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X44_Y27_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X60_Y31_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X52_Y27_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X36_Y29_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y25_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y23_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X44_Y21_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X60_Y25_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X52_Y25_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericConstArrShiftRegister:CONST1LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X52_Y21_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X97_Y26_N0, LAB_X92_Y26_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X90_Y28_N0, LAB_X92_Y28_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X92_Y27_N0, LAB_X97_Y27_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:3:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X76_Y32_N0, LAB_X73_Y32_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:4:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X68_Y30_N0, LAB_X73_Y30_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:5:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X92_Y31_N0, LAB_X90_Y31_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:6:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X102_Y32_N0, LAB_X105_Y32_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X92_Y29_N0, LAB_X90_Y29_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 7 64 7 448 0 14 None LAB_X73_Y27_N0, LAB_X76_Y27_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixRoadFIFO:PIXROADFIFO|fifo_188x256_128:FIFO|scfifo:scfifo_component|scfifo_kug1:auto_generated|a_dpfifo_bge1:dpfifo|altsyncram_m2m1:FIFOram|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 256 188 256 188 yes no yes yes 48128 256 173 256 173 44288 5 0 None M10K_X96_Y33_N0, M10K_X101_Y32_N0, M10K_X96_Y30_N0, M10K_X101_Y31_N0, M10K_X101_Y29_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|dualport_ram_14x8:SCTRAM0|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X143_Y42_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|dualport_ram_14x8:SCTRAM1|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X162_Y43_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|dualport_ram_14x8:SCTRAM2|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X162_Y45_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|dualport_ram_14x8:SCTRAM3|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X143_Y43_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|dualport_ram_29x8:PIXRAM0|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X178_Y48_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|dualport_ram_29x8:PIXRAM1|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X178_Y43_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|dualport_ram_29x8:PIXRAM2|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X162_Y42_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|altsyncram_e2m1:FIFOram|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 256 256 256 256 yes no yes yes 65536 256 256 256 256 65536 7 0 None M10K_X148_Y35_N0, M10K_X148_Y33_N0, M10K_X148_Y32_N0, M10K_X148_Y34_N0, M10K_X143_Y30_N0, M10K_X148_Y31_N0, M10K_X143_Y31_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X165_Y65_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X170_Y63_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X174_Y57_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X154_Y65_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X165_Y64_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 8 12 8 96 0 8 None LAB_X165_Y63_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFGenericShiftRegister:GUESSCONSTSR|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_fk41:auto_generated|dpram_0gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 20 20 20 20 yes no no no 400 20 18 20 18 360 0 18 None LAB_X154_Y61_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFGenericShiftRegister:GUESSEDHITSR|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_lk41:auto_generated|dpram_5gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 11 16 11 yes no no no 176 16 11 16 11 176 0 11 None LAB_X146_Y34_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X176_Y65_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X176_Y64_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X176_Y66_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X174_Y68_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X174_Y67_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X165_Y66_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X165_Y70_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X179_Y73_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 2 21 2 42 0 2 None LAB_X176_Y73_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X174_Y65_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X174_Y63_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X170_Y69_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X154_Y69_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X165_Y67_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X154_Y70_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X176_Y48_N0, LAB_X174_Y48_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X176_Y46_N0, LAB_X170_Y46_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X174_Y39_N0, LAB_X176_Y39_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:3:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X154_Y32_N0, LAB_X151_Y32_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:4:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X154_Y34_N0, LAB_X151_Y34_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:5:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X154_Y35_N0, LAB_X151_Y35_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:6:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X151_Y33_N0, LAB_X154_Y33_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X146_Y35_N0, LAB_X141_Y35_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X146_Y33_N0, LAB_X141_Y33_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:9:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 4 64 4 256 0 8 None LAB_X141_Y31_N0, LAB_X141_Y32_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|altsyncram_o1m1:FIFOram|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 256 200 256 200 yes no yes yes 51200 256 190 256 190 48640 5 0 None M10K_X148_Y43_N0, M10K_X148_Y41_N0, M10K_X148_Y42_N0, M10K_X162_Y41_N0, M10K_X162_Y44_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|dualport_ram_14x8:SCTRAM0|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X162_Y33_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|dualport_ram_14x8:SCTRAM1|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X162_Y35_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|dualport_ram_14x8:SCTRAM2|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X162_Y36_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|dualport_ram_14x8:SCTRAM3|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X148_Y36_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|dualport_ram_29x8:PIXRAM0|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X162_Y38_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|dualport_ram_29x8:PIXRAM1|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X162_Y40_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|dualport_ram_29x8:PIXRAM2|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X162_Y37_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|altsyncram_e2m1:FIFOram|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 256 256 256 256 yes no yes yes 65536 256 256 256 256 65536 7 0 None M10K_X143_Y28_N0, M10K_X148_Y29_N0, M10K_X148_Y28_N0, M10K_X148_Y30_N0, M10K_X148_Y26_N0, M10K_X148_Y27_N0, M10K_X143_Y29_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X170_Y39_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X165_Y37_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X167_Y45_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X154_Y39_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X165_Y36_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 8 12 8 96 0 8 None LAB_X165_Y39_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFGenericShiftRegister:GUESSCONSTSR|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_fk41:auto_generated|dpram_0gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 20 20 20 20 yes no no no 400 20 18 20 18 360 0 18 None LAB_X151_Y39_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFGenericShiftRegister:GUESSEDHITSR|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_lk41:auto_generated|dpram_5gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 11 16 11 yes no no no 176 16 11 16 11 176 0 11 None LAB_X165_Y30_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X165_Y34_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X170_Y30_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X174_Y33_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X170_Y35_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X146_Y32_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X165_Y32_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X167_Y37_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X167_Y34_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 2 21 2 42 0 2 None LAB_X167_Y33_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X167_Y39_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X170_Y37_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X174_Y31_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X154_Y31_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X170_Y33_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X165_Y35_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X167_Y27_N0, LAB_X165_Y27_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X167_Y38_N0, LAB_X170_Y38_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X154_Y29_N0, LAB_X151_Y29_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:3:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X151_Y30_N0, LAB_X154_Y30_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:4:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X154_Y26_N0, LAB_X151_Y26_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:5:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X154_Y27_N0, LAB_X151_Y27_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:6:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X151_Y28_N0, LAB_X154_Y28_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X141_Y30_N0, LAB_X146_Y30_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X146_Y31_N0, LAB_X151_Y31_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:9:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 4 64 4 256 0 8 None LAB_X151_Y25_N0, LAB_X146_Y25_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|altsyncram_o1m1:FIFOram|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 256 200 256 200 yes no yes yes 51200 256 190 256 190 48640 5 0 None M10K_X148_Y38_N0, M10K_X148_Y39_N0, M10K_X148_Y37_N0, M10K_X162_Y39_N0, M10K_X148_Y40_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|dualport_ram_14x8:SCTRAM0|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X162_Y49_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|dualport_ram_14x8:SCTRAM1|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X143_Y46_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|dualport_ram_14x8:SCTRAM2|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X143_Y47_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|dualport_ram_14x8:SCTRAM3|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X162_Y46_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|dualport_ram_29x8:PIXRAM0|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X162_Y51_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|dualport_ram_29x8:PIXRAM1|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X162_Y47_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|dualport_ram_29x8:PIXRAM2|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X162_Y50_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|altsyncram_e2m1:FIFOram|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 256 256 256 256 yes no yes yes 65536 256 256 256 256 65536 7 0 None M10K_X143_Y36_N0, M10K_X143_Y33_N0, M10K_X143_Y32_N0, M10K_X143_Y34_N0, M10K_X143_Y26_N0, M10K_X143_Y27_N0, M10K_X143_Y35_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X141_Y79_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X146_Y73_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X165_Y75_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X154_Y77_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X154_Y72_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 8 12 8 96 0 8 None LAB_X151_Y72_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFGenericShiftRegister:GUESSCONSTSR|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_fk41:auto_generated|dpram_0gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 20 20 20 20 yes no no no 400 20 18 20 18 360 0 18 None LAB_X154_Y73_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFGenericShiftRegister:GUESSEDHITSR|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_lk41:auto_generated|dpram_5gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 11 16 11 yes no no no 176 16 11 16 11 176 0 11 None LAB_X146_Y39_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X141_Y75_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X151_Y76_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X151_Y75_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X174_Y82_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X170_Y81_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X141_Y81_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X146_Y80_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X151_Y78_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 2 21 2 42 0 2 None LAB_X154_Y78_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X146_Y79_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X146_Y75_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X165_Y79_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X154_Y81_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X154_Y79_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X151_Y79_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X167_Y44_N0, LAB_X170_Y44_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X174_Y51_N0, LAB_X176_Y51_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X151_Y44_N0, LAB_X154_Y44_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:3:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X170_Y52_N0, LAB_X174_Y52_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:4:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X151_Y38_N0, LAB_X146_Y38_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:5:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X146_Y36_N0, LAB_X141_Y36_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:6:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X151_Y37_N0, LAB_X154_Y37_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X151_Y36_N0, LAB_X154_Y36_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X154_Y40_N0, LAB_X151_Y40_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:9:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 4 64 4 256 0 8 None LAB_X151_Y42_N0, LAB_X154_Y42_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|altsyncram_o1m1:FIFOram|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 256 200 256 200 yes no yes yes 51200 256 190 256 190 48640 5 0 None M10K_X148_Y44_N0, M10K_X148_Y45_N0, M10K_X148_Y46_N0, M10K_X148_Y47_N0, M10K_X162_Y48_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|dualport_ram_14x8:SCTRAM0|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X130_Y37_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|dualport_ram_14x8:SCTRAM1|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X130_Y39_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|dualport_ram_14x8:SCTRAM2|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X120_Y39_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|dualport_ram_14x8:SCTRAM3|altsyncram:altsyncram_component|altsyncram_mbt1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 14 8 14 yes no yes yes 112 8 14 8 14 112 1 0 None M10K_X120_Y38_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|dualport_ram_29x8:PIXRAM0|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X120_Y40_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|dualport_ram_29x8:PIXRAM1|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X130_Y41_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|dualport_ram_29x8:PIXRAM2|altsyncram:altsyncram_component|altsyncram_2ct1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Single Clock 8 29 8 29 yes no yes yes 232 8 29 8 29 232 1 0 None M10K_X130_Y42_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|altsyncram_e2m1:FIFOram|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 256 256 256 256 yes no yes yes 65536 256 256 256 256 65536 7 0 None M10K_X130_Y35_N0, M10K_X130_Y33_N0, M10K_X130_Y32_N0, M10K_X130_Y34_N0, M10K_X130_Y30_N0, M10K_X130_Y31_N0, M10K_X130_Y36_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X44_Y45_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X52_Y43_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X44_Y41_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X44_Y42_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 20 12 20 240 0 20 None LAB_X44_Y39_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_hk41:auto_generated|dpram_2gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 12 20 12 20 yes no no no 240 12 8 12 8 96 0 8 None LAB_X60_Y37_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFGenericShiftRegister:GUESSCONSTSR|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_fk41:auto_generated|dpram_0gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 20 20 20 20 yes no no no 400 20 18 20 18 360 0 18 None LAB_X44_Y43_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFGenericShiftRegister:GUESSEDHITSR|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_lk41:auto_generated|dpram_5gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 11 16 11 yes no no no 176 16 11 16 11 176 0 11 None LAB_X141_Y34_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X36_Y44_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X36_Y43_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X36_Y39_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X36_Y40_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X52_Y39_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X44_Y36_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X44_Y35_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 20 21 20 420 0 20 None LAB_X52_Y34_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|dpram_1gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 21 20 21 20 yes no no no 420 21 2 21 2 42 0 2 None LAB_X52_Y35_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y45_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X25_Y39_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y41_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X44_Y38_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 20 16 20 320 0 20 None LAB_X36_Y35_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericConstArrShiftRegister:CONST0LARGESR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_kk41:auto_generated|dpram_4gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 16 20 16 20 yes no no no 320 16 8 16 8 128 0 8 None LAB_X52_Y37_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFSctGuessedChiCalculator:GUESSEDCHICALC|add_27_28:ADDER5|parallel_add:parallel_add_component|par_add_kre:auto_generated|altshift_taps:dffe12_rtl_0|shift_taps_fru:auto_generated|altsyncram_lr91:altsyncram4|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 3 2777 3 2777 yes no yes yes 8331 3 2777 3 2777 8331 70 0 None M10K_X143_Y37_N0, M10K_X96_Y25_N0, M10K_X67_Y32_N0, M10K_X43_Y82_N0, M10K_X35_Y81_N0, M10K_X19_Y56_N0, M10K_X143_Y74_N0, M10K_X162_Y65_N0, M10K_X75_Y23_N0, M10K_X96_Y20_N0, M10K_X43_Y34_N0, M10K_X27_Y33_N0, M10K_X43_Y33_N0, M10K_X162_Y80_N0, M10K_X162_Y84_N0, M10K_X178_Y85_N0, M10K_X178_Y77_N0, M10K_X178_Y74_N0, M10K_X162_Y72_N0, M10K_X162_Y34_N0, M10K_X162_Y26_N0, M10K_X162_Y27_N0, M10K_X148_Y17_N0, M10K_X35_Y19_N0, M10K_X43_Y19_N0, M10K_X75_Y15_N0, M10K_X96_Y15_N0, M10K_X120_Y16_N0, M10K_X120_Y15_N0, M10K_X130_Y78_N0, M10K_X96_Y67_N0, M10K_X59_Y65_N0, M10K_X67_Y72_N0, M10K_X27_Y95_N0, M10K_X19_Y75_N0, M10K_X59_Y83_N0, M10K_X130_Y99_N0, M10K_X130_Y91_N0, M10K_X19_Y83_N0, M10K_X5_Y91_N0, M10K_X5_Y93_N0, M10K_X19_Y93_N0, M10K_X19_Y100_N0, M10K_X35_Y101_N0, M10K_X35_Y103_N0, M10K_X19_Y60_N0, M10K_X19_Y65_N0, M10K_X5_Y68_N0, M10K_X19_Y73_N0, M10K_X19_Y76_N0, M10K_X19_Y81_N0, M10K_X59_Y91_N0, M10K_X101_Y101_N0, M10K_X101_Y105_N0, M10K_X130_Y103_N0, M10K_X143_Y103_N0, M10K_X130_Y105_N0, M10K_X130_Y101_N0, M10K_X162_Y92_N0, M10K_X148_Y91_N0, M10K_X143_Y93_N0, M10K_X96_Y63_N0, M10K_X51_Y65_N0, M10K_X43_Y60_N0, M10K_X67_Y27_N0, M10K_X27_Y68_N0, M10K_X143_Y41_N0, M10K_X27_Y56_N0, M10K_X75_Y84_N0, M10K_X96_Y65_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|altshift_taps:ofl_mh_reg_rtl_0|shift_taps_3ou:auto_generated|altsyncram_1l91:altsyncram5|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 9 14 9 14 yes no yes yes 126 9 14 9 14 126 1 0 None M10K_X130_Y77_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|altshift_taps:ofl_tv_reg_rtl_0|shift_taps_1ou:auto_generated|altsyncram_rk91:altsyncram5|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 6 15 6 15 yes no yes yes 90 6 15 6 15 90 1 0 None M10K_X67_Y34_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|altshift_taps:chisquare_reg_rtl_0|shift_taps_5ru:auto_generated|altsyncram_7r91:altsyncram5|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 22 336 22 336 yes no yes yes 7392 22 336 22 336 7392 9 0 None M10K_X130_Y25_N0, M10K_X143_Y25_N0, M10K_X148_Y25_N0, M10K_X143_Y24_N0, M10K_X143_Y22_N0, M10K_X143_Y23_N0, M10K_X130_Y24_N0, M10K_X130_Y23_N0, M10K_X130_Y22_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|altshift_taps:ofl1_reg_rtl_0|shift_taps_imu:auto_generated|altsyncram_sh91:altsyncram5|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 5 7 5 7 yes no yes yes 35 5 7 5 7 35 1 0 None M10K_X111_Y36_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|altshift_taps:passes_reg_rtl_0|shift_taps_tnu:auto_generated|altsyncram_ok91:altsyncram5|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 20 6 20 6 yes no yes yes 120 20 6 20 6 120 1 0 None M10K_X130_Y20_N0 Don't care New data New data Yes
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X124_Y36_N0, LAB_X121_Y36_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X121_Y34_N0, LAB_X124_Y34_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X124_Y41_N0, LAB_X131_Y41_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:3:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X124_Y42_N0, LAB_X131_Y42_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:4:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X141_Y37_N0, LAB_X146_Y37_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:5:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X131_Y37_N0, LAB_X131_Y36_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:6:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X124_Y37_N0, LAB_X121_Y37_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X131_Y38_N0, LAB_X141_Y38_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 20 64 20 1280 0 40 None LAB_X146_Y40_N0, LAB_X141_Y40_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:9:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|ALTDPRAM_INSTANCE MLAB Simple Dual Port Single Clock 64 20 64 20 yes no no no 1280 64 4 64 4 256 0 8 None LAB_X131_Y39_N0, LAB_X141_Y39_N0        
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|altsyncram_o1m1:FIFOram|ALTSYNCRAM M10K block Simple Dual Port Dual Clocks 256 200 256 200 yes no yes yes 51200 256 190 256 190 48640 5 0 None M10K_X143_Y38_N0, M10K_X143_Y39_N0, M10K_X130_Y38_N0, M10K_X143_Y40_N0, M10K_X130_Y40_N0 Don't care New data New data Yes
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX0HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|altsyncram_rn41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 3 1024 3 yes no yes no 3072 1024 3 1024 3 3072 1 0 None M10K_X43_Y114_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX1HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|altsyncram_rn41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 3 1024 3 yes no yes no 3072 1024 3 1024 3 3072 1 0 None M10K_X43_Y116_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX2HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|altsyncram_rn41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 3 1024 3 yes no yes no 3072 1024 3 1024 3 3072 1 0 None M10K_X35_Y116_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX3HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|altsyncram_rn41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 3 1024 3 yes no yes no 3072 1024 3 1024 3 3072 1 0 None M10K_X35_Y115_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX4HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|altsyncram_rn41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 3 1024 3 yes no yes no 3072 1024 3 1024 3 3072 1 0 None M10K_X43_Y113_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX5HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|altsyncram_rn41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 3 1024 3 yes no yes no 3072 1024 3 1024 3 3072 1 0 None M10K_X43_Y115_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:SCT0HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|altsyncram_rn41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 3 1024 3 yes no yes no 3072 1024 3 1024 3 3072 1 0 None M10K_X51_Y110_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:SCT1HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|altsyncram_rn41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 3 1024 3 yes no yes no 3072 1024 3 1024 3 3072 1 0 None M10K_X43_Y112_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:SCT2HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|altsyncram_rn41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 3 1024 3 yes no yes no 3072 1024 3 1024 3 3072 1 0 None M10K_X35_Y114_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:SCT3HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|altsyncram_rn41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 3 1024 3 yes no yes no 3072 1024 3 1024 3 3072 1 0 None M10K_X75_Y112_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:SCT4HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|altsyncram_rn41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 3 1024 3 yes no yes no 3072 1024 3 1024 3 3072 1 0 None M10K_X75_Y111_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_layermap:LAYERMAPFIFO|dcfifo:dcfifo_component|dcfifo_t0m1:auto_generated|altsyncram_pq41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 11 1024 11 yes no yes no 11264 1024 11 1024 11 11264 2 0 None M10K_X51_Y108_N0, M10K_X59_Y108_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX0FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|altsyncram_br41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 29 1024 29 yes no yes no 29696 1024 29 1024 29 29696 3 0 None M10K_X35_Y105_N0, M10K_X35_Y106_N0, M10K_X27_Y106_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX1FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|altsyncram_br41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 29 1024 29 yes no yes no 29696 1024 29 1024 29 29696 3 0 None M10K_X51_Y106_N0, M10K_X43_Y106_N0, M10K_X43_Y105_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX2FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|altsyncram_br41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 29 1024 29 yes no yes no 29696 1024 29 1024 29 29696 3 0 None M10K_X27_Y107_N0, M10K_X27_Y109_N0, M10K_X27_Y108_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX3FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|altsyncram_br41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 29 1024 29 yes no yes no 29696 1024 29 1024 29 29696 3 0 None M10K_X35_Y110_N0, M10K_X35_Y109_N0, M10K_X35_Y111_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX4FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|altsyncram_br41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 29 1024 29 yes no yes no 29696 1024 29 1024 29 29696 3 0 None M10K_X43_Y107_N0, M10K_X35_Y107_N0, M10K_X35_Y108_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX5FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|altsyncram_br41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 29 1024 29 yes no yes no 29696 1024 29 1024 29 29696 3 0 None M10K_X43_Y108_N0, M10K_X43_Y110_N0, M10K_X43_Y111_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_road:ROADFIFO|dcfifo:dcfifo_component|dcfifo_11m1:auto_generated|altsyncram_tq41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 22 1024 22 yes no yes yes 22528 1024 22 1024 22 22528 3 0 None M10K_X43_Y104_N0, M10K_X43_Y103_N0, M10K_X43_Y102_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_sctlayer:SCT0FIFO|dcfifo:dcfifo_component|dcfifo_31m1:auto_generated|altsyncram_vq41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 14 1024 14 yes no yes yes 14336 1024 14 1024 14 14336 2 0 None M10K_X59_Y109_N0, M10K_X59_Y110_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_sctlayer:SCT1FIFO|dcfifo:dcfifo_component|dcfifo_31m1:auto_generated|altsyncram_vq41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 14 1024 14 yes no yes yes 14336 1024 14 1024 14 14336 2 0 None M10K_X51_Y109_N0, M10K_X43_Y109_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_sctlayer:SCT2FIFO|dcfifo:dcfifo_component|dcfifo_31m1:auto_generated|altsyncram_vq41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 14 1024 14 yes no yes yes 14336 1024 14 1024 14 14336 2 0 None M10K_X35_Y112_N0, M10K_X35_Y113_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_sctlayer:SCT3FIFO|dcfifo:dcfifo_component|dcfifo_31m1:auto_generated|altsyncram_vq41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 14 1024 14 yes no yes yes 14336 1024 14 1024 14 14336 2 0 None M10K_X67_Y111_N0, M10K_X67_Y112_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_sctlayer:SCT4FIFO|dcfifo:dcfifo_component|dcfifo_31m1:auto_generated|altsyncram_vq41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 14 1024 14 yes no yes yes 14336 1024 14 1024 14 14336 2 0 None M10K_X67_Y110_N0, M10K_X75_Y110_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_sector:SECTORFIFO|dcfifo:dcfifo_component|dcfifo_v0m1:auto_generated|altsyncram_rq41:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 12 1024 12 yes no yes yes 12288 1024 12 1024 12 12288 2 0 None M10K_X59_Y107_N0, M10K_X51_Y107_N0 Don't care New data New data No - Address Too Wide
TFInputBufferLogic:TFInputBufferLogic_inst|TFInputFIFO:ATFINPUTFIFO|fifo_dotf_tfend:FIFO|scfifo:scfifo_component|scfifo_nhg1:auto_generated|a_dpfifo_h6e1:dpfifo|altsyncram_t1m1:FIFOram|ALTDPRAM_INSTANCE MLAB Simple Dual Port Dual Clocks 16 256 16 256 yes no no yes 4096 16 208 16 208 3328 0 208 None LAB_X44_Y106_N0, LAB_X36_Y106_N0, LAB_X36_Y105_N0, LAB_X44_Y104_N0, LAB_X52_Y104_N0, LAB_X52_Y105_N0, LAB_X60_Y108_N0, LAB_X68_Y108_N0, LAB_X68_Y104_N0, LAB_X52_Y103_N0, LAB_X60_Y103_N0        
TFSpyBuffers:TFSpyBuffers_inst|VMEBuffBlock:VMEBuffBlock_TF_inst_constants|altsyncram:altsyncram_component|altsyncram_vq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 256 32 256 32 yes no yes no 8192 256 32 256 32 8192 1 0 None M10K_X35_Y54_N0 Don't care New data New data No - Read Address Using Clock 1 on Port B
TFSpyBuffers:TFSpyBuffers_inst|VMEBuffBlock:VMEBuffBlock_TF_inst_tracks|altsyncram:altsyncram_component|altsyncram_l014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 2048 32 2048 32 yes no yes no 65536 2048 32 2048 32 65536 7 0 None M10K_X35_Y47_N0, M10K_X35_Y45_N0, M10K_X27_Y47_N0, M10K_X35_Y46_N0, M10K_X27_Y49_N0, M10K_X35_Y48_N0, M10K_X27_Y45_N0 Don't care New data New data No - Address Too Wide
TFSpyBuffers:TFSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_TF:0:VMEBuffBlock_TF_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X43_Y96_N0, M10K_X35_Y96_N0 Don't care New data New data No - Address Too Wide
TFSpyBuffers:TFSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_TF:10:VMEBuffBlock_TF_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X51_Y92_N0, M10K_X51_Y93_N0 Don't care New data New data No - Address Too Wide
TFSpyBuffers:TFSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_TF:11:VMEBuffBlock_TF_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X59_Y92_N0, M10K_X67_Y93_N0 Don't care New data New data No - Address Too Wide
TFSpyBuffers:TFSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_TF:1:VMEBuffBlock_TF_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X35_Y94_N0, M10K_X35_Y93_N0 Don't care New data New data No - Address Too Wide
TFSpyBuffers:TFSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_TF:2:VMEBuffBlock_TF_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X43_Y95_N0, M10K_X35_Y95_N0 Don't care New data New data No - Address Too Wide
TFSpyBuffers:TFSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_TF:3:VMEBuffBlock_TF_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X51_Y96_N0, M10K_X43_Y93_N0 Don't care New data New data No - Address Too Wide
TFSpyBuffers:TFSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_TF:4:VMEBuffBlock_TF_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X67_Y95_N0, M10K_X75_Y95_N0 Don't care New data New data No - Address Too Wide
TFSpyBuffers:TFSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_TF:5:VMEBuffBlock_TF_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X67_Y94_N0, M10K_X75_Y94_N0 Don't care New data New data No - Address Too Wide
TFSpyBuffers:TFSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_TF:6:VMEBuffBlock_TF_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X59_Y95_N0, M10K_X51_Y95_N0 Don't care New data New data No - Address Too Wide
TFSpyBuffers:TFSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_TF:7:VMEBuffBlock_TF_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X59_Y94_N0, M10K_X59_Y93_N0 Don't care New data New data No - Address Too Wide
TFSpyBuffers:TFSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_TF:8:VMEBuffBlock_TF_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X67_Y92_N0, M10K_X67_Y91_N0 Don't care New data New data No - Address Too Wide
TFSpyBuffers:TFSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_TF:9:VMEBuffBlock_TF_inst|altsyncram:altsyncram_component|altsyncram_nq04:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 32 512 32 yes no yes no 16384 512 32 512 32 16384 2 0 None M10K_X59_Y89_N0, M10K_X75_Y93_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:VMEBuffBlock_gendata_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X19_Y44_N0, M10K_X19_Y46_N0, M10K_X27_Y46_N0, M10K_X19_Y45_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:VMEBuffBlock_merge_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X27_Y44_N0, M10K_X27_Y42_N0, M10K_X35_Y42_N0, M10K_X27_Y43_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:\pix_spy_gen:0:VMEBuffBlock_pixhits_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X35_Y26_N0, M10K_X35_Y33_N0, M10K_X35_Y25_N0, M10K_X35_Y34_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:\pix_spy_gen:10:VMEBuffBlock_pixhits_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X96_Y90_N0, M10K_X96_Y86_N0, M10K_X101_Y86_N0, M10K_X96_Y88_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:\pix_spy_gen:11:VMEBuffBlock_pixhits_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X59_Y85_N0, M10K_X59_Y84_N0, M10K_X51_Y84_N0, M10K_X51_Y85_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:\pix_spy_gen:1:VMEBuffBlock_pixhits_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X27_Y54_N0, M10K_X19_Y55_N0, M10K_X27_Y53_N0, M10K_X19_Y57_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:\pix_spy_gen:2:VMEBuffBlock_pixhits_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X51_Y88_N0, M10K_X51_Y91_N0, M10K_X43_Y89_N0, M10K_X51_Y89_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:\pix_spy_gen:3:VMEBuffBlock_pixhits_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X75_Y88_N0, M10K_X67_Y88_N0, M10K_X67_Y89_N0, M10K_X75_Y89_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:\pix_spy_gen:4:VMEBuffBlock_pixhits_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X101_Y91_N0, M10K_X96_Y91_N0, M10K_X96_Y93_N0, M10K_X96_Y89_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:\pix_spy_gen:5:VMEBuffBlock_pixhits_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X130_Y92_N0, M10K_X130_Y98_N0, M10K_X130_Y97_N0, M10K_X130_Y93_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:\pix_spy_gen:6:VMEBuffBlock_pixhits_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X111_Y94_N0, M10K_X111_Y93_N0, M10K_X101_Y94_N0, M10K_X101_Y93_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:\pix_spy_gen:7:VMEBuffBlock_pixhits_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X120_Y92_N0, M10K_X120_Y91_N0, M10K_X120_Y89_N0, M10K_X120_Y90_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:\pix_spy_gen:8:VMEBuffBlock_pixhits_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X120_Y88_N0, M10K_X111_Y87_N0, M10K_X111_Y89_N0, M10K_X101_Y89_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:\pix_spy_gen:9:VMEBuffBlock_pixhits_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X120_Y96_N0, M10K_X130_Y95_N0, M10K_X130_Y96_N0, M10K_X120_Y95_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:\road_spy_gen:0:VMEBuffBlock_roads_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X19_Y47_N0, M10K_X19_Y51_N0, M10K_X19_Y49_N0, M10K_X27_Y51_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:\road_spy_gen:1:VMEBuffBlock_roads_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X27_Y50_N0, M10K_X19_Y50_N0, M10K_X19_Y53_N0, M10K_X19_Y54_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:\road_spy_gen:2:VMEBuffBlock_roads_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X27_Y48_N0, M10K_X19_Y48_N0, M10K_X19_Y52_N0, M10K_X27_Y52_N0 Don't care New data New data No - Address Too Wide
TXSpyBuffers:TXSpyBuffers_inst|VMEBuffBlock:\road_spy_gen:3:VMEBuffBlock_roads_inst|altsyncram:altsyncram_component|altsyncram_5014:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 4 0 None M10K_X19_Y43_N0, M10K_X19_Y41_N0, M10K_X19_Y42_N0, M10K_X27_Y41_N0 Don't care New data New data No - Address Too Wide
VMEBuffAddrBlock:epcq_vmebuff_inst|vme_buffer1:vmebuff_inst|altsyncram:altsyncram_component|altsyncram_1114:auto_generated|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 4096 32 4096 32 yes no yes no 131072 4096 32 4096 32 131072 16 0 None M10K_X35_Y27_N0, M10K_X27_Y30_N0, M10K_X27_Y28_N0, M10K_X27_Y29_N0, M10K_X43_Y29_N0, M10K_X43_Y28_N0, M10K_X43_Y32_N0, M10K_X43_Y30_N0, M10K_X35_Y28_N0, M10K_X35_Y32_N0, M10K_X35_Y31_N0, M10K_X35_Y29_N0, M10K_X43_Y27_N0, M10K_X43_Y31_N0, M10K_X35_Y30_N0, M10K_X27_Y31_N0 Don't care New data New data No - Address Too Wide
epcq_control:epcq_contro_inst|VMEWriteFIFOBlock:epcq_buffer_inst|VMEWriteFIFO:fifo_inst|dcfifo:dcfifo_component|dcfifo_v2p1:auto_generated|altsyncram_aj91:fifo_ram|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 256 32 256 32 yes no yes yes 8192 256 32 256 32 8192 1 0 None M10K_X27_Y27_N0 Don't care New data New data No - Read Address Using Clock 1 on Port B
epcq_control:epcq_contro_inst|epcqio:epcqio_inst|epcqio_altasmi_parallel_bmo2:epcqio_altasmi_parallel_bmo2_component|scfifo:scfifo3|scfifo_99c1:auto_generated|a_dpfifo_k651:dpfifo|dpram_am31:FIFOram|altsyncram_e0q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 8 512 8 yes no yes no 4096 512 8 512 8 4096 1 0 None M10K_X19_Y30_N0 Don't care New data New data No - Address Too Wide
user_logic_mux:\gen_tx_mux:0:user_logic_mux|user_logic_fifo:tx2|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X19_Y3_N0, M10K_X19_Y1_N0 Don't care New data New data No - Address Too Wide
user_logic_mux:\gen_tx_mux:10:user_logic_mux|user_logic_fifo:tx2|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X162_Y1_N0, M10K_X162_Y3_N0 Don't care New data New data No - Address Too Wide
user_logic_mux:\gen_tx_mux:11:user_logic_mux|user_logic_fifo:tx2|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X178_Y67_N0, M10K_X178_Y66_N0 Don't care New data New data No - Address Too Wide
user_logic_mux:\gen_tx_mux:1:user_logic_mux|user_logic_fifo:tx2|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X5_Y33_N0, M10K_X19_Y33_N0 Don't care New data New data No - Address Too Wide
user_logic_mux:\gen_tx_mux:2:user_logic_mux|user_logic_fifo:tx2|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X19_Y26_N0, M10K_X27_Y26_N0 Don't care New data New data No - Address Too Wide
user_logic_mux:\gen_tx_mux:3:user_logic_mux|user_logic_fifo:tx2|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X5_Y30_N0, M10K_X5_Y32_N0 Don't care New data New data No - Address Too Wide
user_logic_mux:\gen_tx_mux:4:user_logic_mux|user_logic_fifo:tx2|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X162_Y11_N0, M10K_X162_Y10_N0 Don't care New data New data No - Address Too Wide
user_logic_mux:\gen_tx_mux:5:user_logic_mux|user_logic_fifo:tx2|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X148_Y16_N0, M10K_X143_Y16_N0 Don't care New data New data No - Address Too Wide
user_logic_mux:\gen_tx_mux:6:user_logic_mux|user_logic_fifo:tx2|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X178_Y49_N0, M10K_X178_Y50_N0 Don't care New data New data No - Address Too Wide
user_logic_mux:\gen_tx_mux:7:user_logic_mux|user_logic_fifo:tx2|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X178_Y41_N0, M10K_X178_Y42_N0 Don't care New data New data No - Address Too Wide
user_logic_mux:\gen_tx_mux:8:user_logic_mux|user_logic_fifo:tx2|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X178_Y55_N0, M10K_X178_Y54_N0 Don't care New data New data No - Address Too Wide
user_logic_mux:\gen_tx_mux:9:user_logic_mux|user_logic_fifo:tx2|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|dpram_pp61:FIFOram|altsyncram_i3q1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port Dual Clocks 512 33 512 33 yes no yes no 16896 512 33 512 33 16896 2 0 None M10K_X178_Y32_N0, M10K_X178_Y33_N0 Don't care New data New data No - Address Too Wide