Name Location Fan-Out Usage Global Global Resource Used Global Line Name Enable Signal Source Name
DFSynchronization:DFSynchronization_inst|AFIFO32:headerfifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 MLABCELL_X60_Y26_N57 10 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|AFIFO32:headerfifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_rreq MLABCELL_X60_Y26_N54 12 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|AFIFO32:headerfifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_wreq MLABCELL_X60_Y26_N33 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|AFIFO32:trailerfifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X57_Y28_N45 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|AFIFO32:trailerfifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_rreq LABCELL_X57_Y28_N0 12 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|AFIFO32:trailerfifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_wreq LABCELL_X57_Y28_N39 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:0:ambroadcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X16_Y37_N51 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:0:ambroadcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_rreq LABCELL_X18_Y37_N6 12 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:0:ambroadcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_wreq MLABCELL_X15_Y37_N18 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:0:ambroadcon_inst|LWEN_N_delay FF_X4_Y45_N59 35 Clock enable, Sync. clear no -- -- --
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:1:ambroadcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X28_Y39_N33 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:1:ambroadcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_wreq LABCELL_X17_Y46_N0 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:1:ambroadcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_rreq LABCELL_X18_Y37_N36 12 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:1:ambroadcon_inst|LWEN_N_delay FF_X21_Y50_N41 35 Clock enable, Sync. clear no -- -- --
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:2:ambroadcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X21_Y37_N54 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:2:ambroadcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_rreq LABCELL_X18_Y37_N33 13 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:2:ambroadcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_wreq MLABCELL_X20_Y37_N30 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:2:ambroadcon_inst|LWEN_N_delay FF_X21_Y49_N44 35 Clock enable, Sync. clear no -- -- --
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:3:ambroadcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X23_Y34_N12 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:3:ambroadcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_rreq LABCELL_X18_Y37_N54 12 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:3:ambroadcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_wreq LABCELL_X23_Y34_N9 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|AMBConverter:\gen_ambroadcon:3:ambroadcon_inst|LWEN_N_delay FF_X15_Y34_N14 35 Clock enable, Sync. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:0:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X93_Y34_N57 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:0:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_rreq~0 LABCELL_X93_Y34_N36 15 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:0:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_wreq LABCELL_X93_Y34_N48 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:0:dfsctcon_inst|headeridx[2]~0 LABCELL_X40_Y26_N6 3 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:0:dfsctcon_inst|proc_fsm~1 LABCELL_X40_Y26_N42 4 Async. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:1:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X50_Y90_N57 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:1:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_wreq LABCELL_X50_Y90_N15 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:1:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_rreq~0 LABCELL_X50_Y90_N36 15 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:1:dfsctcon_inst|headeridx[2]~0 LABCELL_X17_Y40_N36 3 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:1:dfsctcon_inst|proc_fsm~2 LABCELL_X17_Y40_N48 4 Async. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:2:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X47_Y88_N30 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:2:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_rreq~0 LABCELL_X64_Y105_N3 15 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:2:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_wreq LABCELL_X47_Y88_N45 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:2:dfsctcon_inst|headeridx[2]~0 LABCELL_X34_Y32_N27 3 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:2:dfsctcon_inst|proc_fsm~2 LABCELL_X34_Y32_N6 4 Async. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:3:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X74_Y92_N30 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:3:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_rreq~0 MLABCELL_X76_Y92_N51 15 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:3:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_wreq MLABCELL_X76_Y92_N33 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:3:dfsctcon_inst|headeridx[2]~0 LABCELL_X64_Y88_N57 3 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:3:dfsctcon_inst|proc_fsm~2 LABCELL_X64_Y88_N42 4 Async. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:4:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X98_Y99_N48 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:4:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_rreq~0 LABCELL_X98_Y99_N24 15 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:4:dfsctcon_inst|AFIFO32:datafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_wreq LABCELL_X98_Y99_N57 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:4:dfsctcon_inst|headeridx[2]~0 LABCELL_X99_Y36_N54 3 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFConverter:\gen_dfsctcon:4:dfsctcon_inst|proc_fsm~2 LABCELL_X99_Y36_N51 4 Async. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:0:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X122_Y101_N15 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:0:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_rreq LABCELL_X122_Y101_N45 13 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:0:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_wreq LABCELL_X122_Y101_N30 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:0:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X125_Y102_N54 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:0:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_rreq LABCELL_X125_Y102_N30 12 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:0:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_wreq LABCELL_X125_Y102_N45 21 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:0:dfpixcon_inst|fsm.readdata FF_X164_Y100_N50 37 Sync. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:0:dfpixcon_inst|headeridx[2]~0 MLABCELL_X174_Y100_N18 3 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:0:dfpixcon_inst|proc_fsm~0 MLABCELL_X174_Y100_N3 4 Async. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:1:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 MLABCELL_X92_Y104_N39 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:1:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_rreq MLABCELL_X92_Y104_N21 13 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:1:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_wreq LABCELL_X91_Y104_N6 21 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:1:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X108_Y97_N36 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:1:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_wreq LABCELL_X108_Y97_N48 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:1:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_rreq LABCELL_X108_Y97_N39 12 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:1:dfpixcon_inst|fsm.readdata FF_X127_Y94_N26 37 Sync. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:1:dfpixcon_inst|headeridx[2]~0 LABCELL_X134_Y94_N15 3 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:1:dfpixcon_inst|proc_fsm~0 LABCELL_X118_Y95_N9 4 Async. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:2:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X98_Y96_N6 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:2:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_wreq LABCELL_X98_Y96_N51 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:2:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 MLABCELL_X97_Y93_N6 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:2:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_rreq MLABCELL_X97_Y93_N15 12 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:2:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_wreq MLABCELL_X97_Y93_N9 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:2:dfpixcon_inst|fifo_rdreq LABCELL_X98_Y96_N57 13 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:2:dfpixcon_inst|fsm.readdata FF_X122_Y90_N11 37 Sync. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:2:dfpixcon_inst|headeridx[2]~0 LABCELL_X122_Y90_N54 3 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:2:dfpixcon_inst|proc_fsm~0 LABCELL_X122_Y90_N12 4 Async. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:3:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 MLABCELL_X73_Y104_N54 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:3:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_wreq MLABCELL_X73_Y104_N33 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:3:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X110_Y94_N36 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:3:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_rreq LABCELL_X110_Y94_N30 12 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:3:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_wreq LABCELL_X110_Y94_N54 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:3:dfpixcon_inst|fifo_rdreq LABCELL_X74_Y111_N57 13 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:3:dfpixcon_inst|fsm.readdata FF_X141_Y76_N14 37 Sync. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:3:dfpixcon_inst|headeridx[2]~0 LABCELL_X142_Y76_N21 3 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:3:dfpixcon_inst|proc_fsm~0 LABCELL_X142_Y76_N57 4 Async. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:4:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X100_Y110_N15 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:4:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_rreq LABCELL_X100_Y110_N21 13 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:4:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_wreq LABCELL_X100_Y110_N24 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:4:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 MLABCELL_X102_Y110_N27 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:4:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_rreq MLABCELL_X102_Y110_N24 12 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:4:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_wreq MLABCELL_X102_Y110_N9 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:4:dfpixcon_inst|fsm.readdata FF_X152_Y96_N32 37 Sync. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:4:dfpixcon_inst|headeridx[2]~0 MLABCELL_X151_Y96_N57 3 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:4:dfpixcon_inst|proc_fsm~0 MLABCELL_X146_Y96_N42 4 Async. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:5:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 MLABCELL_X105_Y110_N9 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:5:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|valid_wreq MLABCELL_X105_Y110_N21 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:5:dfpixcon_inst|AFIFO32:hitdatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_rreq MLABCELL_X105_Y110_N27 13 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:5:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|a_fefifo_s7f:fifo_state|_~0 LABCELL_X107_Y110_N12 9 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:5:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_rreq LABCELL_X107_Y110_N15 12 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:5:dfpixcon_inst|AFIFO32:ssiddatafifo_inst|scfifo:scfifo_component|scfifo_tsb1:auto_generated|a_dpfifo_ie91:dpfifo|valid_wreq LABCELL_X107_Y110_N6 20 Clock enable, Write enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:5:dfpixcon_inst|fsm.readdata FF_X131_Y78_N2 37 Sync. clear no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:5:dfpixcon_inst|headeridx[2]~0 LABCELL_X132_Y78_N0 3 Clock enable no -- -- --
DFSynchronization:DFSynchronization_inst|DFPIXConverter:\gen_dfpixcon:5:dfpixcon_inst|proc_fsm~0 LABCELL_X132_Y78_N42 4 Async. clear no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:0:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 LABCELL_X56_Y104_N30 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:0:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~0 LABCELL_X58_Y104_N48 25 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:10:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 LABCELL_X106_Y113_N9 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:10:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~0 LABCELL_X109_Y113_N54 22 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:11:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 LABCELL_X99_Y113_N48 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:11:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~1 LABCELL_X103_Y111_N48 25 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:1:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 LABCELL_X58_Y113_N3 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:1:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~0 LABCELL_X55_Y113_N30 25 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:2:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 MLABCELL_X92_Y104_N45 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:2:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~0 LABCELL_X93_Y105_N45 22 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:3:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 LABCELL_X125_Y108_N45 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:3:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~0 LABCELL_X125_Y109_N24 25 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:4:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 LABCELL_X71_Y103_N36 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:4:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~1 MLABCELL_X73_Y101_N54 25 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:5:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 LABCELL_X69_Y106_N39 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:5:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~0 LABCELL_X71_Y107_N54 25 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:6:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 MLABCELL_X73_Y113_N6 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:6:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~0 MLABCELL_X68_Y113_N9 22 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:7:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 LABCELL_X117_Y116_N12 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:7:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~2 LABCELL_X114_Y116_N30 25 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:8:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 LABCELL_X100_Y118_N6 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:8:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~2 LABCELL_X99_Y118_N3 25 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:9:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 LABCELL_X65_Y116_N33 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_pix_streams:9:PIX_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~1 LABCELL_X61_Y116_N3 25 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_sct_streams:0:SCT_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 LABCELL_X107_Y107_N54 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_sct_streams:0:SCT_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~1 MLABCELL_X105_Y107_N54 25 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_sct_streams:1:SCT_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 MLABCELL_X97_Y107_N54 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_sct_streams:1:SCT_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~1 MLABCELL_X97_Y108_N57 25 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_sct_streams:2:SCT_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 LABCELL_X64_Y105_N27 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_sct_streams:2:SCT_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~0 MLABCELL_X73_Y105_N21 22 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_sct_streams:3:SCT_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 LABCELL_X117_Y112_N57 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_sct_streams:3:SCT_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~2 LABCELL_X112_Y112_N33 25 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_sct_streams:4:SCT_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_rdreq~1 LABCELL_X110_Y101_N36 23 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|fifo_32_to_32_forDOwClr:\gen_sct_streams:4:SCT_STREAM_INST|dcfifo:dcfifo_component|dcfifo_2tp1:auto_generated|valid_wrreq~1 LABCELL_X110_Y101_N15 24 Clock enable, Write enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|hit_stream_addr_reg[4]~0 MLABCELL_X76_Y101_N48 5 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|roads_wren_reg FF_X32_Y42_N46 33 Sync. load no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|tx_fifo:road_fifo|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|_~0 LABCELL_X33_Y38_N42 9 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|tx_fifo:road_fifo|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|valid_rreq LABCELL_X41_Y38_N15 13 Clock enable no -- -- --
DOProcessVMEInput:DOProcessVMEInput_inst|tx_fifo:road_fifo|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|valid_wreq LABCELL_X33_Y38_N48 20 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|DO1_WRready_rising LABCELL_X57_Y101_N18 581 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:0:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X23_Y90_N54 18 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:0:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X58_Y94_N48 20 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:0:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X58_Y94_N47 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:10:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X94_Y100_N48 16 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:10:VMEBuffBlock_DO_inst|dowrite~0 MLABCELL_X97_Y100_N54 18 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:10:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X97_Y100_N50 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:11:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X88_Y96_N54 16 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:11:VMEBuffBlock_DO_inst|dowrite~0 MLABCELL_X87_Y98_N27 18 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:11:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X86_Y98_N47 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:12:VMEBuffBlock_DO_inst|WideAnd0 MLABCELL_X83_Y94_N54 19 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:12:VMEBuffBlock_DO_inst|dowrite~0 MLABCELL_X87_Y98_N51 21 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:12:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X86_Y98_N11 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:13:VMEBuffBlock_DO_inst|WideAnd0 MLABCELL_X92_Y96_N54 16 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:13:VMEBuffBlock_DO_inst|dowrite~0 MLABCELL_X87_Y98_N45 18 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:13:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X86_Y98_N14 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:14:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X79_Y98_N12 16 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:14:VMEBuffBlock_DO_inst|dowrite~0 MLABCELL_X87_Y98_N33 18 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:14:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X86_Y98_N2 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:15:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X57_Y86_N54 18 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:15:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X58_Y94_N27 20 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:15:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X58_Y94_N35 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:16:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X63_Y90_N54 20 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:16:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X58_Y94_N15 22 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:16:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X58_Y94_N23 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:17:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X50_Y86_N54 19 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:17:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X39_Y101_N30 21 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:17:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X39_Y101_N41 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:18:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X37_Y98_N51 16 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:18:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X39_Y101_N24 18 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:18:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X39_Y101_N11 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:19:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X34_Y98_N54 18 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:19:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X39_Y101_N48 20 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:19:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X39_Y101_N8 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:1:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X26_Y93_N48 20 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:1:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X57_Y100_N21 22 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:1:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X56_Y102_N5 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:20:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X32_Y98_N33 17 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:20:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X39_Y101_N0 19 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:20:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X39_Y101_N56 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:21:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X40_Y98_N54 20 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:21:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X39_Y101_N45 22 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:21:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X39_Y101_N38 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:22:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X55_Y98_N54 19 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:22:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X56_Y110_N48 21 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:22:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X56_Y110_N8 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:23:VMEBuffBlock_DO_inst|WideAnd0 MLABCELL_X68_Y98_N18 16 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:23:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X56_Y110_N30 18 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:23:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X56_Y110_N38 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:24:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X49_Y98_N54 19 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:24:VMEBuffBlock_DO_inst|dowrite~0 MLABCELL_X52_Y112_N0 21 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:24:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X52_Y112_N56 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:25:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X48_Y98_N54 18 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:25:VMEBuffBlock_DO_inst|dowrite~0 MLABCELL_X36_Y112_N36 20 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:25:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X36_Y112_N56 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:26:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X63_Y98_N54 18 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:26:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X63_Y108_N48 20 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:26:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X63_Y108_N23 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:27:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X61_Y98_N54 18 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:27:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X69_Y111_N0 20 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:27:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X69_Y111_N56 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:28:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X64_Y99_N54 17 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:28:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X63_Y108_N15 19 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:28:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X63_Y108_N8 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:29:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X47_Y101_N30 16 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:29:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X39_Y101_N12 18 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:29:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X39_Y101_N23 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:2:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X31_Y90_N54 16 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:2:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X58_Y94_N3 18 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:2:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X58_Y94_N59 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:3:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X34_Y90_N18 16 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:3:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X57_Y100_N6 18 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:3:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X57_Y100_N5 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:4:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X34_Y91_N39 16 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:4:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X57_Y100_N57 18 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:4:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X57_Y100_N17 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:5:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X41_Y90_N48 16 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:5:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X57_Y100_N24 18 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:5:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X57_Y100_N50 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:6:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X42_Y90_N54 20 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:6:VMEBuffBlock_DO_inst|dowrite~0 LABCELL_X58_Y94_N39 22 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:6:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X42_Y95_N44 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:7:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X88_Y98_N51 16 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:7:VMEBuffBlock_DO_inst|dowrite~0 MLABCELL_X87_Y98_N39 18 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:7:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X97_Y100_N2 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:8:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X94_Y98_N24 17 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:8:VMEBuffBlock_DO_inst|dowrite~0 MLABCELL_X102_Y100_N42 19 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:8:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X102_Y100_N41 3 Clock enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:9:VMEBuffBlock_DO_inst|WideAnd0 LABCELL_X94_Y96_N42 17 Sync. clear no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:9:VMEBuffBlock_DO_inst|dowrite~0 MLABCELL_X87_Y98_N57 19 Clock enable, Write enable no -- -- --
DOSpyBuffers:DOSpyBuffers_inst|VMEBuffBlock:\gen_VMEBuffBlock_DO:9:VMEBuffBlock_DO_inst|test_mode_n_reg FF_X86_Y98_N50 3 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[23]~1 MLABCELL_X20_Y124_N3 3 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[5]~2 MLABCELL_X20_Y124_N39 6 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[8]~0 MLABCELL_X20_Y124_N54 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|always1~0 LABCELL_X21_Y124_N21 17 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[13]~0 MLABCELL_X20_Y124_N6 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[5]~1 MLABCELL_X20_Y124_N0 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|current_byte[1]~3 LABCELL_X23_Y124_N54 3 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[6]~4 LABCELL_X21_Y125_N33 7 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data~0 LABCELL_X24_Y124_N3 35 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_ADDR2 FF_X20_Y124_N29 7 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_ADDR3 FF_X20_Y124_N26 12 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.READ_SEND_WAIT FF_X26_Y125_N44 30 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.WRITE_WAIT FF_X24_Y124_N2 19 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|unshifted_byteenable[3]~1 LABCELL_X24_Y123_N0 5 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[15]~3 LABCELL_X28_Y123_N0 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[23]~1 LABCELL_X28_Y123_N21 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[29]~2 MLABCELL_X20_Y123_N54 9 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[7]~0 LABCELL_X28_Y123_N27 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_sc_fifo:fifo|internal_out_ready LABCELL_X28_Y124_N12 3 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_sc_fifo:fifo|write LABCELL_X29_Y124_N57 10 Clock enable, Write enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_bytes_to_packets:b2p|always2~0 LABCELL_X28_Y124_N15 9 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_bytes_to_packets:b2p|out_channel[7]~0 LABCELL_X17_Y124_N39 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|full0 FF_X102_Y121_N41 21 Clock enable, Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|full1~1 LABCELL_X103_Y121_N51 10 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|take_in_data LABCELL_X26_Y124_N39 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|sync_control_signal~0 LABCELL_X29_Y124_N30 9 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal14~0 LABCELL_X109_Y120_N30 15 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal14~1 LABCELL_X106_Y120_N39 3 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover|out_valid LABCELL_X58_Y124_N42 9 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[6] FF_X109_Y120_N28 1 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[1]~0 LABCELL_X107_Y120_N51 8 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[1]~1 LABCELL_X110_Y120_N27 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|clock_sense_reset_n FF_X106_Y120_N37 8 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[0]~1 LABCELL_X109_Y120_N39 11 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_in[1]~0 LABCELL_X106_Y122_N18 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0]~10 LABCELL_X108_Y121_N6 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_debug[0]~1 LABCELL_X107_Y120_N54 2 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[0]~1 LABCELL_X106_Y120_N33 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[14]~0 LABCELL_X110_Y121_N18 12 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[0]~1 LABCELL_X110_Y122_N48 4 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[0]~2 LABCELL_X109_Y121_N30 4 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_data[0]~0 LABCELL_X112_Y119_N30 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|offset[7]~0 LABCELL_X106_Y120_N18 9 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[0]~1 LABCELL_X110_Y121_N57 8 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[0]~2 LABCELL_X110_Y121_N24 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[0]~1 LABCELL_X110_Y121_N12 4 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_length[0]~0 LABCELL_X109_Y122_N12 13 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[0]~9 LABCELL_X107_Y123_N0 10 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[7]~0 LABCELL_X107_Y121_N33 20 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[0]~1 LABCELL_X106_Y122_N30 20 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[7]~3 LABCELL_X106_Y122_N36 12 Sync. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter[0]~1 LABCELL_X110_Y121_N21 4 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_length[0]~2 LABCELL_X109_Y122_N24 3 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state~17 LABCELL_X110_Y120_N12 3 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer|dreg[1] FF_X18_Y125_N5 43 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_avalon_st_packets_to_bytes:p2b|in_ready~0 LABCELL_X26_Y124_N33 14 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_dmaster:dmaster|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out FF_X15_Y130_N49 234 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|RLDRAMII_p0_acv_ldc:acv_ck_ldc|adc_clk_cps CLKPHASESELECT_X14_Y137_N4 1 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|RLDRAMII_p0_clock_pair_generator:uclk_generator|wire_pseudo_diffa_oebout[0] PSEUDODIFFOUT_X19_Y137_N37 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|RLDRAMII_p0_clock_pair_generator:uclk_generator|wire_pseudo_diffa_oeout[0] PSEUDODIFFOUT_X19_Y137_N37 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|diff_oe PSEUDODIFFOUT_X14_Y137_N43 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|diff_oe_bar PSEUDODIFFOUT_X14_Y137_N43 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|dq_shifted_clock CLKPHASESELECT_X20_Y137_N5 20 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|dq_shifted_clock~_Duplicate CLKPHASESELECT_X14_Y137_N5 17 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|dqs_shifted_clock CLKPHASESELECT_X20_Y137_N1 13 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|dqs_shifted_clock~_Duplicate CLKPHASESELECT_X14_Y137_N1 12 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|dqsbusout DELAYCHAIN_X20_Y137_N19 38 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|fr_os_oct DDIOOUT_X20_Y137_N7 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|fr_os_oct~_Duplicate DDIOOUT_X14_Y137_N7 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|hr_seq_clock CLKPHASESELECT_X20_Y137_N6 44 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|hr_seq_clock~_Duplicate CLKPHASESELECT_X14_Y137_N6 38 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[0].delayed_oe_1 DELAYCHAIN_X22_Y137_N41 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[10].delayed_oe_1 DELAYCHAIN_X20_Y137_N64 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[11].delayed_oe_1 DELAYCHAIN_X26_Y137_N7 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[12].delayed_oe_1 DELAYCHAIN_X17_Y137_N7 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[13].delayed_oe_1 DELAYCHAIN_X20_Y137_N47 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[14].delayed_oe_1 DELAYCHAIN_X17_Y137_N24 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[15].delayed_oe_1 DELAYCHAIN_X24_Y137_N7 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[16].delayed_oe_1 DELAYCHAIN_X24_Y137_N41 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[17].delayed_oe_1 DELAYCHAIN_X20_Y137_N81 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[1].delayed_oe_1 DELAYCHAIN_X19_Y137_N24 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[2].delayed_oe_1 DELAYCHAIN_X16_Y137_N41 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[3].delayed_oe_1 DELAYCHAIN_X16_Y137_N24 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[4].delayed_oe_1 DELAYCHAIN_X26_Y137_N41 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[5].delayed_oe_1 DELAYCHAIN_X16_Y137_N7 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[6].delayed_oe_1 DELAYCHAIN_X19_Y137_N7 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[7].delayed_oe_1 DELAYCHAIN_X26_Y137_N24 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[8].delayed_oe_1 DELAYCHAIN_X17_Y137_N41 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[9].delayed_oe_1 DELAYCHAIN_X24_Y137_N24 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|diff_oe PSEUDODIFFOUT_X44_Y137_N3 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|diff_oe_bar PSEUDODIFFOUT_X44_Y137_N3 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|dq_shifted_clock CLKPHASESELECT_X50_Y137_N5 20 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|dq_shifted_clock~_Duplicate CLKPHASESELECT_X42_Y137_N5 16 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|dqs_shifted_clock CLKPHASESELECT_X50_Y137_N1 13 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|dqs_shifted_clock~_Duplicate CLKPHASESELECT_X42_Y137_N1 12 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|dqsbusout DELAYCHAIN_X50_Y137_N19 38 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|fr_os_oct DDIOOUT_X50_Y137_N7 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|fr_os_oct~_Duplicate DDIOOUT_X42_Y137_N7 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|hr_seq_clock CLKPHASESELECT_X50_Y137_N6 44 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|hr_seq_clock~_Duplicate CLKPHASESELECT_X42_Y137_N6 36 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[0].delayed_oe_1 DELAYCHAIN_X54_Y137_N7 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[10].delayed_oe_1 DELAYCHAIN_X56_Y137_N24 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[11].delayed_oe_1 DELAYCHAIN_X50_Y137_N64 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[12].delayed_oe_1 DELAYCHAIN_X52_Y137_N41 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[13].delayed_oe_1 DELAYCHAIN_X50_Y137_N81 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[14].delayed_oe_1 DELAYCHAIN_X42_Y137_N81 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[15].delayed_oe_1 DELAYCHAIN_X45_Y137_N41 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[16].delayed_oe_1 DELAYCHAIN_X56_Y137_N41 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[17].delayed_oe_1 DELAYCHAIN_X42_Y137_N64 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[1].delayed_oe_1 DELAYCHAIN_X45_Y137_N7 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[2].delayed_oe_1 DELAYCHAIN_X42_Y137_N47 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[3].delayed_oe_1 DELAYCHAIN_X48_Y137_N7 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[4].delayed_oe_1 DELAYCHAIN_X54_Y137_N41 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[5].delayed_oe_1 DELAYCHAIN_X45_Y137_N24 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[6].delayed_oe_1 DELAYCHAIN_X54_Y137_N24 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[7].delayed_oe_1 DELAYCHAIN_X48_Y137_N24 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[8].delayed_oe_1 DELAYCHAIN_X56_Y137_N7 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_new_io_pads:uio_pads|RLDRAMII_p0_altdqdqs_r:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen[9].delayed_oe_1 DELAYCHAIN_X50_Y137_N47 1 Output enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_reset:ureset|RLDRAMII_p0_reset_sync:ureset_addr_cmd_clk|reset_reg[14] FF_X31_Y136_N38 25 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_reset:ureset|RLDRAMII_p0_reset_sync:ureset_afi_clk|reset_reg[15] FF_X39_Y135_N59 29 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_reset:ureset|RLDRAMII_p0_reset_sync:ureset_afi_clk|reset_reg[17] FF_X39_Y135_N2 204 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_reset:ureset|RLDRAMII_p0_reset_sync:ureset_avl_clk|reset_reg[1] FF_X16_Y130_N14 4 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_reset:ureset|RLDRAMII_p0_reset_sync:ureset_ctl_reset_clk|reset_reg[15] FF_X17_Y134_N17 266 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_reset:ureset|RLDRAMII_p0_reset_sync:ureset_scc_clk|reset_reg[14] FF_X37_Y130_N2 174 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_reset:ureset|RLDRAMII_p0_reset_sync:ureset_seq_clk|reset_reg[14] FF_X26_Y131_N41 13 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_p0:p0|RLDRAMII_p0_memphy:umemphy|RLDRAMII_p0_reset:ureset|phy_reset_n LABCELL_X34_Y131_N48 78 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_pll0:pll0|afi_phy_clk PLLOUTPUTCOUNTER_X81_Y116_N1 1522 Clock yes Global Clock GCLK15 --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_pll0:pll0|pll2_phy~PLL_LVDS_OUTPUT_O_LOADEN PLLLVDSOUTPUT_X81_Y108_N2 1 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_pll0:pll0|pll2_phy~PLL_LVDS_OUTPUT_O_LVDSCLK PLLLVDSOUTPUT_X81_Y108_N2 1 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_pll0:pll0|pll3~PLL_DLL_OUTPUT_O_CLKOUT PLLDLLOUTPUT_X81_Y118_N2 1 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_pll0:pll0|pll3~PLL_LVDS_OUTPUT_O_LOADEN PLLLVDSOUTPUT_X81_Y109_N2 1 Clock no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_pll0:pll0|pll_addr_cmd_clk PLLOUTPUTCOUNTER_X81_Y107_N1 40 Clock yes Global Clock GCLK13 --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_pll0:pll0|pll_avl_clk PLLOUTPUTCOUNTER_X81_Y108_N1 1088 Clock yes Global Clock GCLK12 --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_pll0:pll0|pll_config_clk PLLOUTPUTCOUNTER_X81_Y109_N1 275 Clock yes Global Clock GCLK14 --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_pll0:pll0|pll_locked FRACTIONALPLL_X81_Y112_N0 2 Async. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|RLDRAMII_s0_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always0~0 LABCELL_X18_Y128_N27 5 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|RLDRAMII_s0_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~0 MLABCELL_X25_Y128_N39 4 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|RLDRAMII_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent|m0_write LABCELL_X24_Y128_N42 33 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|RLDRAMII_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent|m0_read~0 LABCELL_X18_Y131_N15 34 Sync. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|RLDRAMII_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter|save_dest_id~0 LABCELL_X21_Y128_N12 5 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_avalon_mm_bridge:seq_bridge|cmd_waitrequest~1 LABCELL_X24_Y128_N39 59 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_avalon_mm_bridge:seq_bridge|use_reg FF_X24_Y126_N2 57 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_avalon_mm_bridge:seq_bridge|wait_rise LABCELL_X21_Y126_N42 55 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|D_iw[4] FF_X15_Y128_N47 52 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|E_alu_result~1 LABCELL_X11_Y129_N3 65 Sync. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|E_new_inst FF_X8_Y129_N23 48 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|E_src1[18]~0 MLABCELL_X3_Y132_N57 17 Sync. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|E_valid FF_X10_Y129_N32 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|Equal0~0 LABCELL_X13_Y128_N30 10 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|F_pc_sel_nxt.10~0 MLABCELL_X3_Y131_N15 13 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|F_valid~0 LABCELL_X13_Y130_N33 38 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|R_src2_hi~1 LABCELL_X1_Y128_N33 16 Sync. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|R_src2_lo~0 LABCELL_X1_Y128_N0 16 Sync. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|R_src2_use_imm FF_X10_Y128_N26 32 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|W_rf_wren LABCELL_X13_Y131_N57 2 Clock enable, Write enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|W_status_reg_pie_inst_nxt~1 LABCELL_X11_Y129_N24 17 Sync. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|W_valid FF_X10_Y129_N38 17 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|av_ld_aligning_data FF_X10_Y129_N20 27 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|av_ld_byte0_data[7]~0 LABCELL_X13_Y129_N9 9 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|av_ld_byte1_data_en~0 LABCELL_X13_Y129_N57 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst:cpu_inst|av_ld_rshift8~0 LABCELL_X13_Y129_N0 16 Clock enable, Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_mem_no_ifdef_params:sequencer_mem|wren~0 LABCELL_X18_Y128_N57 32 Write enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_rst:sequencer_rst|r_early_rst FF_X15_Y130_N7 32 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_rst:sequencer_rst|r_sync_rst FF_X15_Y130_N59 11 Sync. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|altera_mem_if_sequencer_rst:sequencer_rst|r_sync_rst FF_X15_Y130_N59 751 Async. clear yes Global Clock GCLK0 --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|avl_readdata_g_avl[5]~0 MLABCELL_X12_Y132_N48 26 Sync. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|afi_rdata_valid_r FF_X10_Y134_N14 40 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|cmd_clear_read_datapath LABCELL_X10_Y134_N57 24 Sync. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|next_PC~1 LABCELL_X10_Y134_N15 25 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_ac_ROM_no_ifdef_params:ac_ROM_i|altsyncram:altsyncram_component|altsyncram_q1u1:auto_generated|decode_7da:wr_decode|eq_node[0]~1 LABCELL_X10_Y134_N21 28 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_ac_ROM_no_ifdef_params:ac_ROM_i|altsyncram:altsyncram_component|altsyncram_q1u1:auto_generated|decode_7da:wr_decode|eq_node[1]~0 LABCELL_X10_Y134_N48 28 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_inst_ROM_no_ifdef_params:inst_ROM_i|altsyncram:altsyncram_component|altsyncram_p8s1:auto_generated|mux_49b:rd_mux|l2_w18_n0_mux_dataout~0 MLABCELL_X6_Y136_N3 10 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_jumplogic:jumplogic_i|always0~0 MLABCELL_X8_Y135_N57 16 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_jumplogic:jumplogic_i|always1~0 LABCELL_X7_Y135_N0 16 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_jumplogic:jumplogic_i|always2~0 LABCELL_X10_Y135_N21 16 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_jumplogic:jumplogic_i|always3~0 LABCELL_X7_Y133_N24 16 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_jumplogic:jumplogic_i|cntr[0][0]~1 MLABCELL_X8_Y135_N36 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_jumplogic:jumplogic_i|cntr[1][0]~10 LABCELL_X7_Y135_N33 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_jumplogic:jumplogic_i|cntr[2][0]~19 LABCELL_X7_Y135_N6 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_jumplogic:jumplogic_i|cntr[3][5]~28 LABCELL_X7_Y133_N21 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_jumplogic:jumplogic_i|jump_pointers[0][5]~0 LABCELL_X9_Y134_N42 7 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_jumplogic:jumplogic_i|jump_pointers[1][5]~1 LABCELL_X9_Y134_N0 7 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_jumplogic:jumplogic_i|jump_pointers[2][5]~2 LABCELL_X9_Y134_N3 7 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_jumplogic:jumplogic_i|jump_pointers[3][5]~3 LABCELL_X9_Y134_N54 7 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_read_datapath:read_datapath_i|dm_lfsr_step MLABCELL_X8_Y133_N54 11 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_read_datapath:read_datapath_i|do_lfsr_step LABCELL_X9_Y133_N51 37 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_read_datapath:read_datapath_i|pattern_radd[4]~1 LABCELL_X7_Y136_N0 6 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_read_datapath:read_datapath_i|pattern_wadd[0]~1 LABCELL_X9_Y136_N42 5 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_soft_reset_n LABCELL_X17_Y134_N12 274 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|write_DM_lfsr_step MLABCELL_X6_Y136_N9 11 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|write_DO_lfsr_step LABCELL_X11_Y136_N45 36 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|Selector10~0 LABCELL_X28_Y131_N54 4 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|Selector3~0 LABCELL_X28_Y131_N57 3 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|avl_readdata_r[0]~3 LABCELL_X24_Y131_N33 5 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_fail~0 LABCELL_X28_Y131_N39 4 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_mux_sel FF_X31_Y131_N14 200 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_read_increment_vfifo_fr_pre_combined[0]~0 LABCELL_X26_Y131_N39 5 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_read_latency_counter[4]~0 LABCELL_X26_Y131_N51 5 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|rfile[0][4]~3 LABCELL_X31_Y131_N21 5 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|rfile[3][1]~4 LABCELL_X31_Y131_N36 2 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|state_avl_curr.STATE_AVL_IDLE FF_X28_Y131_N32 14 Sync. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|Equal15~1 LABCELL_X40_Y132_N48 41 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|always5~0 LABCELL_X31_Y130_N27 9 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|always8~0 LABCELL_X39_Y129_N42 29 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|scc_dq_ena[1]~0 LABCELL_X41_Y133_N15 31 Sync. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|scc_dqs_cfg_curr[29]~0 LABCELL_X41_Y129_N36 26 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|scc_dqs_cfg_curr_p[0][19]~7 LABCELL_X40_Y129_N24 24 Sync. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|scc_dqs_cfg_curr_p~2 LABCELL_X39_Y129_N12 29 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|scc_io_cfg_curr[8]~0 MLABCELL_X44_Y129_N0 20 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|scc_state_curr.STATE_SCC_LOAD FF_X42_Y129_N17 30 Sync. clear, Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_msr1:auto_generated|decode_7ea:wr_decode|eq_node[0]~1 LABCELL_X31_Y130_N3 19 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_msr1:auto_generated|decode_7ea:wr_decode|eq_node[1]~0 LABCELL_X31_Y130_N42 19 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|alt_rld_controller_top_ctl_bl_is_one:c0|alt_rld_controller_ctl_bl_is_one:controller_inst|alt_rld_afi_ctl_bl_is_one:afi|memctl_burst_latency_shifter_ctl_bl_is_one:write_latency_shifter_inst|latency_shifter_gen_n.latency_shifter[3] FF_X31_Y132_N23 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|alt_rld_controller_top_ctl_bl_is_one:c0|alt_rld_controller_ctl_bl_is_one:controller_inst|alt_rld_fsm_ctl_bl_is_one:fsm|do_aref~0 LABCELL_X33_Y133_N21 5 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|alt_rld_controller_top_ctl_bl_is_one:c0|alt_rld_controller_ctl_bl_is_one:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|avl_ready~2 LABCELL_X32_Y131_N30 34 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|alt_rld_controller_top_ctl_bl_is_one:c0|alt_rld_controller_ctl_bl_is_one:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[14]~1 LABCELL_X32_Y131_N36 25 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|alt_rld_controller_top_ctl_bl_is_one:c0|alt_rld_controller_ctl_bl_is_one:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_read_req~0 LABCELL_X32_Y131_N0 2 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|alt_rld_controller_top_ctl_bl_is_one:c0|alt_rld_controller_ctl_bl_is_one:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|state.INIT FF_X29_Y131_N44 28 Sync. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|alt_rld_controller_top_ctl_bl_is_one:c0|alt_rld_controller_ctl_bl_is_one:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|state.NORMAL FF_X29_Y131_N35 33 Sync. load no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|alt_rld_controller_top_ctl_bl_is_one:c0|alt_rld_controller_ctl_bl_is_one:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[3] FF_X34_Y133_N47 57 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|alt_rld_controller_top_ctl_bl_is_one:c0|alt_rld_controller_ctl_bl_is_one:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[4] FF_X32_Y132_N14 57 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|alt_rld_controller_top_ctl_bl_is_one:c0|alt_rld_controller_ctl_bl_is_one:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[5] FF_X34_Y133_N5 15 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|alt_rld_controller_top_ctl_bl_is_one:c0|alt_rld_controller_ctl_bl_is_one:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[6] FF_X34_Y133_N44 25 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|alt_rld_controller_top_ctl_bl_is_one:c0|alt_rld_controller_ctl_bl_is_one:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[7] FF_X34_Y133_N56 12 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|alt_rld_controller_top_ctl_bl_is_one:c0|alt_rld_controller_ctl_bl_is_one:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[8] FF_X32_Y132_N43 4 Async. clear no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|alt_rld_controller_top_ctl_bl_is_one:c0|alt_rld_controller_ctl_bl_is_one:controller_inst|memctl_wdata_rdata_logic:memctl_wdata_rdata_logic_inst|memctl_beat_valid_fifo:memctl_wdata_valid_fifo_inst|beat_valid_out~0 LABCELL_X31_Y132_N33 8 Clock enable no -- -- --
DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|alt_rld_controller_top_ctl_bl_is_one:c0|alt_rld_controller_ctl_bl_is_one:controller_inst|memctl_wdata_rdata_logic:memctl_wdata_rdata_logic_inst|memctl_wdata_fifo:memctl_wdata_fifo_inst|write_req_reg FF_X29_Y131_N41 7 Clock enable, Write enable no -- -- --
DOVME:DOVME_inst|VMEBuffBlock:b2v_inst144|test_mode_n_reg FF_X25_Y101_N53 4 Clock enable no -- -- --
DOVME:DOVME_inst|counter22:b2v_inst2|lpm_counter:LPM_COUNTER_component|cntr_pfi:auto_generated|_~0 LABCELL_X34_Y131_N42 22 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|AMMAP_outssidL0[3] FF_X63_Y24_N26 32 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|AMMAP_outssidL1[3] FF_X36_Y24_N5 32 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|AMMAP_outssidL2[3] FF_X107_Y116_N38 32 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|Equal0~6 LABCELL_X50_Y115_N18 33 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|Equal1~6 LABCELL_X63_Y100_N57 33 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|Equal2~6 LABCELL_X32_Y100_N54 33 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|Equal3~6 LABCELL_X33_Y110_N39 33 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|Equal4~6 LABCELL_X126_Y110_N21 33 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|Equal5~6 LABCELL_X56_Y114_N0 33 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLADD11L_latchreq[0] FF_X60_Y117_N13 47 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLADD11L_latchreq[10] FF_X105_Y122_N26 29 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLADD11L_latchreq[1] FF_X77_Y13_N17 47 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLADD11L_latchreq[2] FF_X21_Y101_N35 47 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLADD11L_latchreq[3] FF_X39_Y117_N19 47 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLADD11L_latchreq[4] FF_X127_Y110_N13 47 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLADD11L_latchreq[5] FF_X63_Y114_N14 47 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLADD11L_latchreq[6] FF_X125_Y10_N50 29 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLADD11L_latchreq[7] FF_X154_Y108_N29 29 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLADD11L_latchreq[8] FF_X124_Y113_N17 29 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLADD11L_latchreq[9] FF_X49_Y12_N32 29 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLRDADD11L_latchreq[0] FF_X71_Y106_N32 31 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLRDADD11L_latchreq[10] FF_X71_Y106_N8 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLRDADD11L_latchreq[2] FF_X68_Y106_N59 31 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLRDADD11L_latchreq[4] FF_X98_Y112_N44 31 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLRDADD11L_latchreq[6] FF_X71_Y106_N50 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLRDADD11L_latchreq[7] FF_X71_Y106_N44 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLRDADD11L_latchreq[8] FF_X71_Y106_N47 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|MLRDADD11L_latchreq[9] FF_X71_Y106_N14 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_read[0] FF_X80_Y107_N53 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_read[10] FF_X93_Y111_N38 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_read[1] FF_X80_Y107_N29 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_read[2] FF_X77_Y106_N44 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_read[3] FF_X80_Y109_N5 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_read[4] FF_X95_Y109_N50 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_read[5] FF_X91_Y107_N7 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_read[6] FF_X94_Y107_N41 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_read[7] FF_X90_Y107_N50 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_read[8] FF_X94_Y109_N50 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_read[9] FF_X91_Y107_N23 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_write[0] FF_X79_Y117_N41 331 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_write[10] FF_X99_Y122_N14 313 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_write[1] FF_X77_Y103_N5 331 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_write[2] FF_X65_Y99_N41 331 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_write[3] FF_X17_Y110_N35 331 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_write[4] FF_X134_Y110_N38 331 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_write[5] FF_X71_Y114_N38 331 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_write[6] FF_X129_Y106_N14 314 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_write[7] FF_X151_Y106_N35 314 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_write[8] FF_X131_Y114_N23 314 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|fsm11L_write[9] FF_X79_Y14_N38 314 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[0][0] FF_X60_Y129_N25 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[0][1] FF_X50_Y125_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[0][2] FF_X50_Y124_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[0][3] FF_X50_Y129_N4 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[0][4] FF_X60_Y124_N25 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[0][5] FF_X60_Y125_N49 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[0][6] FF_X60_Y127_N28 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[0][7] FF_X69_Y127_N4 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[1][0] FF_X93_Y2_N28 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[1][1] FF_X93_Y2_N22 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[1][2] FF_X90_Y2_N52 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[1][3] FF_X92_Y3_N41 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[1][4] FF_X80_Y5_N49 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[1][5] FF_X97_Y6_N28 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[1][6] FF_X97_Y1_N49 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[1][7] FF_X94_Y3_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[2][0] FF_X23_Y25_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[2][1] FF_X24_Y22_N16 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[2][2] FF_X28_Y23_N50 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[2][3] FF_X16_Y22_N52 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[2][4] FF_X28_Y25_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[2][5] FF_X16_Y22_N7 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[2][6] FF_X26_Y24_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[2][7] FF_X18_Y25_N29 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[3][0] FF_X15_Y118_N52 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[3][1] FF_X15_Y118_N10 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[3][2] FF_X28_Y116_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[3][3] FF_X28_Y117_N17 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[3][4] FF_X15_Y118_N16 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[3][5] FF_X18_Y117_N2 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[3][6] FF_X28_Y120_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[3][7] FF_X20_Y120_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[4][0] FF_X151_Y124_N52 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[4][1] FF_X147_Y123_N49 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[4][2] FF_X142_Y122_N1 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[4][3] FF_X145_Y122_N49 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[4][4] FF_X144_Y123_N28 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[4][5] FF_X144_Y123_N43 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[4][6] FF_X142_Y124_N28 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[4][7] FF_X144_Y123_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[5][0] FF_X42_Y119_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[5][1] FF_X36_Y120_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[5][2] FF_X52_Y120_N40 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[5][3] FF_X42_Y120_N1 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[5][4] FF_X36_Y119_N52 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[5][5] FF_X34_Y118_N25 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[5][6] FF_X48_Y121_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmpix_wren[5][7] FF_X34_Y118_N31 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[0][0] FF_X142_Y12_N41 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[0][1] FF_X136_Y10_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[0][2] FF_X131_Y14_N28 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[0][3] FF_X131_Y11_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[0][4] FF_X131_Y12_N25 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[0][5] FF_X136_Y10_N8 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[0][6] FF_X136_Y10_N41 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[0][7] FF_X132_Y12_N52 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[1][0] FF_X163_Y109_N4 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[1][1] FF_X161_Y108_N38 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[1][2] FF_X161_Y110_N53 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[1][3] FF_X151_Y112_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[1][4] FF_X161_Y111_N38 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[1][5] FF_X161_Y112_N16 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[1][6] FF_X161_Y113_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[1][7] FF_X149_Y111_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[2][0] FF_X131_Y116_N25 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[2][1] FF_X142_Y114_N53 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[2][2] FF_X121_Y114_N25 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[2][3] FF_X131_Y116_N55 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[2][4] FF_X121_Y116_N4 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[2][5] FF_X131_Y114_N16 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[2][6] FF_X119_Y115_N25 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[2][7] FF_X142_Y112_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[3][0] FF_X52_Y10_N25 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[3][1] FF_X50_Y9_N28 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[3][2] FF_X50_Y8_N28 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[3][3] FF_X42_Y11_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[3][4] FF_X44_Y14_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[3][5] FF_X44_Y13_N49 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[3][6] FF_X44_Y13_N10 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[3][7] FF_X44_Y12_N4 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[4][0] FF_X108_Y129_N1 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[4][1] FF_X108_Y129_N44 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[4][2] FF_X100_Y131_N14 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[4][3] FF_X105_Y129_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[4][4] FF_X112_Y129_N4 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[4][5] FF_X108_Y130_N40 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[4][6] FF_X110_Y129_N41 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hcmsct_wren[4][7] FF_X110_Y132_N17 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcpix_rd_analyze[0] FF_X99_Y114_N14 109 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcpix_rd_analyze[1] FF_X66_Y86_N56 109 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcpix_rd_analyze[2] FF_X32_Y24_N26 109 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcpix_rd_analyze[3] FF_X21_Y113_N5 110 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcpix_rd_analyze[4] FF_X109_Y112_N2 109 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcpix_rd_analyze[5] FF_X93_Y112_N14 110 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|FIFOIndex_indata[1]~0 LABCELL_X71_Y122_N27 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|HCM_rdaddr[0][2]~0 LABCELL_X65_Y123_N18 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|HitCounter[4]~1 LABCELL_X80_Y122_N21 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|_~1 LABCELL_X79_Y121_N48 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X79_Y121_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X93_Y121_N12 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X93_Y121_N24 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X93_Y121_N54 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X93_Y121_N3 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X93_Y121_N30 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X93_Y121_N51 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X93_Y121_N18 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X93_Y121_N39 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X93_Y121_N42 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|_~1 LABCELL_X95_Y121_N39 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X95_Y121_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X95_Y121_N42 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X95_Y121_N21 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X95_Y121_N51 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X99_Y122_N45 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X99_Y122_N36 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X99_Y122_N33 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X99_Y122_N24 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X99_Y122_N9 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X99_Y122_N0 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|_~1 LABCELL_X74_Y121_N0 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|a_fefifo_t7f:fifo_state|cntr_2a7:count_usedw|_~0 LABCELL_X69_Y121_N18 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|cntr_m9b:wr_ptr|_~0 LABCELL_X80_Y127_N27 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode301w[2] LABCELL_X80_Y127_N24 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode314w[2] LABCELL_X80_Y127_N54 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode322w[2] LABCELL_X80_Y127_N36 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode330w[2] LABCELL_X80_Y127_N42 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|_~1 LABCELL_X80_Y121_N39 12 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|a_fefifo_b6f:fifo_state|cntr_1a7:count_usedw|_~0 LABCELL_X80_Y121_N54 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|cntr_l9b:wr_ptr|_~0 LABCELL_X80_Y121_N45 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|decode_up6:wr_decode|eq_node[0] LABCELL_X80_Y121_N27 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|decode_up6:wr_decode|eq_node[1] LABCELL_X80_Y121_N42 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|_~1 LABCELL_X65_Y121_N33 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|a_fefifo_56f:fifo_state|cntr_0a7:count_usedw|_~0 LABCELL_X66_Y121_N42 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|a_fefifo_56f:fifo_state|valid_wreq LABCELL_X65_Y121_N42 19 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|cntr_k9b:wr_ptr|_~0 LABCELL_X66_Y121_N51 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|_~1 LABCELL_X74_Y121_N51 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|a_fefifo_66f:fifo_state|cntr_v97:count_usedw|_~0 LABCELL_X72_Y121_N54 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|cntr_j9b:wr_ptr|_~0 LABCELL_X72_Y121_N24 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|valid_wreq LABCELL_X72_Y121_N45 18 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|_~1 LABCELL_X77_Y121_N24 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X77_Y121_N42 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X77_Y121_N21 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|valid_wreq LABCELL_X77_Y121_N18 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|_~1 LABCELL_X66_Y121_N45 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X66_Y121_N54 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|valid_wreq LABCELL_X66_Y121_N27 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X66_Y121_N24 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|_~1 LABCELL_X77_Y122_N24 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X77_Y122_N27 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X74_Y122_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X74_Y122_N33 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X74_Y122_N51 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X74_Y122_N30 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X74_Y122_N48 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X74_Y122_N39 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X74_Y122_N42 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X74_Y122_N24 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X74_Y122_N45 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|RD_EOR_sync0~3 LABCELL_X79_Y122_N57 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|SSIndex[3]~1 LABCELL_X71_Y122_N24 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:0:Top_HitListControlRDPIX|process_index~1 LABCELL_X79_Y122_N51 27 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|FIFOIndex_indata[3]~0 LABCELL_X66_Y9_N54 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|HCM_rdaddr[0][3]~0 LABCELL_X66_Y8_N48 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|HitCounter[0]~1 LABCELL_X57_Y4_N30 9 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|_~1 LABCELL_X71_Y9_N3 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X72_Y9_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X72_Y1_N15 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X72_Y1_N27 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X72_Y1_N54 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X72_Y1_N51 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X72_Y1_N30 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X72_Y1_N0 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X72_Y1_N45 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X72_Y1_N39 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X72_Y1_N18 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|_~1 LABCELL_X56_Y3_N54 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X56_Y3_N30 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X50_Y3_N27 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X50_Y3_N24 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X50_Y3_N21 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X50_Y3_N0 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X53_Y3_N48 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X50_Y3_N6 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X53_Y3_N42 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X50_Y3_N15 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X53_Y3_N36 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|_~1 LABCELL_X69_Y9_N57 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|a_fefifo_t7f:fifo_state|cntr_2a7:count_usedw|_~0 LABCELL_X69_Y9_N30 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|cntr_m9b:wr_ptr|_~0 LABCELL_X69_Y7_N18 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode301w[2] LABCELL_X72_Y8_N15 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode314w[2] LABCELL_X72_Y8_N54 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode322w[2] LABCELL_X72_Y8_N36 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode330w[2] LABCELL_X72_Y8_N21 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|_~1 LABCELL_X53_Y6_N24 12 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|a_fefifo_b6f:fifo_state|cntr_1a7:count_usedw|_~0 LABCELL_X53_Y6_N57 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|cntr_l9b:wr_ptr|_~0 LABCELL_X50_Y6_N24 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|decode_up6:wr_decode|eq_node[0] LABCELL_X50_Y6_N48 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|decode_up6:wr_decode|eq_node[1] LABCELL_X50_Y6_N54 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|_~1 MLABCELL_X60_Y9_N24 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|a_fefifo_56f:fifo_state|cntr_0a7:count_usedw|_~0 MLABCELL_X60_Y9_N36 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|cntr_k9b:wr_ptr|_~0 MLABCELL_X60_Y9_N57 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|valid_wreq MLABCELL_X60_Y9_N27 19 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|_~1 LABCELL_X61_Y8_N51 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|a_fefifo_66f:fifo_state|cntr_v97:count_usedw|_~0 LABCELL_X61_Y8_N24 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|cntr_j9b:wr_ptr|_~0 LABCELL_X61_Y8_N18 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|valid_wreq LABCELL_X61_Y8_N21 18 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|_~1 LABCELL_X56_Y8_N21 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X56_Y8_N24 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|valid_wreq LABCELL_X56_Y8_N57 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X56_Y8_N54 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|_~1 LABCELL_X63_Y9_N51 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X63_Y9_N9 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X63_Y9_N3 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|valid_wreq LABCELL_X63_Y9_N0 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|_~1 LABCELL_X66_Y10_N3 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X66_Y10_N18 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X71_Y10_N33 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X72_Y10_N51 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X72_Y10_N33 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X72_Y10_N36 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X72_Y10_N9 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X71_Y10_N3 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X71_Y10_N6 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X71_Y10_N24 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X72_Y10_N21 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|RD_EOR_sync0~3 LABCELL_X63_Y8_N54 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|SSIndex[3]~1 LABCELL_X61_Y9_N15 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:1:Top_HitListControlRDPIX|process_index~1 LABCELL_X63_Y8_N3 27 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|FIFOIndex_indata[1]~0 LABCELL_X21_Y10_N27 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|HCM_rdaddr[0][7]~0 LABCELL_X32_Y24_N57 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|HitCounter[3]~1 LABCELL_X18_Y13_N21 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|_~1 LABCELL_X17_Y10_N18 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X17_Y10_N36 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X17_Y10_N27 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X16_Y10_N21 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X16_Y10_N24 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X16_Y10_N30 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X16_Y10_N36 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X16_Y10_N57 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X16_Y10_N3 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X16_Y10_N6 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X16_Y10_N51 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|_~1 LABCELL_X18_Y9_N54 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X18_Y9_N24 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X18_Y9_N27 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X11_Y9_N30 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X11_Y9_N36 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X11_Y9_N54 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X11_Y9_N3 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X11_Y9_N9 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X11_Y9_N48 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X11_Y9_N42 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X17_Y9_N48 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|_~1 LABCELL_X31_Y14_N15 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|a_fefifo_t7f:fifo_state|cntr_2a7:count_usedw|_~0 LABCELL_X31_Y14_N54 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|cntr_m9b:wr_ptr|_~0 LABCELL_X31_Y14_N12 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode301w[2] LABCELL_X29_Y14_N36 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode314w[2] LABCELL_X29_Y14_N57 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode322w[2] LABCELL_X29_Y14_N12 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode330w[2] LABCELL_X29_Y14_N30 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|_~1 LABCELL_X11_Y11_N15 12 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|a_fefifo_b6f:fifo_state|cntr_1a7:count_usedw|_~0 LABCELL_X11_Y11_N30 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|cntr_l9b:wr_ptr|_~0 LABCELL_X10_Y13_N51 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|decode_up6:wr_decode|eq_node[0] LABCELL_X10_Y13_N24 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|decode_up6:wr_decode|eq_node[1] LABCELL_X10_Y13_N21 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|_~1 LABCELL_X28_Y15_N6 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|a_fefifo_56f:fifo_state|cntr_0a7:count_usedw|_~0 LABCELL_X28_Y15_N48 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|cntr_k9b:wr_ptr|_~0 LABCELL_X28_Y15_N24 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|valid_wreq LABCELL_X28_Y15_N9 19 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|_~1 LABCELL_X13_Y15_N15 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|a_fefifo_66f:fifo_state|cntr_v97:count_usedw|_~0 LABCELL_X13_Y15_N54 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|a_fefifo_66f:fifo_state|valid_wreq LABCELL_X13_Y15_N21 18 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|cntr_j9b:wr_ptr|_~0 LABCELL_X13_Y15_N12 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|_~1 LABCELL_X21_Y14_N51 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 MLABCELL_X20_Y14_N9 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|valid_wreq MLABCELL_X20_Y14_N48 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|cntr_i9b:wr_ptr|_~0 MLABCELL_X20_Y14_N21 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|_~1 LABCELL_X26_Y14_N57 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X26_Y14_N24 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|valid_wreq LABCELL_X26_Y14_N21 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X26_Y14_N18 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|_~1 LABCELL_X11_Y7_N54 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X11_Y7_N3 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X16_Y6_N12 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X16_Y6_N36 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X16_Y6_N9 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X13_Y6_N0 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X13_Y6_N18 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X16_Y6_N27 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X16_Y6_N21 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X16_Y6_N0 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X16_Y6_N33 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|RD_EOR_sync0~3 LABCELL_X32_Y13_N27 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|SSIndex[0]~1 LABCELL_X17_Y7_N33 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:2:Top_HitListControlRDPIX|process_index~1 LABCELL_X18_Y13_N54 27 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|FIFOIndex_indata[0]~0 LABCELL_X16_Y111_N0 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|HCM_rdaddr[0][7]~0 LABCELL_X17_Y113_N33 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|HitCounter[0]~1 LABCELL_X13_Y112_N54 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|_~1 LABCELL_X7_Y110_N15 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X9_Y110_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X2_Y115_N57 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X2_Y115_N36 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X2_Y115_N12 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X2_Y115_N21 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X2_Y115_N0 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X2_Y115_N54 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X2_Y115_N27 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X2_Y115_N9 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X2_Y115_N6 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|_~1 LABCELL_X10_Y110_N0 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X10_Y110_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X4_Y109_N51 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X4_Y111_N15 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X4_Y109_N48 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X4_Y109_N54 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X4_Y111_N30 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X9_Y113_N3 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X9_Y113_N30 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X4_Y111_N36 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X9_Y113_N12 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|_~1 LABCELL_X11_Y110_N39 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|a_fefifo_t7f:fifo_state|cntr_2a7:count_usedw|_~0 LABCELL_X11_Y110_N24 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|cntr_m9b:wr_ptr|_~0 LABCELL_X11_Y110_N27 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode301w[2] LABCELL_X16_Y114_N0 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode314w[2] LABCELL_X16_Y114_N9 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode322w[2] LABCELL_X16_Y114_N27 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode330w[2] LABCELL_X16_Y114_N24 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|_~1 LABCELL_X11_Y111_N51 12 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|a_fefifo_b6f:fifo_state|cntr_1a7:count_usedw|_~0 LABCELL_X11_Y111_N18 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|cntr_l9b:wr_ptr|_~0 LABCELL_X11_Y111_N39 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|decode_up6:wr_decode|eq_node[0] LABCELL_X11_Y111_N45 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|decode_up6:wr_decode|eq_node[1] LABCELL_X11_Y111_N36 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|_~1 LABCELL_X17_Y110_N54 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|a_fefifo_56f:fifo_state|cntr_0a7:count_usedw|_~0 LABCELL_X17_Y110_N30 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|a_fefifo_56f:fifo_state|valid_wreq LABCELL_X17_Y110_N18 19 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|cntr_k9b:wr_ptr|_~0 LABCELL_X17_Y110_N27 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|_~1 LABCELL_X16_Y110_N45 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|a_fefifo_66f:fifo_state|cntr_v97:count_usedw|_~0 LABCELL_X16_Y110_N48 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|a_fefifo_66f:fifo_state|valid_wreq LABCELL_X16_Y110_N21 18 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|cntr_j9b:wr_ptr|_~0 LABCELL_X16_Y110_N12 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|_~1 LABCELL_X21_Y112_N54 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X21_Y112_N51 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|valid_wreq LABCELL_X21_Y112_N42 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X21_Y112_N45 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|_~1 LABCELL_X21_Y110_N21 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X21_Y110_N48 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X21_Y110_N54 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|valid_wreq LABCELL_X21_Y110_N57 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|_~1 LABCELL_X10_Y111_N30 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X10_Y111_N39 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X9_Y111_N3 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X9_Y111_N57 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X9_Y111_N27 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X9_Y111_N21 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X9_Y111_N24 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X9_Y111_N18 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X9_Y111_N15 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X9_Y111_N9 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X9_Y111_N12 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|RD_EOR_sync0~3 LABCELL_X13_Y111_N27 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|SSIndex[2]~1 LABCELL_X13_Y110_N30 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:3:Top_HitListControlRDPIX|process_index~1 LABCELL_X13_Y112_N33 27 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|FIFOIndex_indata[1]~0 LABCELL_X175_Y117_N57 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|HCM_rdaddr[0][3]~0 MLABCELL_X176_Y116_N3 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|HitCounter[4]~1 LABCELL_X180_Y114_N6 9 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|_~1 LABCELL_X173_Y112_N3 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X173_Y112_N21 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X163_Y110_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X164_Y112_N39 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X163_Y111_N39 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X163_Y111_N33 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X163_Y111_N24 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] MLABCELL_X167_Y112_N24 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X166_Y111_N33 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X164_Y112_N18 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X163_Y110_N39 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|_~1 LABCELL_X182_Y116_N12 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X182_Y116_N24 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X181_Y113_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X181_Y113_N39 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X181_Y113_N30 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X181_Y113_N51 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X181_Y113_N48 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X181_Y113_N21 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X181_Y113_N18 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X181_Y113_N27 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X181_Y113_N24 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|_~1 LABCELL_X182_Y115_N30 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|a_fefifo_t7f:fifo_state|cntr_2a7:count_usedw|_~0 LABCELL_X182_Y115_N36 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|cntr_m9b:wr_ptr|_~0 LABCELL_X182_Y114_N21 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode301w[2] LABCELL_X173_Y115_N12 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode314w[2] LABCELL_X182_Y114_N0 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode322w[2] LABCELL_X173_Y115_N9 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode330w[2] LABCELL_X173_Y115_N36 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|_~1 LABCELL_X182_Y117_N21 12 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|a_fefifo_b6f:fifo_state|cntr_1a7:count_usedw|_~0 LABCELL_X181_Y117_N57 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|cntr_l9b:wr_ptr|_~0 LABCELL_X180_Y117_N54 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|decode_up6:wr_decode|eq_node[0] LABCELL_X180_Y117_N30 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|decode_up6:wr_decode|eq_node[1] LABCELL_X180_Y117_N27 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|_~1 LABCELL_X171_Y114_N21 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|a_fefifo_56f:fifo_state|cntr_0a7:count_usedw|_~0 LABCELL_X171_Y114_N24 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|a_fefifo_56f:fifo_state|valid_wreq LABCELL_X171_Y114_N9 19 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|cntr_k9b:wr_ptr|_~0 LABCELL_X171_Y114_N12 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|_~1 LABCELL_X175_Y116_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|a_fefifo_66f:fifo_state|cntr_v97:count_usedw|_~0 LABCELL_X175_Y116_N45 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|a_fefifo_66f:fifo_state|valid_wreq LABCELL_X175_Y116_N42 18 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|cntr_j9b:wr_ptr|_~0 LABCELL_X175_Y116_N57 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|_~1 MLABCELL_X170_Y116_N51 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 MLABCELL_X170_Y116_N24 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|cntr_i9b:wr_ptr|_~0 MLABCELL_X170_Y116_N48 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|valid_wreq MLABCELL_X170_Y116_N57 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|_~1 LABCELL_X177_Y118_N24 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X177_Y118_N54 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|valid_wreq LABCELL_X177_Y118_N21 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X177_Y118_N18 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|_~1 LABCELL_X181_Y120_N12 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X180_Y120_N45 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X177_Y120_N21 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X177_Y120_N9 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X177_Y120_N27 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X177_Y120_N6 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X177_Y120_N24 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X177_Y120_N15 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X177_Y120_N57 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X177_Y120_N0 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X177_Y120_N54 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|RD_EOR_sync0~3 MLABCELL_X179_Y116_N51 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|SSIndex[1]~1 LABCELL_X181_Y116_N36 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:4:Top_HitListControlRDPIX|process_index~1 LABCELL_X180_Y114_N39 27 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|FIFOIndex_indata[0]~0 LABCELL_X91_Y120_N30 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|HCM_rdaddr[0][2]~0 LABCELL_X80_Y120_N45 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|HitCounter[1]~1 LABCELL_X99_Y115_N0 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|_~1 LABCELL_X80_Y119_N9 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X80_Y119_N3 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X80_Y117_N27 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X79_Y117_N57 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X79_Y117_N0 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X79_Y117_N6 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X80_Y117_N51 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X80_Y117_N48 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X80_Y117_N45 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X80_Y117_N36 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X80_Y117_N54 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|_~1 LABCELL_X95_Y113_N54 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X95_Y113_N24 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X95_Y113_N27 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X94_Y113_N15 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X94_Y113_N42 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X94_Y113_N27 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X94_Y113_N30 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X94_Y113_N39 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X94_Y113_N54 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X94_Y113_N51 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_crh1:auto_generated|a_dpfifo_gce1:dpfifo|dpram_0nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X94_Y113_N18 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|_~1 LABCELL_X93_Y119_N57 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|a_fefifo_t7f:fifo_state|cntr_2a7:count_usedw|_~0 LABCELL_X93_Y119_N36 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|cntr_m9b:wr_ptr|_~0 LABCELL_X94_Y119_N54 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode301w[2] LABCELL_X93_Y119_N54 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode314w[2] LABCELL_X94_Y119_N57 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode322w[2] LABCELL_X93_Y119_N24 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_8rh1:auto_generated|a_dpfifo_dce1:dpfifo|dpram_vmb1:FIFOram|decode_1q6:wr_decode|w_anode330w[2] LABCELL_X93_Y119_N51 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|_~1 LABCELL_X95_Y118_N39 12 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|a_fefifo_b6f:fifo_state|cntr_1a7:count_usedw|_~0 LABCELL_X95_Y118_N54 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|cntr_l9b:wr_ptr|_~0 LABCELL_X95_Y118_N27 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|decode_up6:wr_decode|eq_node[0] LABCELL_X95_Y118_N24 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_aoh1:auto_generated|a_dpfifo_rae1:dpfifo|dpram_umb1:FIFOram|decode_up6:wr_decode|eq_node[1] LABCELL_X95_Y118_N30 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|_~1 LABCELL_X79_Y116_N51 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|a_fefifo_56f:fifo_state|cntr_0a7:count_usedw|_~0 LABCELL_X79_Y116_N18 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|cntr_k9b:wr_ptr|_~0 LABCELL_X79_Y116_N21 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_1oh1:auto_generated|a_dpfifo_lae1:dpfifo|valid_wreq LABCELL_X79_Y116_N24 19 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|_~1 LABCELL_X69_Y115_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|a_fefifo_66f:fifo_state|cntr_v97:count_usedw|_~0 LABCELL_X69_Y115_N57 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|cntr_j9b:wr_ptr|_~0 LABCELL_X69_Y115_N15 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_2oh1:auto_generated|a_dpfifo_mae1:dpfifo|valid_wreq LABCELL_X69_Y115_N18 18 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|_~1 LABCELL_X80_Y118_N21 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X80_Y118_N54 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X80_Y118_N39 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|valid_wreq LABCELL_X80_Y118_N27 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|_~1 LABCELL_X95_Y119_N45 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X95_Y119_N54 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|a_fefifo_m4f:fifo_state|valid_wreq LABCELL_X95_Y119_N3 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_5lh1:auto_generated|a_dpfifo_69e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X80_Y119_N27 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|_~1 LABCELL_X99_Y120_N48 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X99_Y120_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X103_Y120_N24 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X103_Y120_N3 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X103_Y120_N9 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X103_Y120_N0 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X103_Y120_N6 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X103_Y120_N18 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X103_Y120_N57 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X103_Y120_N15 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|PIXIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X103_Y120_N54 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|RD_EOR_sync0~3 LABCELL_X99_Y115_N3 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|SSIndex[0]~1 LABCELL_X98_Y118_N45 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadpix:\HitListCtrlRDPIX:5:Top_HitListControlRDPIX|process_index~1 LABCELL_X95_Y115_N54 27 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|FIFOIndex_indata[3]~0 LABCELL_X163_Y4_N0 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|FIFOSS_indata[1][2]~51 LABCELL_X158_Y6_N30 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|FIFOSS_indata[2][2]~61 LABCELL_X161_Y7_N30 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|FIFOSS_indata[3][2]~29 LABCELL_X161_Y7_N12 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|FIFOSS_indata[3][7]~27 LABCELL_X161_Y7_N18 13 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|FIFOSS_indata[4][2]~7 LABCELL_X155_Y7_N39 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|FIFOSS_indata[4][3]~6 LABCELL_X155_Y7_N30 13 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|FIFOSS_indata[5][2]~17 LABCELL_X155_Y7_N21 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|FIFOSS_indata[5][9]~16 LABCELL_X156_Y8_N36 13 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|FIFOSS_indata[6][2]~11 LABCELL_X156_Y6_N33 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|FIFOSS_indata[6][3]~8 LABCELL_X159_Y6_N36 28 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|FIFOSS_indata[7][2]~21 LABCELL_X158_Y6_N6 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|FIFOSS_indata[7][4]~18 LABCELL_X159_Y6_N24 28 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|HCM_rdaddr[0][7]~0 LABCELL_X132_Y24_N48 11 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|HitCounter[2]~1 LABCELL_X168_Y9_N21 9 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|RD_EOR_sync0~2 LABCELL_X150_Y104_N15 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|_~1 LABCELL_X166_Y8_N18 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X163_Y8_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X168_Y10_N18 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X168_Y10_N51 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X168_Y10_N6 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X168_Y10_N3 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X168_Y10_N42 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X168_Y10_N27 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X168_Y10_N30 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X168_Y10_N39 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X168_Y10_N36 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|_~1 LABCELL_X172_Y8_N27 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X172_Y7_N18 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X175_Y7_N24 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X175_Y7_N51 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X175_Y7_N9 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X175_Y7_N0 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X175_Y7_N21 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X175_Y7_N36 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X175_Y7_N54 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X175_Y7_N15 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X175_Y7_N33 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|_~1 LABCELL_X163_Y5_N36 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|a_fefifo_t7f:fifo_state|cntr_2a7:count_usedw|_~0 LABCELL_X163_Y5_N51 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|cntr_m9b:wr_ptr|_~0 LABCELL_X173_Y5_N21 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode301w[2] LABCELL_X172_Y5_N3 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode314w[2] LABCELL_X173_Y5_N54 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode322w[2] LABCELL_X173_Y5_N36 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode330w[2] LABCELL_X172_Y5_N30 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|_~1 LABCELL_X180_Y7_N45 12 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|a_fefifo_b6f:fifo_state|cntr_1a7:count_usedw|_~0 LABCELL_X180_Y7_N51 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|cntr_l9b:wr_ptr|_~0 LABCELL_X180_Y7_N30 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|dpram_3nb1:FIFOram|decode_up6:wr_decode|eq_node[0] LABCELL_X180_Y7_N6 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|dpram_3nb1:FIFOram|decode_up6:wr_decode|eq_node[1] LABCELL_X180_Y7_N39 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|_~1 LABCELL_X164_Y4_N27 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|a_fefifo_56f:fifo_state|cntr_0a7:count_usedw|_~0 LABCELL_X155_Y4_N48 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|cntr_k9b:wr_ptr|_~0 LABCELL_X155_Y4_N54 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|valid_wreq LABCELL_X156_Y4_N15 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|_~1 LABCELL_X164_Y8_N48 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|a_fefifo_66f:fifo_state|cntr_v97:count_usedw|_~0 LABCELL_X161_Y8_N54 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|cntr_j9b:wr_ptr|_~0 LABCELL_X164_Y8_N33 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|valid_wreq LABCELL_X164_Y8_N12 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|_~1 LABCELL_X161_Y4_N45 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X161_Y4_N54 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|a_fefifo_m4f:fifo_state|valid_wreq LABCELL_X161_Y4_N48 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X161_Y4_N51 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|_~1 LABCELL_X166_Y6_N57 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X166_Y6_N24 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X166_Y6_N15 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|valid_wreq LABCELL_X166_Y6_N33 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|_~1 LABCELL_X168_Y8_N54 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X168_Y8_N33 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X171_Y4_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X171_Y4_N45 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X171_Y4_N51 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X171_Y4_N42 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X171_Y4_N48 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X171_Y4_N39 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X171_Y4_N30 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X171_Y4_N24 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X171_Y4_N33 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|SSIndex[1]~1 LABCELL_X168_Y6_N21 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:0:Top_HitListControlRDSCT|process_index~1 MLABCELL_X167_Y8_N3 29 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|FIFOIndex_indata[1]~0 LABCELL_X175_Y107_N45 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|FIFOSS_indata[1][2]~50 LABCELL_X163_Y105_N42 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|FIFOSS_indata[2][2]~60 MLABCELL_X170_Y106_N48 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|FIFOSS_indata[3][2]~28 MLABCELL_X174_Y105_N51 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|FIFOSS_indata[3][4]~26 MLABCELL_X174_Y105_N33 13 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|FIFOSS_indata[4][10]~6 MLABCELL_X174_Y106_N12 13 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|FIFOSS_indata[4][2]~7 LABCELL_X173_Y106_N12 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|FIFOSS_indata[5][2]~17 LABCELL_X172_Y108_N0 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|FIFOSS_indata[5][6]~16 LABCELL_X172_Y108_N21 13 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|FIFOSS_indata[6][1]~8 LABCELL_X175_Y106_N51 28 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|FIFOSS_indata[6][2]~11 LABCELL_X175_Y106_N18 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|FIFOSS_indata[7][12]~18 LABCELL_X175_Y106_N54 28 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|FIFOSS_indata[7][2]~21 LABCELL_X173_Y106_N33 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|HCM_rdaddr[0][4]~0 LABCELL_X144_Y104_N18 11 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|HitCounter[1]~1 LABCELL_X182_Y104_N57 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|RD_EOR_sync0~2 LABCELL_X181_Y107_N57 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|_~1 LABCELL_X182_Y103_N48 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X182_Y103_N6 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X181_Y102_N21 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X180_Y102_N12 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X180_Y102_N9 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] MLABCELL_X179_Y102_N0 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] MLABCELL_X179_Y102_N42 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X182_Y103_N33 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X180_Y103_N33 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X180_Y103_N15 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] MLABCELL_X179_Y102_N39 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|_~1 LABCELL_X168_Y102_N48 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X168_Y102_N0 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X171_Y101_N33 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X163_Y101_N24 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X163_Y101_N42 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X171_Y101_N3 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X171_Y101_N0 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X163_Y101_N36 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X171_Y101_N18 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X171_Y101_N27 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X163_Y101_N54 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|_~1 LABCELL_X182_Y108_N6 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|a_fefifo_t7f:fifo_state|cntr_2a7:count_usedw|_~0 LABCELL_X182_Y108_N54 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|cntr_m9b:wr_ptr|_~0 LABCELL_X181_Y108_N6 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode301w[2] LABCELL_X177_Y108_N39 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode314w[2] LABCELL_X182_Y108_N21 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode322w[2] LABCELL_X177_Y108_N30 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode330w[2] LABCELL_X177_Y108_N24 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|_~1 LABCELL_X175_Y105_N48 12 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|a_fefifo_b6f:fifo_state|cntr_1a7:count_usedw|_~0 LABCELL_X175_Y105_N24 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|cntr_l9b:wr_ptr|_~0 LABCELL_X181_Y105_N18 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|dpram_3nb1:FIFOram|decode_up6:wr_decode|eq_node[0] LABCELL_X181_Y105_N54 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|dpram_3nb1:FIFOram|decode_up6:wr_decode|eq_node[1] LABCELL_X181_Y105_N27 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|_~1 LABCELL_X180_Y106_N54 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|a_fefifo_56f:fifo_state|cntr_0a7:count_usedw|_~0 LABCELL_X177_Y106_N24 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|cntr_k9b:wr_ptr|_~0 LABCELL_X177_Y106_N42 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|valid_wreq LABCELL_X177_Y106_N39 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|_~1 LABCELL_X166_Y104_N42 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|a_fefifo_66f:fifo_state|cntr_v97:count_usedw|_~0 LABCELL_X166_Y104_N45 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|a_fefifo_66f:fifo_state|valid_wreq LABCELL_X166_Y104_N18 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|cntr_j9b:wr_ptr|_~0 LABCELL_X166_Y104_N27 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|_~1 MLABCELL_X176_Y106_N21 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 MLABCELL_X176_Y106_N48 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|cntr_i9b:wr_ptr|_~0 MLABCELL_X176_Y106_N15 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|valid_wreq MLABCELL_X176_Y106_N42 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|_~1 LABCELL_X173_Y107_N21 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X173_Y107_N30 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|a_fefifo_m4f:fifo_state|valid_wreq LABCELL_X173_Y107_N57 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X173_Y107_N18 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|_~1 LABCELL_X180_Y107_N36 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X180_Y107_N51 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X180_Y110_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X180_Y110_N33 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X180_Y110_N27 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X180_Y110_N30 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X180_Y110_N24 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X180_Y110_N39 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X180_Y110_N42 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X180_Y110_N48 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X180_Y110_N45 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|SSIndex[0]~1 LABCELL_X181_Y107_N39 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:1:Top_HitListControlRDSCT|process_index~1 LABCELL_X182_Y107_N6 29 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|FIFOIndex_indata[2]~0 LABCELL_X163_Y124_N21 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|FIFOSS_indata[1][2]~50 LABCELL_X156_Y123_N54 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|FIFOSS_indata[2][2]~60 LABCELL_X159_Y122_N18 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|FIFOSS_indata[3][10]~26 LABCELL_X159_Y121_N0 13 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|FIFOSS_indata[3][2]~28 LABCELL_X158_Y122_N0 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|FIFOSS_indata[4][2]~7 MLABCELL_X154_Y120_N18 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|FIFOSS_indata[4][8]~6 MLABCELL_X154_Y120_N27 13 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|FIFOSS_indata[5][0]~16 LABCELL_X158_Y122_N45 13 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|FIFOSS_indata[5][2]~17 LABCELL_X158_Y122_N3 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|FIFOSS_indata[6][2]~11 MLABCELL_X154_Y119_N45 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|FIFOSS_indata[6][2]~8 LABCELL_X157_Y123_N6 28 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|FIFOSS_indata[7][2]~21 LABCELL_X159_Y119_N42 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|FIFOSS_indata[7][4]~18 LABCELL_X158_Y123_N33 28 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|HCM_rdaddr[0][1]~0 LABCELL_X145_Y116_N57 11 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|HitCounter[3]~1 LABCELL_X171_Y120_N33 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|RD_EOR_sync0~2 LABCELL_X161_Y120_N54 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|_~1 LABCELL_X168_Y123_N30 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X168_Y123_N24 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X177_Y121_N21 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X177_Y121_N27 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X177_Y121_N54 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X177_Y121_N3 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X177_Y121_N0 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X177_Y121_N18 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X177_Y121_N15 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X177_Y121_N9 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X177_Y121_N6 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|_~1 LABCELL_X173_Y123_N12 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X173_Y123_N48 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X180_Y122_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X177_Y122_N3 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X177_Y122_N30 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X180_Y122_N24 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X177_Y122_N39 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X177_Y122_N54 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X180_Y122_N30 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X177_Y122_N15 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X177_Y122_N18 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|_~1 MLABCELL_X167_Y120_N39 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|a_fefifo_t7f:fifo_state|cntr_2a7:count_usedw|_~0 MLABCELL_X167_Y120_N36 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|cntr_m9b:wr_ptr|_~0 LABCELL_X168_Y120_N57 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode301w[2] LABCELL_X168_Y120_N36 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode314w[2] LABCELL_X168_Y120_N42 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode322w[2] LABCELL_X168_Y120_N51 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode330w[2] LABCELL_X168_Y120_N54 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|_~1 LABCELL_X164_Y123_N6 12 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|a_fefifo_b6f:fifo_state|cntr_1a7:count_usedw|_~0 LABCELL_X164_Y123_N0 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|cntr_l9b:wr_ptr|_~0 LABCELL_X164_Y123_N54 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|dpram_3nb1:FIFOram|decode_up6:wr_decode|eq_node[0] LABCELL_X164_Y123_N3 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|dpram_3nb1:FIFOram|decode_up6:wr_decode|eq_node[1] LABCELL_X164_Y123_N57 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|_~1 LABCELL_X163_Y123_N3 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|a_fefifo_56f:fifo_state|cntr_0a7:count_usedw|_~0 LABCELL_X163_Y123_N54 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|a_fefifo_56f:fifo_state|valid_wreq LABCELL_X163_Y123_N21 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|cntr_k9b:wr_ptr|_~0 LABCELL_X155_Y123_N57 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|_~1 LABCELL_X168_Y120_N39 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|a_fefifo_66f:fifo_state|cntr_v97:count_usedw|_~0 LABCELL_X166_Y120_N27 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|a_fefifo_66f:fifo_state|valid_wreq LABCELL_X166_Y120_N33 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|cntr_j9b:wr_ptr|_~0 LABCELL_X166_Y120_N12 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|_~1 LABCELL_X156_Y119_N12 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X156_Y119_N54 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X156_Y119_N24 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|valid_wreq LABCELL_X156_Y119_N45 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|_~1 LABCELL_X161_Y123_N57 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X161_Y123_N48 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X161_Y123_N24 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|valid_wreq LABCELL_X161_Y123_N21 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|_~1 LABCELL_X177_Y124_N45 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X177_Y124_N33 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X175_Y124_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X175_Y124_N45 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X175_Y124_N51 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X175_Y124_N42 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X175_Y124_N48 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X175_Y124_N27 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X175_Y124_N30 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X175_Y124_N36 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X175_Y124_N33 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|SSIndex[0]~1 LABCELL_X172_Y120_N36 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:2:Top_HitListControlRDSCT|process_index~1 LABCELL_X168_Y120_N48 29 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|FIFOIndex_indata[3]~0 LABCELL_X94_Y7_N6 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|FIFOSS_indata[1][2]~50 MLABCELL_X92_Y11_N42 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|FIFOSS_indata[2][2]~60 MLABCELL_X90_Y12_N18 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|FIFOSS_indata[3][2]~28 LABCELL_X93_Y12_N39 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|FIFOSS_indata[3][3]~26 LABCELL_X93_Y12_N30 13 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|FIFOSS_indata[4][0]~6 MLABCELL_X97_Y11_N0 13 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|FIFOSS_indata[4][2]~7 MLABCELL_X97_Y11_N21 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|FIFOSS_indata[5][2]~17 MLABCELL_X92_Y11_N21 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|FIFOSS_indata[5][9]~16 MLABCELL_X97_Y11_N36 13 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|FIFOSS_indata[6][10]~8 LABCELL_X94_Y12_N0 28 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|FIFOSS_indata[6][2]~11 LABCELL_X95_Y12_N36 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|FIFOSS_indata[7][10]~18 LABCELL_X93_Y9_N39 28 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|FIFOSS_indata[7][2]~21 LABCELL_X93_Y12_N12 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|HCM_rdaddr[0][8]~0 LABCELL_X95_Y14_N42 11 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|HitCounter[3]~1 LABCELL_X100_Y10_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|RD_EOR_sync0~2 LABCELL_X100_Y14_N18 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|_~1 LABCELL_X109_Y9_N3 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X109_Y9_N33 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X109_Y9_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X106_Y9_N15 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X106_Y9_N18 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X108_Y9_N48 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X108_Y9_N18 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X108_Y9_N39 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X108_Y9_N54 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X106_Y9_N36 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X108_Y9_N3 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|_~1 LABCELL_X99_Y8_N12 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X98_Y9_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X118_Y9_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X119_Y9_N15 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X119_Y9_N21 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X118_Y9_N24 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X119_Y9_N36 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X118_Y9_N18 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X119_Y9_N45 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X119_Y9_N3 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X118_Y9_N12 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|_~1 LABCELL_X99_Y8_N0 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|a_fefifo_t7f:fifo_state|cntr_2a7:count_usedw|_~0 LABCELL_X99_Y9_N6 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|cntr_m9b:wr_ptr|_~0 LABCELL_X99_Y9_N15 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode301w[2] MLABCELL_X97_Y9_N39 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode314w[2] MLABCELL_X97_Y9_N51 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode322w[2] MLABCELL_X97_Y9_N48 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode330w[2] MLABCELL_X97_Y9_N6 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|_~1 LABCELL_X100_Y12_N54 12 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|a_fefifo_b6f:fifo_state|cntr_1a7:count_usedw|_~0 MLABCELL_X105_Y12_N27 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|cntr_l9b:wr_ptr|_~0 MLABCELL_X105_Y12_N51 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|dpram_3nb1:FIFOram|decode_up6:wr_decode|eq_node[0] MLABCELL_X105_Y12_N57 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|dpram_3nb1:FIFOram|decode_up6:wr_decode|eq_node[1] LABCELL_X100_Y12_N42 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|_~1 LABCELL_X106_Y11_N24 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|a_fefifo_56f:fifo_state|cntr_0a7:count_usedw|_~0 LABCELL_X99_Y9_N36 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|cntr_k9b:wr_ptr|_~0 LABCELL_X100_Y9_N24 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|valid_wreq LABCELL_X100_Y9_N57 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|_~1 LABCELL_X107_Y11_N54 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|a_fefifo_66f:fifo_state|cntr_v97:count_usedw|_~0 LABCELL_X107_Y11_N57 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|a_fefifo_66f:fifo_state|valid_wreq LABCELL_X107_Y11_N42 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|cntr_j9b:wr_ptr|_~0 LABCELL_X107_Y11_N15 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|_~1 LABCELL_X98_Y14_N51 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X98_Y14_N12 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|a_fefifo_m4f:fifo_state|valid_wreq LABCELL_X98_Y14_N15 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X98_Y14_N54 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|_~1 LABCELL_X99_Y13_N21 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X99_Y13_N24 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X99_Y13_N36 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|valid_wreq LABCELL_X99_Y13_N57 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|_~1 LABCELL_X98_Y7_N9 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X98_Y7_N27 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X93_Y7_N27 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X93_Y7_N3 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X93_Y7_N9 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X93_Y7_N0 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X93_Y7_N6 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X93_Y7_N15 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X93_Y7_N57 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X93_Y7_N24 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X93_Y7_N18 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|SSIndex[2]~1 LABCELL_X100_Y7_N30 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:3:Top_HitListControlRDSCT|process_index~1 LABCELL_X98_Y10_N39 29 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|FIFOIndex_indata[2]~0 LABCELL_X77_Y130_N27 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|FIFOSS_indata[1][2]~50 LABCELL_X99_Y130_N12 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|FIFOSS_indata[2][2]~60 LABCELL_X99_Y130_N21 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|FIFOSS_indata[3][10]~26 LABCELL_X100_Y128_N30 13 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|FIFOSS_indata[3][2]~28 LABCELL_X100_Y128_N0 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|FIFOSS_indata[4][2]~6 LABCELL_X94_Y129_N36 13 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|FIFOSS_indata[4][2]~7 LABCELL_X94_Y129_N54 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|FIFOSS_indata[5][2]~17 LABCELL_X91_Y130_N24 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|FIFOSS_indata[5][9]~16 LABCELL_X91_Y129_N6 13 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|FIFOSS_indata[6][2]~11 MLABCELL_X92_Y129_N42 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|FIFOSS_indata[6][8]~8 LABCELL_X93_Y130_N45 28 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|FIFOSS_indata[7][10]~18 LABCELL_X93_Y130_N42 28 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|FIFOSS_indata[7][2]~21 LABCELL_X91_Y128_N18 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|HCM_rdaddr[0][5]~0 LABCELL_X94_Y120_N3 11 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|HitCounter[2]~1 LABCELL_X95_Y131_N33 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|RD_EOR_sync0~2 LABCELL_X94_Y127_N54 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|_~1 LABCELL_X80_Y133_N54 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X80_Y133_N36 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X80_Y133_N57 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X93_Y133_N3 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X93_Y133_N54 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X80_Y133_N33 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X93_Y133_N36 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X93_Y133_N6 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X93_Y133_N51 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X93_Y133_N33 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS0:FIFO_fullSS0|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X93_Y133_N24 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|_~1 MLABCELL_X90_Y134_N51 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 MLABCELL_X90_Y134_N33 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X107_Y134_N36 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X106_Y134_N0 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X107_Y134_N24 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X107_Y134_N45 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X106_Y134_N21 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X107_Y134_N15 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X107_Y134_N54 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X107_Y134_N51 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS1:FIFO_fullSS1|scfifo:scfifo_component|scfifo_arh1:auto_generated|a_dpfifo_ece1:dpfifo|dpram_1nb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X107_Y134_N18 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|_~1 LABCELL_X77_Y132_N45 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|a_fefifo_t7f:fifo_state|cntr_2a7:count_usedw|_~0 LABCELL_X77_Y132_N24 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|cntr_m9b:wr_ptr|_~0 LABCELL_X95_Y132_N54 7 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode301w[2] LABCELL_X95_Y132_N27 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode314w[2] LABCELL_X99_Y132_N12 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode322w[2] LABCELL_X99_Y132_N18 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS2:FIFO_fullSS2|scfifo:scfifo_component|scfifo_6rh1:auto_generated|a_dpfifo_bce1:dpfifo|dpram_2nb1:FIFOram|decode_1q6:wr_decode|w_anode330w[2] LABCELL_X99_Y132_N3 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|_~1 LABCELL_X91_Y132_N21 12 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|a_fefifo_b6f:fifo_state|cntr_1a7:count_usedw|_~0 LABCELL_X91_Y132_N3 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|cntr_l9b:wr_ptr|_~0 LABCELL_X91_Y132_N6 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|dpram_3nb1:FIFOram|decode_up6:wr_decode|eq_node[0] LABCELL_X91_Y132_N24 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS3:FIFO_fullSS3|scfifo:scfifo_component|scfifo_8oh1:auto_generated|a_dpfifo_pae1:dpfifo|dpram_3nb1:FIFOram|decode_up6:wr_decode|eq_node[1] LABCELL_X91_Y132_N27 13 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|_~1 LABCELL_X80_Y134_N51 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|a_fefifo_56f:fifo_state|cntr_0a7:count_usedw|_~0 LABCELL_X80_Y134_N21 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|cntr_k9b:wr_ptr|_~0 LABCELL_X80_Y134_N54 5 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS4:FIFO_fullSS4|scfifo:scfifo_component|scfifo_4oh1:auto_generated|a_dpfifo_jae1:dpfifo|valid_wreq LABCELL_X80_Y134_N27 17 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|_~1 LABCELL_X80_Y132_N27 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|a_fefifo_66f:fifo_state|cntr_v97:count_usedw|_~0 LABCELL_X80_Y132_N54 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|cntr_j9b:wr_ptr|_~0 LABCELL_X80_Y132_N24 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS5:FIFO_fullSS5|scfifo:scfifo_component|scfifo_vnh1:auto_generated|a_dpfifo_kae1:dpfifo|valid_wreq LABCELL_X80_Y132_N51 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|_~1 LABCELL_X77_Y131_N45 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X77_Y131_N48 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|a_fefifo_m4f:fifo_state|valid_wreq LABCELL_X77_Y131_N21 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS6:FIFO_fullSS6|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X77_Y131_N24 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|_~1 LABCELL_X79_Y128_N21 6 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|a_fefifo_m4f:fifo_state|cntr_u97:count_usedw|_~0 LABCELL_X79_Y128_N54 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|a_fefifo_m4f:fifo_state|valid_wreq LABCELL_X79_Y128_N27 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTFIFOSS7:FIFO_fullSS7|scfifo:scfifo_component|scfifo_4lh1:auto_generated|a_dpfifo_49e1:dpfifo|cntr_i9b:wr_ptr|_~0 LABCELL_X79_Y128_N48 3 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|_~1 LABCELL_X72_Y130_N27 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|a_fefifo_08f:fifo_state|cntr_3a7:count_usedw|_~0 LABCELL_X72_Y130_N3 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|cntr_n9b:wr_ptr|_~0 LABCELL_X69_Y130_N33 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode390w[3] LABCELL_X69_Y130_N54 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode407w[3] LABCELL_X69_Y130_N48 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode417w[3] LABCELL_X72_Y130_N24 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode427w[3] LABCELL_X72_Y130_N54 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode437w[3] LABCELL_X72_Y130_N51 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode447w[3] LABCELL_X72_Y130_N6 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode457w[3] LABCELL_X72_Y130_N12 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SCTIndexFIFO:FIFO_SSIndex|scfifo:scfifo_component|scfifo_qph1:auto_generated|a_dpfifo_uae1:dpfifo|dpram_elb1:FIFOram|decode_6q6:wr_decode|w_anode467w[3] LABCELL_X69_Y130_N39 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|SSIndex[1]~1 LABCELL_X91_Y131_N42 4 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcreadsct:\HitListCtrlRDSCT:4:Top_HitListControlRDSCT|process_index~1 LABCELL_X94_Y132_N42 29 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcsct_rd_analyze[0] FF_X150_Y104_N32 106 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcsct_rd_analyze[1] FF_X129_Y106_N23 105 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcsct_rd_analyze[2] FF_X102_Y116_N41 104 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcsct_rd_analyze[3] FF_X95_Y14_N41 106 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcsct_rd_analyze[4] FF_X95_Y123_N26 104 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcsct_rd_topread[0] FF_X92_Y109_N8 165 Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:0:Top_HitListControlWRPix|HLM_wrdata_sync1[0]~32 LABCELL_X61_Y124_N24 8 Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:0:Top_HitListControlWRPix|HLP_wrdata_sync1[0][9]~7 LABCELL_X56_Y129_N21 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:0:Top_HitListControlWRPix|HLP_wrdata_sync1[1][9]~6 LABCELL_X61_Y126_N12 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:0:Top_HitListControlWRPix|HLP_wrdata_sync1[2][9]~5 LABCELL_X49_Y128_N27 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:0:Top_HitListControlWRPix|HLP_wrdata_sync1[3][9]~4 MLABCELL_X60_Y128_N36 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:0:Top_HitListControlWRPix|HLP_wrdata_sync1[4][9]~2 LABCELL_X56_Y127_N30 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:0:Top_HitListControlWRPix|HLP_wrdata_sync1[5][9]~3 MLABCELL_X60_Y128_N30 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:0:Top_HitListControlWRPix|HLP_wrdata_sync1[6][9]~1 LABCELL_X61_Y126_N9 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:0:Top_HitListControlWRPix|HLP_wrdata_sync1[7][9]~0 LABCELL_X56_Y127_N33 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:0:Top_HitListControlWRPix|HLP_wren_sync1[3]~0 LABCELL_X61_Y124_N27 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:0:Top_HitListControlWRPix|WR_savedAMSSID[9]~0 LABCELL_X61_Y130_N30 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:0:Top_HitListControlWRPix|WR_savedssid[13]~0 LABCELL_X64_Y124_N9 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:0:Top_HitListControlWRPix|Writelogic~0 LABCELL_X63_Y124_N39 83 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:0:Top_HitListControlWRPix|hlm_wraddr_int[0]~0 LABCELL_X61_Y124_N0 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:0:Top_HitListControlWRPix|hlm_wraddr_int_sync0[0]~0 LABCELL_X61_Y124_N57 20 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:1:Top_HitListControlWRPix|HLM_wrdata_sync1[0]~32 MLABCELL_X90_Y3_N9 8 Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:1:Top_HitListControlWRPix|HLP_wrdata_sync1[0][9]~7 MLABCELL_X90_Y3_N15 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:1:Top_HitListControlWRPix|HLP_wrdata_sync1[1][9]~6 MLABCELL_X90_Y3_N12 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:1:Top_HitListControlWRPix|HLP_wrdata_sync1[2][9]~5 MLABCELL_X90_Y3_N42 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:1:Top_HitListControlWRPix|HLP_wrdata_sync1[3][9]~4 MLABCELL_X90_Y3_N45 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:1:Top_HitListControlWRPix|HLP_wrdata_sync1[4][9]~2 LABCELL_X77_Y2_N48 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:1:Top_HitListControlWRPix|HLP_wrdata_sync1[5][9]~3 LABCELL_X77_Y2_N30 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:1:Top_HitListControlWRPix|HLP_wrdata_sync1[6][9]~1 LABCELL_X80_Y3_N15 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:1:Top_HitListControlWRPix|HLP_wrdata_sync1[7][9]~0 MLABCELL_X90_Y3_N36 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:1:Top_HitListControlWRPix|HLP_wren_sync1[5]~0 MLABCELL_X90_Y3_N3 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:1:Top_HitListControlWRPix|WR_savedAMSSID[5]~0 LABCELL_X98_Y6_N48 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:1:Top_HitListControlWRPix|WR_savedssid[3]~0 LABCELL_X93_Y6_N36 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:1:Top_HitListControlWRPix|Writelogic~0 MLABCELL_X90_Y3_N18 31 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:1:Top_HitListControlWRPix|hlm_wraddr_int[4]~0 MLABCELL_X90_Y3_N54 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:1:Top_HitListControlWRPix|hlm_wraddr_int_sync0[0]~0 MLABCELL_X90_Y3_N27 20 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:2:Top_HitListControlWRPix|HLM_wrdata_sync1[0]~32 LABCELL_X17_Y41_N39 8 Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:2:Top_HitListControlWRPix|HLP_wrdata_sync1[0][9]~7 LABCELL_X18_Y22_N6 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:2:Top_HitListControlWRPix|HLP_wrdata_sync1[1][9]~6 LABCELL_X16_Y24_N30 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:2:Top_HitListControlWRPix|HLP_wrdata_sync1[2][9]~5 LABCELL_X18_Y22_N21 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:2:Top_HitListControlWRPix|HLP_wrdata_sync1[3][9]~4 LABCELL_X18_Y22_N39 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:2:Top_HitListControlWRPix|HLP_wrdata_sync1[4][9]~2 LABCELL_X18_Y22_N0 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:2:Top_HitListControlWRPix|HLP_wrdata_sync1[5][9]~3 LABCELL_X18_Y22_N54 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:2:Top_HitListControlWRPix|HLP_wrdata_sync1[6][9]~1 LABCELL_X18_Y22_N24 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:2:Top_HitListControlWRPix|HLP_wrdata_sync1[7][9]~0 LABCELL_X16_Y41_N45 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:2:Top_HitListControlWRPix|HLP_wren_sync1[3]~0 LABCELL_X17_Y41_N0 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:2:Top_HitListControlWRPix|WR_savedAMSSID[3]~0 LABCELL_X13_Y100_N21 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:2:Top_HitListControlWRPix|WR_savedssid[1]~0 LABCELL_X16_Y101_N21 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:2:Top_HitListControlWRPix|Writelogic~0 LABCELL_X16_Y41_N9 31 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:2:Top_HitListControlWRPix|hlm_wraddr_int[5]~0 LABCELL_X17_Y41_N12 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:2:Top_HitListControlWRPix|hlm_wraddr_int_sync0[0]~0 LABCELL_X17_Y41_N54 20 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:3:Top_HitListControlWRPix|HLM_wrdata_sync1[0]~32 LABCELL_X18_Y118_N57 8 Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:3:Top_HitListControlWRPix|HLP_wrdata_sync1[0][9]~7 LABCELL_X13_Y118_N6 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:3:Top_HitListControlWRPix|HLP_wrdata_sync1[1][9]~6 LABCELL_X13_Y118_N33 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:3:Top_HitListControlWRPix|HLP_wrdata_sync1[2][9]~5 LABCELL_X18_Y118_N45 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:3:Top_HitListControlWRPix|HLP_wrdata_sync1[3][9]~4 LABCELL_X13_Y118_N24 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:3:Top_HitListControlWRPix|HLP_wrdata_sync1[4][9]~2 LABCELL_X18_Y118_N12 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:3:Top_HitListControlWRPix|HLP_wrdata_sync1[5][9]~3 LABCELL_X18_Y118_N18 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:3:Top_HitListControlWRPix|HLP_wrdata_sync1[6][9]~1 LABCELL_X18_Y118_N36 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:3:Top_HitListControlWRPix|HLP_wrdata_sync1[7][9]~0 LABCELL_X18_Y118_N42 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:3:Top_HitListControlWRPix|HLP_wren_sync1[7]~0 LABCELL_X18_Y118_N0 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:3:Top_HitListControlWRPix|WR_savedAMSSID[1]~0 LABCELL_X16_Y121_N12 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:3:Top_HitListControlWRPix|WR_savedssid[11]~0 MLABCELL_X15_Y121_N6 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:3:Top_HitListControlWRPix|Writelogic~0 LABCELL_X23_Y118_N9 31 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:3:Top_HitListControlWRPix|hlm_wraddr_int[1]~0 LABCELL_X18_Y118_N6 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:3:Top_HitListControlWRPix|hlm_wraddr_int_sync0[0]~0 LABCELL_X18_Y118_N51 20 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:4:Top_HitListControlWRPix|HLM_wrdata_sync1[0]~32 LABCELL_X150_Y117_N9 8 Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:4:Top_HitListControlWRPix|HLP_wrdata_sync1[0][9]~7 LABCELL_X150_Y117_N24 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:4:Top_HitListControlWRPix|HLP_wrdata_sync1[1][9]~6 LABCELL_X150_Y117_N0 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:4:Top_HitListControlWRPix|HLP_wrdata_sync1[2][9]~5 LABCELL_X150_Y117_N27 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:4:Top_HitListControlWRPix|HLP_wrdata_sync1[3][9]~4 LABCELL_X150_Y117_N21 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:4:Top_HitListControlWRPix|HLP_wrdata_sync1[4][9]~2 LABCELL_X150_Y117_N42 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:4:Top_HitListControlWRPix|HLP_wrdata_sync1[5][9]~3 LABCELL_X150_Y117_N18 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:4:Top_HitListControlWRPix|HLP_wrdata_sync1[6][9]~1 LABCELL_X150_Y117_N6 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:4:Top_HitListControlWRPix|HLP_wrdata_sync1[7][9]~0 LABCELL_X150_Y117_N3 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:4:Top_HitListControlWRPix|HLP_wren_sync1[6]~0 LABCELL_X150_Y117_N45 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:4:Top_HitListControlWRPix|WR_savedAMSSID[0]~0 LABCELL_X150_Y125_N9 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:4:Top_HitListControlWRPix|WR_savedssid[8]~0 LABCELL_X144_Y125_N3 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:4:Top_HitListControlWRPix|Writelogic~0 LABCELL_X150_Y117_N39 31 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:4:Top_HitListControlWRPix|hlm_wraddr_int[9]~0 LABCELL_X145_Y114_N24 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:4:Top_HitListControlWRPix|hlm_wraddr_int_sync0[0]~0 LABCELL_X145_Y114_N27 20 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:5:Top_HitListControlWRPix|HLM_wrdata_sync1[0]~32 LABCELL_X45_Y118_N15 8 Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:5:Top_HitListControlWRPix|HLP_wrdata_sync1[0][9]~7 LABCELL_X49_Y118_N48 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:5:Top_HitListControlWRPix|HLP_wrdata_sync1[1][9]~6 LABCELL_X49_Y118_N21 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:5:Top_HitListControlWRPix|HLP_wrdata_sync1[2][9]~5 LABCELL_X49_Y118_N54 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:5:Top_HitListControlWRPix|HLP_wrdata_sync1[3][9]~4 LABCELL_X49_Y118_N12 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:5:Top_HitListControlWRPix|HLP_wrdata_sync1[4][9]~2 LABCELL_X49_Y118_N42 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:5:Top_HitListControlWRPix|HLP_wrdata_sync1[5][9]~3 LABCELL_X49_Y118_N24 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:5:Top_HitListControlWRPix|HLP_wrdata_sync1[6][9]~1 LABCELL_X49_Y118_N15 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:5:Top_HitListControlWRPix|HLP_wrdata_sync1[7][9]~0 LABCELL_X49_Y118_N39 20 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:5:Top_HitListControlWRPix|HLP_wren_sync1[1]~0 LABCELL_X45_Y118_N30 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:5:Top_HitListControlWRPix|WR_savedAMSSID[9]~0 LABCELL_X47_Y122_N36 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:5:Top_HitListControlWRPix|WR_savedssid[13]~0 LABCELL_X48_Y118_N6 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:5:Top_HitListControlWRPix|Writelogic~0 LABCELL_X45_Y118_N36 31 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:5:Top_HitListControlWRPix|hlm_wraddr_int[2]~0 LABCELL_X45_Y117_N33 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritepix:\HitListCtrlWRPix:5:Top_HitListControlWRPix|hlm_wraddr_int_sync0[0]~0 LABCELL_X45_Y117_N36 20 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:0:Top_HitListControlWRSCT|HLM_wrdata_sync1[0]~14 LABCELL_X140_Y10_N51 8 Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:0:Top_HitListControlWRSCT|HLP_wrdata_sync1[0][9]~7 LABCELL_X140_Y10_N30 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:0:Top_HitListControlWRSCT|HLP_wrdata_sync1[1][9]~6 LABCELL_X140_Y10_N0 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:0:Top_HitListControlWRSCT|HLP_wrdata_sync1[2][9]~5 LABCELL_X140_Y10_N12 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:0:Top_HitListControlWRSCT|HLP_wrdata_sync1[3][9]~4 LABCELL_X140_Y10_N18 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:0:Top_HitListControlWRSCT|HLP_wrdata_sync1[4][9]~2 LABCELL_X140_Y10_N42 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:0:Top_HitListControlWRSCT|HLP_wrdata_sync1[5][9]~3 LABCELL_X140_Y10_N33 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:0:Top_HitListControlWRSCT|HLP_wrdata_sync1[6][9]~1 LABCELL_X140_Y10_N24 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:0:Top_HitListControlWRSCT|HLP_wrdata_sync1[7][9]~0 LABCELL_X140_Y10_N27 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:0:Top_HitListControlWRSCT|HLP_wren_sync1[6]~0 LABCELL_X140_Y10_N6 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:0:Top_HitListControlWRSCT|WR_savedAMSSID[6]~0 LABCELL_X139_Y5_N51 11 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:0:Top_HitListControlWRSCT|Writelogic~0 LABCELL_X139_Y10_N33 31 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:0:Top_HitListControlWRSCT|\Writelogic:WR_tempCNT[0]~0 LABCELL_X128_Y10_N54 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:0:Top_HitListControlWRSCT|hlm_wraddr_int[3]~0 LABCELL_X140_Y10_N48 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:0:Top_HitListControlWRSCT|hlm_wraddr_int_sync0[0]~0 LABCELL_X140_Y10_N15 20 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:1:Top_HitListControlWRSCT|HLM_wrdata_sync1[0]~14 LABCELL_X159_Y109_N6 8 Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:1:Top_HitListControlWRSCT|HLP_wrdata_sync1[0][9]~7 LABCELL_X159_Y109_N21 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:1:Top_HitListControlWRSCT|HLP_wrdata_sync1[1][9]~6 LABCELL_X159_Y109_N27 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:1:Top_HitListControlWRSCT|HLP_wrdata_sync1[2][9]~5 LABCELL_X159_Y109_N15 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:1:Top_HitListControlWRSCT|HLP_wrdata_sync1[3][9]~4 LABCELL_X158_Y109_N24 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:1:Top_HitListControlWRSCT|HLP_wrdata_sync1[4][9]~2 LABCELL_X158_Y109_N33 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:1:Top_HitListControlWRSCT|HLP_wrdata_sync1[5][9]~3 LABCELL_X159_Y109_N24 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:1:Top_HitListControlWRSCT|HLP_wrdata_sync1[6][9]~1 LABCELL_X159_Y109_N33 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:1:Top_HitListControlWRSCT|HLP_wrdata_sync1[7][9]~0 LABCELL_X159_Y109_N3 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:1:Top_HitListControlWRSCT|HLP_wren_sync1[3]~0 LABCELL_X159_Y109_N39 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:1:Top_HitListControlWRSCT|WR_savedAMSSID[10]~0 LABCELL_X166_Y125_N51 11 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:1:Top_HitListControlWRSCT|Writelogic~0 LABCELL_X159_Y109_N57 31 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:1:Top_HitListControlWRSCT|\Writelogic:WR_tempCNT[2]~0 MLABCELL_X165_Y125_N51 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:1:Top_HitListControlWRSCT|hlm_wraddr_int[1]~0 LABCELL_X159_Y109_N45 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:1:Top_HitListControlWRSCT|hlm_wraddr_int_sync0[0]~0 LABCELL_X159_Y109_N9 20 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:2:Top_HitListControlWRSCT|HLM_wrdata_sync1[0]~14 LABCELL_X134_Y117_N30 8 Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:2:Top_HitListControlWRSCT|HLP_wrdata_sync1[0][9]~7 LABCELL_X129_Y116_N48 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:2:Top_HitListControlWRSCT|HLP_wrdata_sync1[1][9]~6 LABCELL_X136_Y116_N45 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:2:Top_HitListControlWRSCT|HLP_wrdata_sync1[2][9]~5 LABCELL_X136_Y116_N36 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:2:Top_HitListControlWRSCT|HLP_wrdata_sync1[3][9]~4 LABCELL_X136_Y116_N48 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:2:Top_HitListControlWRSCT|HLP_wrdata_sync1[4][9]~2 LABCELL_X136_Y116_N30 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:2:Top_HitListControlWRSCT|HLP_wrdata_sync1[5][9]~3 LABCELL_X136_Y116_N39 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:2:Top_HitListControlWRSCT|HLP_wrdata_sync1[6][9]~1 LABCELL_X136_Y116_N54 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:2:Top_HitListControlWRSCT|HLP_wrdata_sync1[7][9]~0 LABCELL_X136_Y116_N51 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:2:Top_HitListControlWRSCT|HLP_wren_sync1[5]~0 LABCELL_X135_Y117_N6 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:2:Top_HitListControlWRSCT|WR_savedAMSSID[6]~0 MLABCELL_X131_Y117_N42 11 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:2:Top_HitListControlWRSCT|Writelogic~0 LABCELL_X135_Y117_N24 31 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:2:Top_HitListControlWRSCT|\Writelogic:WR_tempCNT[2]~0 LABCELL_X128_Y115_N6 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:2:Top_HitListControlWRSCT|hlm_wraddr_int[3]~0 LABCELL_X135_Y117_N12 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:2:Top_HitListControlWRSCT|hlm_wraddr_int_sync0[0]~0 LABCELL_X135_Y117_N48 20 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:3:Top_HitListControlWRSCT|HLM_wrdata_sync1[0]~14 LABCELL_X50_Y12_N9 8 Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:3:Top_HitListControlWRSCT|HLP_wrdata_sync1[0][9]~7 LABCELL_X50_Y12_N33 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:3:Top_HitListControlWRSCT|HLP_wrdata_sync1[1][9]~6 LABCELL_X50_Y12_N54 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:3:Top_HitListControlWRSCT|HLP_wrdata_sync1[2][9]~5 LABCELL_X50_Y12_N18 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:3:Top_HitListControlWRSCT|HLP_wrdata_sync1[3][9]~4 LABCELL_X50_Y12_N21 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:3:Top_HitListControlWRSCT|HLP_wrdata_sync1[4][9]~2 LABCELL_X50_Y12_N30 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:3:Top_HitListControlWRSCT|HLP_wrdata_sync1[5][9]~3 LABCELL_X50_Y12_N15 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:3:Top_HitListControlWRSCT|HLP_wrdata_sync1[6][9]~1 LABCELL_X50_Y12_N57 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:3:Top_HitListControlWRSCT|HLP_wrdata_sync1[7][9]~0 LABCELL_X50_Y12_N6 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:3:Top_HitListControlWRSCT|HLP_wren_sync1[0]~0 LABCELL_X50_Y12_N0 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:3:Top_HitListControlWRSCT|WR_savedAMSSID[0]~0 LABCELL_X42_Y10_N12 11 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:3:Top_HitListControlWRSCT|Writelogic~0 LABCELL_X57_Y12_N3 31 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:3:Top_HitListControlWRSCT|\Writelogic:WR_tempCNT[2]~0 LABCELL_X48_Y12_N33 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:3:Top_HitListControlWRSCT|hlm_wraddr_int[6]~0 MLABCELL_X52_Y12_N45 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:3:Top_HitListControlWRSCT|hlm_wraddr_int_sync0[0]~0 MLABCELL_X52_Y12_N54 20 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:4:Top_HitListControlWRSCT|HLM_wrdata_sync1[0]~14 LABCELL_X108_Y127_N42 8 Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:4:Top_HitListControlWRSCT|HLP_wrdata_sync1[0][9]~7 LABCELL_X107_Y128_N39 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:4:Top_HitListControlWRSCT|HLP_wrdata_sync1[1][9]~6 LABCELL_X108_Y127_N33 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:4:Top_HitListControlWRSCT|HLP_wrdata_sync1[2][9]~5 LABCELL_X107_Y128_N18 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:4:Top_HitListControlWRSCT|HLP_wrdata_sync1[3][9]~4 LABCELL_X107_Y128_N51 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:4:Top_HitListControlWRSCT|HLP_wrdata_sync1[4][9]~2 LABCELL_X107_Y128_N42 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:4:Top_HitListControlWRSCT|HLP_wrdata_sync1[5][9]~3 LABCELL_X107_Y128_N27 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:4:Top_HitListControlWRSCT|HLP_wrdata_sync1[6][9]~1 LABCELL_X108_Y127_N0 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:4:Top_HitListControlWRSCT|HLP_wrdata_sync1[7][9]~0 LABCELL_X107_Y128_N12 21 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:4:Top_HitListControlWRSCT|HLP_wren_sync1[1]~0 LABCELL_X109_Y127_N45 8 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:4:Top_HitListControlWRSCT|WR_savedAMSSID[0]~0 LABCELL_X112_Y131_N9 11 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:4:Top_HitListControlWRSCT|Writelogic~0 LABCELL_X109_Y127_N18 31 Sync. load no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:4:Top_HitListControlWRSCT|\Writelogic:WR_tempCNT[0]~0 MLABCELL_X113_Y130_N33 14 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:4:Top_HitListControlWRSCT|hlm_wraddr_int[4]~0 LABCELL_X109_Y127_N24 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlcwritesct:\HitListCtrlWRSCT:4:Top_HitListControlWRSCT|hlm_wraddr_int_sync0[0]~0 LABCELL_X108_Y127_N21 20 Clock enable, Sync. clear no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_rden[0] FF_X53_Y118_N25 5 Read enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_rden[1] FF_X71_Y12_N22 5 Read enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_rden[2] FF_X32_Y24_N34 5 Read enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_rden[3] FF_X26_Y111_N4 5 Read enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_rden[4] FF_X142_Y111_N28 5 Read enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_rden[5] FF_X80_Y113_N55 5 Read enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_wraddr[0][0]~0 LABCELL_X50_Y124_N27 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_wraddr[1][0]~1 LABCELL_X79_Y74_N24 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_wraddr[2][0]~2 MLABCELL_X20_Y31_N51 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_wraddr[3][0]~3 LABCELL_X26_Y114_N21 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_wraddr[4][0]~4 MLABCELL_X146_Y114_N27 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_wraddr[5][0]~5 MLABCELL_X60_Y115_N30 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_wren[0] FF_X52_Y117_N1 4 Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_wren[1] FF_X79_Y74_N16 4 Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_wren[2] FF_X28_Y96_N52 4 Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_wren[3] FF_X26_Y114_N25 4 Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_wren[4] FF_X146_Y110_N40 4 Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmpix_wren[5] FF_X60_Y115_N1 4 Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmsct_rden[0] FF_X150_Y104_N23 3 Read enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmsct_rden[1] FF_X161_Y103_N1 3 Read enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmsct_rden[2] FF_X146_Y116_N56 3 Read enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmsct_rden[3] FF_X95_Y14_N28 3 Read enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmsct_rden[4] FF_X98_Y124_N25 3 Read enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmsct_wraddr[0][0]~0 LABCELL_X137_Y11_N39 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmsct_wraddr[1][0]~1 LABCELL_X155_Y103_N51 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmsct_wraddr[2][0]~2 LABCELL_X132_Y115_N45 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmsct_wraddr[3][0]~3 MLABCELL_X68_Y14_N42 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmsct_wraddr[4][0]~4 LABCELL_X107_Y124_N45 10 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmsct_wren[0] FF_X137_Y11_N13 2 Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmsct_wren[1] FF_X155_Y103_N49 2 Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmsct_wren[2] FF_X132_Y115_N52 2 Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmsct_wren[3] FF_X68_Y14_N52 2 Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlmsct_wren[4] FF_X107_Y124_N4 2 Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_rden[0][0] FF_X66_Y124_N40 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_rden[1][0] FF_X66_Y8_N31 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_rden[2][0] FF_X26_Y18_N31 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_rden[3][0] FF_X16_Y117_N37 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_rden[4][0] FF_X161_Y116_N40 16 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_rden[5][0] FF_X58_Y120_N4 1 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_rden[5][0]~DUPLICATE FF_X58_Y120_N5 15 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[0][0] FF_X61_Y126_N40 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[0][1] FF_X60_Y124_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[0][2] FF_X50_Y128_N16 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[0][3] FF_X60_Y124_N11 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[0][4] FF_X52_Y127_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[0][5] FF_X60_Y124_N49 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[0][6] FF_X60_Y124_N46 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[0][7] FF_X52_Y126_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[1][0] FF_X79_Y3_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[1][1] FF_X76_Y3_N46 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[1][2] FF_X79_Y3_N34 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[1][3] FF_X79_Y3_N1 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[1][4] FF_X76_Y1_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[1][5] FF_X90_Y2_N19 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[1][6] FF_X76_Y3_N4 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[1][7] FF_X90_Y4_N52 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[2][0] FF_X23_Y23_N1 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[2][1] FF_X20_Y21_N40 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[2][2] FF_X23_Y23_N58 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[2][3] FF_X23_Y23_N28 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[2][4] FF_X23_Y23_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[2][5] FF_X23_Y23_N46 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[2][6] FF_X23_Y23_N10 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[2][7] FF_X23_Y23_N49 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[3][0] FF_X16_Y119_N16 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[3][1] FF_X16_Y119_N19 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[3][2] FF_X24_Y121_N1 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[3][3] FF_X4_Y117_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[3][4] FF_X18_Y122_N26 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[3][5] FF_X16_Y119_N52 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[3][6] FF_X18_Y119_N17 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[3][7] FF_X26_Y118_N17 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[4][0] FF_X149_Y114_N4 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[4][1] FF_X150_Y114_N25 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[4][2] FF_X142_Y113_N29 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[4][3] FF_X150_Y116_N16 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[4][4] FF_X149_Y116_N52 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[4][5] FF_X149_Y117_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[4][6] FF_X151_Y117_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[4][7] FF_X150_Y115_N52 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[5][0] FF_X50_Y121_N28 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[5][1] FF_X52_Y120_N10 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[5][2] FF_X50_Y123_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[5][3] FF_X58_Y121_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[5][4] FF_X60_Y122_N50 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[5][5] FF_X48_Y119_N37 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[5][6] FF_X44_Y119_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlppix_wren[5][7] FF_X45_Y119_N13 1 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_rden[0][0] FF_X132_Y16_N25 24 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_rden[1][0] FF_X161_Y104_N13 24 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_rden[2][0] FF_X135_Y116_N55 24 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_rden[3][0] FF_X74_Y9_N10 24 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_rden[4][0] FF_X98_Y126_N7 24 Clock enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[0][0] FF_X142_Y11_N37 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[0][1] FF_X145_Y10_N19 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[0][2] FF_X146_Y13_N13 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[0][3] FF_X142_Y10_N16 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[0][4] FF_X141_Y10_N1 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[0][5] FF_X137_Y14_N13 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[0][6] FF_X139_Y13_N16 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[0][7] FF_X145_Y10_N37 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[1][0] FF_X163_Y109_N52 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[1][1] FF_X147_Y106_N13 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[1][2] FF_X147_Y105_N52 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[1][3] FF_X154_Y109_N52 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[1][4] FF_X147_Y109_N40 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[1][5] FF_X158_Y108_N37 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[1][6] FF_X163_Y109_N55 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[1][7] FF_X163_Y108_N1 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[2][0] FF_X134_Y112_N52 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[2][1] FF_X146_Y118_N13 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[2][2] FF_X137_Y116_N34 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[2][3] FF_X146_Y116_N25 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[2][4] FF_X147_Y120_N13 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[2][5] FF_X147_Y119_N38 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[2][6] FF_X137_Y116_N37 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[2][7] FF_X147_Y115_N52 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[3][0] FF_X58_Y10_N28 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[3][1] FF_X52_Y13_N25 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[3][2] FF_X52_Y12_N16 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[3][3] FF_X50_Y11_N16 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[3][4] FF_X52_Y12_N28 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[3][5] FF_X52_Y12_N10 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[3][6] FF_X68_Y12_N52 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[3][7] FF_X63_Y11_N52 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[4][0] FF_X102_Y127_N2 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[4][1] FF_X108_Y130_N25 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[4][2] FF_X107_Y126_N13 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[4][3] FF_X100_Y125_N49 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[4][4] FF_X108_Y126_N49 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[4][5] FF_X108_Y129_N49 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[4][6] FF_X108_Y130_N59 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DO11L:b2v_inst|hlpsct_wren[4][7] FF_X107_Y128_N50 2 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|DOPrepAMInput:PrepAMInput_inst|fifo_32_to_256:VMEAMCBUFFER|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_ual1:auto_generated|_~0 MLABCELL_X60_Y16_N51 4 Clock enable no -- -- --
DataOrganizer:inst129|DOPrepAMInput:PrepAMInput_inst|fifo_32_to_256:VMEAMCBUFFER|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_ual1:auto_generated|valid_rdreq~2 LABCELL_X47_Y16_N6 19 Clock enable no -- -- --
DataOrganizer:inst129|DOPrepAMInput:PrepAMInput_inst|fifo_32_to_256:VMEAMCBUFFER|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_ual1:auto_generated|valid_wrreq~0 MLABCELL_X60_Y16_N33 26 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|ammapintram:b2v_inst4|roadFIFO:roadFIFO_inst|scfifo:scfifo_component|scfifo_3nb1:auto_generated|a_dpfifo_rr81:dpfifo|_~5 LABCELL_X66_Y106_N54 6 Clock enable no -- -- --
DataOrganizer:inst129|ammapintram:b2v_inst4|roadFIFO:roadFIFO_inst|scfifo:scfifo_component|scfifo_3nb1:auto_generated|a_dpfifo_rr81:dpfifo|ram_read_address[0]~5 LABCELL_X71_Y78_N0 4 Clock enable no -- -- --
DataOrganizer:inst129|ammapintram:b2v_inst4|roadFIFO:roadFIFO_inst|scfifo:scfifo_component|scfifo_3nb1:auto_generated|a_dpfifo_rr81:dpfifo|valid_rreq LABCELL_X71_Y78_N57 5 Clock enable no -- -- --
DataOrganizer:inst129|ammapintram:b2v_inst4|roadFIFO:roadFIFO_inst|scfifo:scfifo_component|scfifo_3nb1:auto_generated|a_dpfifo_rr81:dpfifo|valid_wreq LABCELL_X66_Y106_N18 14 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|dcfifo:dcfifo_DOReadExtMem_inst|dcfifo_35l1:auto_generated|cmpr_0o5:rdempty_eq_comp|aneb_result_wire[0] LABCELL_X50_Y24_N24 11 Clock enable no -- -- --
DataOrganizer:inst129|dcfifo:dcfifo_DOReadExtMem_inst|dcfifo_35l1:auto_generated|valid_wrreq~2 LABCELL_X48_Y24_N3 10 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|dcfifo:dcfifo_DOWriteExtMem_inst|dcfifo_4fk1:auto_generated|cmpr_0o5:rdempty_eq_comp|aneb_result_wire[0] LABCELL_X57_Y18_N30 27 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|dcfifo:dcfifo_DOWriteExtMem_inst|dcfifo_4fk1:auto_generated|valid_wrreq~0 MLABCELL_X60_Y18_N12 14 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|dcfifo:dcfifo_ExtMemDO_inst|dcfifo_j8l1:auto_generated|cmpr_0o5:rdempty_eq_comp|aneb_result_wire[0] LABCELL_X71_Y78_N3 22 Clock enable no -- -- --
DataOrganizer:inst129|dcfifo:dcfifo_ExtMemDO_inst|dcfifo_j8l1:auto_generated|valid_wrreq~2 LABCELL_X69_Y23_N27 14 Clock enable, Write enable no -- -- --
DataOrganizer:inst129|extmem_rden MLABCELL_X68_Y23_N57 16 Clock enable no -- -- --
DataOrganizer:inst129|fsmtest11L:b2v_inst3|fsm_write_sync0[0] FF_X79_Y106_N14 49 Sync. clear no -- -- --
DataOrganizer:inst129|fsmtest11L:b2v_inst3|fsm_write_sync0[10] FF_X92_Y107_N20 31 Sync. clear no -- -- --
DataOrganizer:inst129|fsmtest11L:b2v_inst3|fsm_write_sync0[1] FF_X77_Y106_N46 48 Sync. clear no -- -- --
DataOrganizer:inst129|fsmtest11L:b2v_inst3|fsm_write_sync0[2] FF_X71_Y103_N47 48 Sync. clear no -- -- --
DataOrganizer:inst129|fsmtest11L:b2v_inst3|fsm_write_sync0[3] FF_X74_Y106_N29 49 Sync. clear no -- -- --
DataOrganizer:inst129|fsmtest11L:b2v_inst3|fsm_write_sync0[4] FF_X134_Y110_N26 49 Sync. clear no -- -- --
DataOrganizer:inst129|fsmtest11L:b2v_inst3|fsm_write_sync0[5] FF_X71_Y114_N5 48 Sync. clear no -- -- --
DataOrganizer:inst129|fsmtest11L:b2v_inst3|fsm_write_sync0[6] FF_X77_Y107_N35 31 Sync. clear no -- -- --
DataOrganizer:inst129|fsmtest11L:b2v_inst3|fsm_write_sync0[7] FF_X151_Y106_N40 30 Sync. clear no -- -- --
DataOrganizer:inst129|fsmtest11L:b2v_inst3|fsm_write_sync0[8] FF_X76_Y107_N58 30 Sync. clear no -- -- --
DataOrganizer:inst129|fsmtest11L:b2v_inst3|fsm_write_sync0[9] FF_X90_Y107_N23 30 Sync. clear no -- -- --
DataOrganizer:inst129|inroadchan_sync0~2 LABCELL_X80_Y107_N51 42 Sync. clear no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:0:hit_fifo_pix|data_int[18]~0 MLABCELL_X174_Y97_N33 33 Sync. load no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:0:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|_~0 LABCELL_X181_Y97_N24 9 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:0:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|valid_rreq MLABCELL_X176_Y97_N54 14 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:0:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|valid_wreq MLABCELL_X176_Y97_N33 20 Clock enable, Write enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:1:hit_fifo_pix|data_int[22]~0 LABCELL_X132_Y94_N18 33 Sync. load no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:1:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|_~0 LABCELL_X128_Y94_N57 9 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:1:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|valid_rreq LABCELL_X128_Y94_N30 13 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:1:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|valid_wreq LABCELL_X128_Y94_N36 20 Clock enable, Write enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:2:hit_fifo_pix|data_int[20]~0 LABCELL_X164_Y90_N6 33 Sync. load no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:2:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|_~0 MLABCELL_X165_Y90_N15 9 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:2:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|valid_wreq LABCELL_X166_Y90_N3 20 Clock enable, Write enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:2:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|valid_rreq LABCELL_X166_Y90_N18 13 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:3:hit_fifo_pix|data_int[1]~0 LABCELL_X142_Y76_N27 33 Sync. load no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:3:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|_~0 LABCELL_X140_Y74_N39 9 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:3:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|valid_wreq LABCELL_X139_Y74_N3 20 Clock enable, Write enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:3:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|valid_rreq LABCELL_X140_Y74_N36 13 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:4:hit_fifo_pix|data_int[20]~0 MLABCELL_X151_Y96_N21 33 Sync. load no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:4:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|_~0 LABCELL_X159_Y96_N30 9 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:4:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|valid_rreq LABCELL_X159_Y96_N33 14 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:4:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|valid_wreq LABCELL_X159_Y96_N36 20 Clock enable, Write enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:5:hit_fifo_pix|data_int[17]~0 LABCELL_X149_Y76_N12 33 Sync. load no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:5:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|_~0 MLABCELL_X146_Y78_N18 9 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:5:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|valid_rreq MLABCELL_X146_Y78_N30 14 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_pix_streams:5:hit_fifo_pix|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|valid_wreq MLABCELL_X146_Y78_N45 20 Clock enable, Write enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:0:hit_fifo_sct|data_int[4]~0 LABCELL_X56_Y26_N12 33 Sync. load no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:0:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|_~0 LABCELL_X55_Y26_N42 9 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:0:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|valid_wreq LABCELL_X55_Y26_N57 20 Clock enable, Write enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:0:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|valid_rreq LABCELL_X55_Y26_N33 14 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:1:hit_fifo_sct|data_int[24]~0 LABCELL_X31_Y40_N24 33 Sync. load no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:1:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|_~0 LABCELL_X26_Y40_N15 10 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:1:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|valid_rreq LABCELL_X26_Y40_N21 13 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:1:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|valid_wreq LABCELL_X26_Y40_N18 20 Clock enable, Write enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:2:hit_fifo_sct|data_int[31]~0 LABCELL_X26_Y32_N39 33 Sync. load no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:2:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|_~0 LABCELL_X21_Y32_N15 10 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:2:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|valid_wreq LABCELL_X21_Y32_N0 20 Clock enable, Write enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:2:hit_fifo_sct|valid_data~0 LABCELL_X21_Y32_N27 13 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:3:hit_fifo_sct|data_int[27]~0 LABCELL_X56_Y88_N57 33 Sync. load no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:3:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|_~0 LABCELL_X55_Y88_N6 9 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:3:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|valid_rreq LABCELL_X55_Y88_N18 14 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:3:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|valid_wreq LABCELL_X55_Y88_N0 20 Clock enable, Write enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:4:hit_fifo_sct|data_int[18]~0 LABCELL_X95_Y91_N9 33 Sync. load no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:4:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|a_fefifo_t7e:fifo_state|_~0 LABCELL_X94_Y36_N9 10 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:4:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|valid_rreq LABCELL_X94_Y36_N21 13 Clock enable no -- -- --
InputHitFIFOS:InputHitFIFOS_inst|user_logic_fifo:\gen_sct_streams:4:hit_fifo_sct|tx_fifo:fifo_inst|scfifo:scfifo_component|scfifo_4m81:auto_generated|a_dpfifo_bs81:dpfifo|valid_wreq LABCELL_X94_Y36_N6 21 Clock enable, Write enable no -- -- --
NewAMBRoundRobin:round_robin_inst|data_reg[9]~1 LABCELL_X17_Y37_N45 32 Sync. clear no -- -- --
NewAMBRoundRobin:round_robin_inst|fifo_32_to_32_forDO:VMEAMCBUFFER|dcfifo:dcfifo_component|dcfifo_gal1:auto_generated|valid_rdreq~0 MLABCELL_X36_Y38_N39 26 Clock enable no -- -- --
NewAMBRoundRobin:round_robin_inst|fifo_32_to_32_forDO:VMEAMCBUFFER|dcfifo:dcfifo_component|dcfifo_gal1:auto_generated|valid_wrreq LABCELL_X28_Y34_N54 27 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_analog:analog.sc_analog|alt_xcvr_reconfig_analog_av:reconfig_analog_av|alt_xreconf_analog_datactrl_av:inst_analog_datactrl|alt_xreconf_analog_rmw_av:inst_rmw_sm|always2~0 LABCELL_X16_Y53_N3 32 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_analog:analog.sc_analog|alt_xcvr_reconfig_analog_av:reconfig_analog_av|alt_xreconf_cif:inst_xreconf_cif|alt_xreconf_basic_acq:inst_basic_acq|Selector8~0 LABCELL_X11_Y53_N18 30 Sync. clear no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_analog:analog.sc_analog|alt_xcvr_reconfig_analog_av:reconfig_analog_av|alt_xreconf_cif:inst_xreconf_cif|alt_xreconf_basic_acq:inst_basic_acq|readdata_for_user[0]~0 LABCELL_X13_Y53_N9 32 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_analog:analog.sc_analog|alt_xcvr_reconfig_analog_av:reconfig_analog_av|alt_xreconf_uif:inst_xreconf_uif|Decoder0~0 LABCELL_X16_Y49_N12 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_analog:analog.sc_analog|alt_xcvr_reconfig_analog_av:reconfig_analog_av|alt_xreconf_uif:inst_xreconf_uif|Decoder0~1 LABCELL_X16_Y49_N57 6 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_analog:analog.sc_analog|alt_xcvr_reconfig_analog_av:reconfig_analog_av|alt_xreconf_uif:inst_xreconf_uif|Decoder0~2 LABCELL_X16_Y49_N36 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|always0~0 MLABCELL_X6_Y61_N15 13 Sync. clear no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|Equal12~0 LABCELL_X11_Y56_N24 21 Sync. load no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|always0~0 LABCELL_X11_Y56_N0 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|always1~0 MLABCELL_X15_Y56_N36 13 Sync. load no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|always6~0 MLABCELL_X6_Y56_N30 6 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|reco_addr[10]~1 LABCELL_X7_Y56_N21 15 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|reg_addr[4]~0 LABCELL_X17_Y56_N27 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|reg_rwdata[7]~1 LABCELL_X10_Y54_N15 16 Sync. clear no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|reg_rwdata[7]~2 MLABCELL_X8_Y54_N33 85 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|reg_write_incr~1 MLABCELL_X6_Y56_N45 4 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|csr_mux:pif_tbus_mux|out_narrow[0] LABCELL_X4_Y54_N3 2 Clock no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|csr_mux:pif_tbus_mux|out_narrow[1] LABCELL_X1_Y55_N30 2 Clock no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|csr_mux:pif_tbus_mux|out_narrow[2] MLABCELL_X3_Y55_N45 2 Clock no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|csr_mux:pif_tbus_mux|out_narrow[3] LABCELL_X1_Y55_N33 2 Clock no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|reg_init[0]~0 LABCELL_X7_Y61_N57 13 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|Selector0~6 LABCELL_X7_Y51_N9 10 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|Selector21~0 LABCELL_X16_Y51_N33 13 Sync. load no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_arbiter_acq:mutex_inst|waitrequest~0 LABCELL_X11_Y53_N15 71 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd0_det|pd_xor~0 LABCELL_X7_Y51_N21 1 Clock no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd180_det|pd_xor~0 LABCELL_X2_Y52_N36 1 Clock no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd270_det|pd_xor~0 LABCELL_X2_Y60_N24 1 Clock no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd90_det|pd_xor~0 LABCELL_X2_Y53_N3 1 Clock no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|cal_pd0_l[0]~1 MLABCELL_X3_Y53_N39 4 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|cal_pd180_l[3]~1 MLABCELL_X3_Y53_N6 4 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|cal_pd270_l[0]~1 MLABCELL_X8_Y50_N54 4 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|cal_pd90_l[2]~1 MLABCELL_X3_Y53_N27 7 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|counter[2]~0 LABCELL_X2_Y51_N6 8 Sync. clear no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|counter[2]~1 LABCELL_X2_Y51_N27 8 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|dataout[0]~2 LABCELL_X4_Y51_N33 16 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|pd_0[0]~1 MLABCELL_X3_Y51_N36 9 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|pd_0_p[0]~1 LABCELL_X2_Y53_N39 8 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|recal_counter[1]~0 LABCELL_X2_Y52_N3 2 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|state.DPRIO_WRITE FF_X6_Y51_N17 13 Async. clear no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|state.SAMPLE_TB FF_X3_Y53_N35 21 Sync. load no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_remap_addr[6]~0 LABCELL_X16_Y51_N24 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|master_write_data[12]~16 LABCELL_X9_Y51_N45 2 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|master_write_data[14]~12 MLABCELL_X8_Y51_N36 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|master_write_data[14]~17 MLABCELL_X15_Y53_N21 16 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|master_write_data[6]~7 MLABCELL_X8_Y51_N0 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|alt_xcvr_resync:inst_reconfig_reset_sync|resync_chains[0].sync_r[1] FF_X2_Y61_N2 320 Async. clear no -- -- --
RxBlock:RxBlock_inst|RxTx_4_2Gbps1Gbps_reco:reco1_inst|alt_xcvr_reconfig:rxtx_4_2gbps1gbps_reco_inst|ifsel_notdone_resync FF_X9_Y53_N29 407 Async. clear, Clock enable, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_analog:analog.sc_analog|alt_xcvr_reconfig_analog_av:reconfig_analog_av|alt_xreconf_analog_datactrl_av:inst_analog_datactrl|alt_xreconf_analog_rmw_av:inst_rmw_sm|always2~0 LABCELL_X163_Y16_N24 32 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_analog:analog.sc_analog|alt_xcvr_reconfig_analog_av:reconfig_analog_av|alt_xreconf_cif:inst_xreconf_cif|alt_xreconf_basic_acq:inst_basic_acq|Selector8~5 MLABCELL_X165_Y16_N39 26 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_analog:analog.sc_analog|alt_xcvr_reconfig_analog_av:reconfig_analog_av|alt_xreconf_cif:inst_xreconf_cif|alt_xreconf_basic_acq:inst_basic_acq|readdata_for_user[0]~0 MLABCELL_X165_Y16_N27 32 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_analog:analog.sc_analog|alt_xcvr_reconfig_analog_av:reconfig_analog_av|alt_xreconf_uif:inst_xreconf_uif|Decoder0~0 LABCELL_X156_Y14_N18 4 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_analog:analog.sc_analog|alt_xcvr_reconfig_analog_av:reconfig_analog_av|alt_xreconf_uif:inst_xreconf_uif|Decoder0~1 LABCELL_X156_Y14_N12 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_analog:analog.sc_analog|alt_xcvr_reconfig_analog_av:reconfig_analog_av|alt_xreconf_uif:inst_xreconf_uif|Decoder0~2 LABCELL_X155_Y14_N36 4 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|always0~0 LABCELL_X181_Y28_N45 13 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|Equal12~0 LABCELL_X166_Y19_N30 21 Sync. load no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|always0~0 LABCELL_X166_Y19_N6 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|always1~0 LABCELL_X166_Y19_N48 16 Sync. load no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|always6~0 LABCELL_X163_Y19_N57 4 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|reco_addr[5]~1 LABCELL_X166_Y19_N54 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|reg_addr[5]~0 LABCELL_X166_Y19_N39 15 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|reg_rwdata[12]~1 MLABCELL_X167_Y18_N9 16 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|reg_rwdata[12]~2 MLABCELL_X167_Y19_N39 87 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|av_xrbasic_lif_csr:lif_csr|reg_write_incr~1 MLABCELL_X167_Y16_N27 2 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|csr_mux:pif_tbus_mux|out_narrow[0] LABCELL_X168_Y18_N30 2 Clock no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|csr_mux:pif_tbus_mux|out_narrow[1] MLABCELL_X167_Y17_N9 2 Clock no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|csr_mux:pif_tbus_mux|out_narrow[2] LABCELL_X168_Y18_N45 2 Clock no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|av_xrbasic_lif:lif[0].logical_if|csr_mux:pif_tbus_mux|out_narrow[3] LABCELL_X168_Y18_N3 2 Clock no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_basic:basic|av_xcvr_reconfig_basic:a5|reg_init[10]~0 LABCELL_X180_Y28_N54 13 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|Selector0~6 LABCELL_X164_Y14_N30 10 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|Selector21~0 LABCELL_X159_Y15_N18 13 Sync. load no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_arbiter_acq:mutex_inst|waitrequest~0 LABCELL_X163_Y16_N9 71 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd0_det|pd_xor~0 LABCELL_X166_Y14_N27 1 Clock no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd180_det|pd_xor~0 LABCELL_X168_Y17_N6 1 Clock no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd270_det|pd_xor~0 LABCELL_X166_Y18_N36 1 Clock no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|alt_cal_edge_detect:pd90_det|pd_xor~0 MLABCELL_X167_Y17_N48 1 Clock no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|cal_pd0_l[2]~1 LABCELL_X172_Y15_N42 4 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|cal_pd180_l[3]~1 LABCELL_X172_Y14_N42 4 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|cal_pd270_l[3]~1 LABCELL_X171_Y15_N54 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|cal_pd90_l[3]~1 LABCELL_X168_Y15_N24 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|counter[5]~0 MLABCELL_X170_Y14_N42 8 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|counter[5]~1 MLABCELL_X170_Y14_N54 8 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|dataout[3]~2 MLABCELL_X167_Y14_N27 16 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|pd_0[0]~1 LABCELL_X168_Y14_N30 10 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|pd_0_p[0]~1 MLABCELL_X170_Y14_N24 8 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|recal_counter[1]~0 LABCELL_X168_Y14_N45 2 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|state.DPRIO_WRITE FF_X166_Y14_N11 13 Async. clear no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_av:alt_cal_inst|state.SAMPLE_TB FF_X168_Y14_N17 22 Sync. load no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|alt_cal_remap_addr[1]~0 LABCELL_X159_Y15_N33 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|master_write_data[10]~12 LABCELL_X161_Y15_N18 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|master_write_data[10]~17 LABCELL_X163_Y16_N54 16 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|master_write_data[12]~16 LABCELL_X159_Y15_N15 2 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_reconfig_offset_cancellation:offset.sc_offset|alt_xcvr_reconfig_offset_cancellation_av:offset_cancellation_av|master_write_data[8]~7 LABCELL_X161_Y15_N33 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|alt_xcvr_resync:inst_reconfig_reset_sync|resync_chains[0].sync_r[1] FF_X182_Y68_N10 338 Async. clear yes Global Clock GCLK10 --
RxBlock:RxBlock_inst|Rx_4_reco:reco2_inst|alt_xcvr_reconfig:rx_4_reco_inst|ifsel_notdone_resync FF_X173_Y26_N29 409 Async. clear, Clock enable, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|SimpleSimplexLDC:ldc_inst|LDOWN_N_int FF_X2_Y50_N50 104 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|SimpleSimplexLDC:ldc_inst|dcfifo:fifo_inst|dcfifo_8ol1:auto_generated|cmpr_bp5:rdempty_eq_comp|aneb_result_wire[0] LABCELL_X4_Y48_N6 23 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|SimpleSimplexLDC:ldc_inst|dcfifo:fifo_inst|dcfifo_8ol1:auto_generated|valid_wrreq~0 MLABCELL_X8_Y48_N36 16 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|SimpleSimplexLDC:ldc_inst|status FF_X3_Y50_N38 7 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|SimpleSimplexLSC:lsc_inst|Equal0~6 MLABCELL_X3_Y47_N3 33 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|SimpleSimplexLSC:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_rdreq~0 LABCELL_X7_Y46_N45 22 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|SimpleSimplexLSC:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_wrreq~0 LABCELL_X4_Y46_N42 25 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|SimpleSimplexLSC:lsc_inst|writeout~0 LABCELL_X1_Y47_N36 34 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|Tx_2_1Gbps:xcvr_inst|altera_xcvr_custom:tx_2_1gbps_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|Decoder0~0 LABCELL_X11_Y49_N36 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|Tx_2_1Gbps:xcvr_inst|altera_xcvr_custom:tx_2_1gbps_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[0]~0 LABCELL_X11_Y49_N54 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|Tx_2_1Gbps:xcvr_inst|altera_xcvr_custom:tx_2_1gbps_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_pll.counter_pll_powerdown|Equal0~1 MLABCELL_X20_Y49_N48 11 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|Tx_2_1Gbps:xcvr_inst|altera_xcvr_custom:tx_2_1gbps_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[0].g_rx.counter_rx_digitalreset|reset_cond~2 LABCELL_X11_Y50_N0 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|Tx_2_1Gbps:xcvr_inst|altera_xcvr_custom:tx_2_1gbps_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~0 MLABCELL_X20_Y49_N6 11 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|Tx_2_1Gbps:xcvr_inst|altera_xcvr_custom:tx_2_1gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X0_Y38_N57 105 Clock yes Periphery Clock PCLK38 --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|Tx_2_1Gbps:xcvr_inst|altera_xcvr_custom:tx_2_1gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout HSSITXPLDPCSINTERFACE_X0_Y35_N57 124 Clock yes Periphery Clock PCLK39 --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|Tx_2_1Gbps:xcvr_inst|altera_xcvr_custom:tx_2_1gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always5~0 MLABCELL_X3_Y57_N12 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|rx_ready_wReset LABCELL_X4_Y49_N15 40 Async. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|user_logic_phy_controller:phy_controller_inst|Selector12~0 MLABCELL_X12_Y49_N6 2 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|user_logic_phy_controller:phy_controller_inst|phy_mgmt_fsm.waitrequest FF_X12_Y49_N5 14 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|Decoder0~0 MLABCELL_X8_Y38_N48 4 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[0]~4 MLABCELL_X6_Y38_N27 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[1]~3 MLABCELL_X6_Y38_N51 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[2]~2 MLABCELL_X6_Y38_N0 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[3]~1 MLABCELL_X6_Y38_N54 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_pll.counter_pll_powerdown|Equal0~1 LABCELL_X10_Y49_N24 10 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[0].g_rx.counter_rx_digitalreset|reset_cond~2 LABCELL_X9_Y50_N33 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[1].g_rx.counter_rx_digitalreset|reset_cond~2 LABCELL_X7_Y49_N6 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[2].g_rx.counter_rx_digitalreset|reset_cond~2 LABCELL_X10_Y50_N12 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[3].g_rx.counter_rx_digitalreset|reset_cond~2 MLABCELL_X15_Y49_N12 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~0 MLABCELL_X15_Y49_N15 11 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~1 LABCELL_X10_Y50_N9 11 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~2 MLABCELL_X8_Y49_N21 11 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~3 LABCELL_X9_Y50_N57 11 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X0_Y22_N57 163 Clock yes Periphery Clock PCLK45 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout HSSITXPLDPCSINTERFACE_X0_Y19_N57 119 Clock yes Periphery Clock PCLK44 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always5~0 MLABCELL_X3_Y57_N15 7 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X0_Y30_N57 131 Clock yes Periphery Clock PCLK41 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout HSSITXPLDPCSINTERFACE_X0_Y27_N57 123 Clock yes Periphery Clock PCLK57 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always5~0 MLABCELL_X6_Y55_N51 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X0_Y26_N57 132 Clock yes Periphery Clock PCLK42 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout HSSITXPLDPCSINTERFACE_X0_Y23_N57 124 Clock yes Periphery Clock PCLK43 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always5~0 LABCELL_X2_Y58_N27 6 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X0_Y34_N57 132 Clock yes Periphery Clock PCLK40 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout HSSITXPLDPCSINTERFACE_X0_Y31_N57 121 Clock yes Periphery Clock PCLK25 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always5~0 MLABCELL_X8_Y58_N36 7 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|LDOWN_N_int FF_X18_Y20_N11 141 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|a_graycounter_qo6:rdptr_g1p|_~1 LABCELL_X40_Y15_N42 20 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_wrreq~0 MLABCELL_X36_Y15_N45 21 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|status FF_X12_Y20_N26 6 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|LDOWN_N_int FF_X2_Y36_N38 139 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|a_graycounter_qo6:rdptr_g1p|_~1 LABCELL_X9_Y40_N42 20 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_wrreq~0 LABCELL_X4_Y40_N18 23 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|status FF_X2_Y36_N44 8 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|LDOWN_N_int FF_X4_Y29_N14 141 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|a_graycounter_qo6:rdptr_g1p|_~1 MLABCELL_X20_Y28_N24 20 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_wrreq~0 LABCELL_X7_Y28_N9 23 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|status FF_X4_Y29_N47 7 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|LDOWN_N_int FF_X4_Y43_N20 141 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|a_graycounter_qo6:rdptr_g1p|_~1 LABCELL_X11_Y42_N42 20 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_wrreq~0 LABCELL_X4_Y42_N51 22 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|status FF_X3_Y43_N38 7 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:0:lsc_inst|Equal0~6 LABCELL_X10_Y4_N21 33 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:0:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_rdreq~0 LABCELL_X2_Y4_N48 18 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:0:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_wrreq~1 LABCELL_X4_Y2_N0 23 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:0:lsc_inst|writeout~0 MLABCELL_X3_Y6_N27 34 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:1:lsc_inst|Equal0~6 LABCELL_X4_Y35_N54 33 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:1:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_rdreq~0 MLABCELL_X8_Y37_N48 21 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:1:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_wrreq~1 LABCELL_X9_Y36_N33 23 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:1:lsc_inst|writeout~0 LABCELL_X9_Y37_N36 34 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:2:lsc_inst|Equal0~6 LABCELL_X11_Y24_N42 33 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:2:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_rdreq~0 MLABCELL_X8_Y27_N39 21 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:2:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_wrreq~1 MLABCELL_X12_Y27_N42 22 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:2:lsc_inst|writeout~0 MLABCELL_X3_Y27_N54 34 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:3:lsc_inst|Equal0~6 LABCELL_X4_Y35_N12 34 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:3:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_rdreq~0 LABCELL_X9_Y35_N30 19 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:3:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_wrreq~1 MLABCELL_X8_Y34_N0 21 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|SimpleSimplexLSC:\gen_slink:3:lsc_inst|writeout~0 LABCELL_X9_Y35_N12 34 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|rx_ready_wReset LABCELL_X16_Y49_N0 168 Async. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|tx_ready_wReset LABCELL_X17_Y6_N15 8 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|user_logic_phy_controller:phy_controller_inst|Selector10~0 LABCELL_X9_Y38_N48 2 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|user_logic_phy_controller:phy_controller_inst|phy_mgmt_fsm.waitrequest FF_X8_Y38_N32 15 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|Decoder0~0 LABCELL_X163_Y17_N18 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[0]~4 LABCELL_X168_Y17_N21 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[1]~3 LABCELL_X168_Y17_N42 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[2]~2 LABCELL_X168_Y17_N33 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[3]~1 LABCELL_X168_Y17_N54 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_pll.counter_pll_powerdown|Equal0~1 LABCELL_X181_Y27_N21 11 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[0].g_rx.counter_rx_digitalreset|reset_cond~2 LABCELL_X181_Y31_N0 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[1].g_rx.counter_rx_digitalreset|reset_cond~2 LABCELL_X180_Y27_N54 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[2].g_rx.counter_rx_digitalreset|reset_cond~2 MLABCELL_X179_Y31_N24 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[3].g_rx.counter_rx_digitalreset|reset_cond~2 LABCELL_X180_Y27_N42 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~0 LABCELL_X181_Y27_N12 11 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~1 LABCELL_X181_Y31_N24 11 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~2 LABCELL_X181_Y27_N9 11 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~3 LABCELL_X181_Y31_N9 11 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X183_Y22_N57 161 Clock yes Periphery Clock PCLK128 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout HSSITXPLDPCSINTERFACE_X183_Y19_N57 121 Clock yes Periphery Clock PCLK129 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always5~0 LABCELL_X172_Y26_N21 6 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X183_Y26_N57 129 Clock yes Periphery Clock PCLK131 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout HSSITXPLDPCSINTERFACE_X183_Y23_N57 122 Clock yes Periphery Clock PCLK130 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always5~0 LABCELL_X177_Y28_N18 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X183_Y30_N57 136 Clock yes Periphery Clock PCLK133 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout HSSITXPLDPCSINTERFACE_X183_Y27_N57 120 Clock yes Periphery Clock PCLK132 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always5~0 LABCELL_X175_Y28_N27 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X183_Y34_N57 133 Clock yes Periphery Clock PCLK134 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout HSSITXPLDPCSINTERFACE_X183_Y31_N57 119 Clock yes Periphery Clock PCLK135 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always5~0 LABCELL_X177_Y27_N42 8 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|LDOWN_N_int FF_X146_Y20_N44 138 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|a_graycounter_qo6:rdptr_g1p|_~1 LABCELL_X142_Y21_N3 20 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_wrreq~0 LABCELL_X145_Y19_N42 22 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|status FF_X164_Y20_N53 7 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|LDOWN_N_int FF_X179_Y30_N56 137 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_rdreq~1 LABCELL_X177_Y30_N15 20 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_wrreq~0 LABCELL_X175_Y30_N9 19 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|status FF_X176_Y29_N8 8 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|LDOWN_N_int FF_X179_Y37_N26 146 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_rdreq~1 LABCELL_X177_Y40_N45 20 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_wrreq~0 LABCELL_X175_Y40_N48 25 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|status FF_X179_Y37_N23 6 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|LDOWN_N_int FF_X181_Y55_N8 143 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_rdreq~1 LABCELL_X177_Y61_N57 20 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_wrreq~0 LABCELL_X180_Y60_N45 21 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|status FF_X180_Y55_N50 6 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:0:lsc_inst|Equal0~6 LABCELL_X173_Y11_N42 33 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:0:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_rdreq~0 LABCELL_X166_Y13_N3 19 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:0:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_wrreq~1 LABCELL_X166_Y12_N21 24 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:0:lsc_inst|writeout~0 LABCELL_X172_Y13_N33 34 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:1:lsc_inst|Equal0~6 LABCELL_X136_Y19_N15 33 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:1:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_rdreq~0 LABCELL_X145_Y18_N21 18 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:1:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_wrreq~1 LABCELL_X136_Y18_N39 20 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:1:lsc_inst|writeout~0 LABCELL_X149_Y18_N33 34 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:2:lsc_inst|Equal0~6 LABCELL_X181_Y48_N42 33 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:2:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_rdreq~0 LABCELL_X181_Y47_N9 18 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:2:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_wrreq~1 LABCELL_X173_Y47_N24 22 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:2:lsc_inst|writeout~0 LABCELL_X182_Y43_N42 34 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:3:lsc_inst|Equal0~6 LABCELL_X172_Y45_N51 33 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:3:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_rdreq~0 LABCELL_X175_Y45_N48 17 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:3:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_wrreq~1 MLABCELL_X174_Y46_N36 21 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|SimpleSimplexLSC:\gen_slink:3:lsc_inst|writeout~0 LABCELL_X182_Y45_N12 34 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|rx_ready_wReset MLABCELL_X179_Y28_N33 167 Async. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|tx_ready_wReset LABCELL_X172_Y13_N39 8 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|user_logic_phy_controller:phy_controller_inst|Selector10~0 LABCELL_X164_Y17_N48 2 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|user_logic_phy_controller:phy_controller_inst|phy_mgmt_fsm.waitrequest FF_X163_Y17_N8 15 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|Decoder0~0 MLABCELL_X176_Y35_N12 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[0]~4 LABCELL_X180_Y35_N18 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[1]~3 MLABCELL_X174_Y35_N12 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[2]~2 MLABCELL_X174_Y35_N33 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[3]~1 LABCELL_X180_Y35_N21 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_pll.counter_pll_powerdown|Equal0~1 LABCELL_X180_Y65_N27 10 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[0].g_rx.counter_rx_digitalreset|reset_cond~2 MLABCELL_X176_Y38_N45 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[1].g_rx.counter_rx_digitalreset|reset_cond~2 MLABCELL_X179_Y34_N33 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[2].g_rx.counter_rx_digitalreset|reset_cond~2 LABCELL_X181_Y34_N42 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[3].g_rx.counter_rx_digitalreset|reset_cond~2 LABCELL_X181_Y35_N42 14 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~0 LABCELL_X180_Y35_N48 13 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~1 LABCELL_X180_Y34_N27 11 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~2 MLABCELL_X179_Y34_N30 11 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~3 LABCELL_X175_Y38_N54 11 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X183_Y46_N57 172 Clock yes Periphery Clock PCLK140 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout HSSITXPLDPCSINTERFACE_X183_Y43_N57 120 Clock yes Periphery Clock PCLK141 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always5~0 MLABCELL_X176_Y27_N24 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X183_Y38_N57 141 Clock yes Periphery Clock PCLK137 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout HSSITXPLDPCSINTERFACE_X183_Y35_N57 120 Clock yes Periphery Clock PCLK136 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always5~0 MLABCELL_X170_Y28_N48 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X183_Y42_N57 133 Clock yes Periphery Clock PCLK139 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout HSSITXPLDPCSINTERFACE_X183_Y39_N57 123 Clock yes Regional Clock RCLK79 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always5~0 MLABCELL_X174_Y27_N45 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X183_Y50_N57 83 Clock yes Periphery Clock PCLK143 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout HSSITXPLDPCSINTERFACE_X183_Y47_N57 118 Clock yes Periphery Clock PCLK142 --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always5~0 LABCELL_X173_Y28_N48 5 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|LDOWN_N_int FF_X180_Y64_N59 147 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_rdreq~1 LABCELL_X175_Y63_N30 20 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_wrreq~0 LABCELL_X180_Y62_N39 24 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|status FF_X181_Y65_N32 9 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|LDOWN_N_int FF_X176_Y53_N26 150 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_rdreq~1 LABCELL_X171_Y53_N33 20 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_wrreq~0 MLABCELL_X174_Y53_N3 24 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|status FF_X180_Y52_N41 7 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|LDOWN_N_int FF_X174_Y60_N8 142 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_rdreq~1 LABCELL_X163_Y62_N39 20 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_wrreq~0 LABCELL_X173_Y62_N33 24 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|status FF_X179_Y59_N53 7 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|LDOWN_N_int FF_X179_Y72_N53 43 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|dcfifo:fifo_inst|dcfifo_7sl1:auto_generated|valid_wrreq~0 LABCELL_X145_Y72_N48 23 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|status FF_X180_Y71_N41 7 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:0:lsc_inst|Equal0~6 LABCELL_X173_Y56_N24 33 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:0:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_rdreq~0 LABCELL_X173_Y56_N51 19 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:0:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_wrreq~1 LABCELL_X177_Y57_N15 24 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:0:lsc_inst|writeout~0 LABCELL_X182_Y60_N6 34 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:1:lsc_inst|Equal0~6 LABCELL_X177_Y39_N33 33 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:1:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_rdreq~0 LABCELL_X172_Y36_N33 20 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:1:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_wrreq~1 LABCELL_X175_Y36_N21 21 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:1:lsc_inst|writeout~0 LABCELL_X173_Y36_N18 34 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:2:lsc_inst|Equal0~6 LABCELL_X177_Y5_N48 33 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:2:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_rdreq~0 LABCELL_X181_Y4_N57 20 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:2:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_wrreq~1 MLABCELL_X176_Y4_N27 25 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:2:lsc_inst|writeout~0 LABCELL_X181_Y4_N54 34 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:3:lsc_inst|Equal0~6 LABCELL_X181_Y70_N6 33 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:3:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_rdreq~0 LABCELL_X181_Y69_N42 17 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:3:lsc_inst|dcfifo:fifo_inst|dcfifo_20m1:auto_generated|valid_wrreq~1 MLABCELL_X174_Y69_N54 25 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|SimpleSimplexLSC:\gen_slink:3:lsc_inst|writeout~0 LABCELL_X181_Y73_N30 34 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|rx_ready_wReset MLABCELL_X170_Y65_N54 169 Async. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|tx_ready_wReset MLABCELL_X176_Y56_N48 8 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|user_logic_phy_controller:phy_controller_inst|Selector10~0 MLABCELL_X176_Y35_N42 2 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|user_logic_phy_controller:phy_controller_inst|phy_mgmt_fsm.waitrequest FF_X176_Y35_N32 16 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|Decoder0~0 LABCELL_X2_Y45_N30 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[0]~4 MLABCELL_X6_Y61_N18 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[1]~3 MLABCELL_X6_Y61_N0 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[2]~2 MLABCELL_X6_Y61_N54 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|alt_xcvr_csr_pcs8g:csr_pcs|reg_rx_bitreversalenable[3]~1 MLABCELL_X6_Y61_N51 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[0].g_rx.counter_rx_digitalreset|reset_cond~2 LABCELL_X10_Y52_N12 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[1].g_rx.counter_rx_digitalreset|reset_cond~2 LABCELL_X7_Y52_N6 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[2].g_rx.counter_rx_digitalreset|reset_cond~2 LABCELL_X4_Y61_N39 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|alt_xcvr_reset_counter:g_rx.g_rx[3].g_rx.counter_rx_digitalreset|reset_cond~2 LABCELL_X2_Y52_N30 12 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~0 LABCELL_X2_Y52_N0 11 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~1 MLABCELL_X3_Y61_N15 11 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~2 LABCELL_X9_Y52_N48 11 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|altera_xcvr_reset_control:gen_embedded_reset.reset_controller|comb~3 LABCELL_X10_Y52_N21 11 Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X0_Y58_N57 168 Clock yes Periphery Clock PCLK18 --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always4~1 MLABCELL_X6_Y60_N24 4 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X0_Y46_N57 137 Clock yes Periphery Clock PCLK23 --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always4~0 MLABCELL_X8_Y59_N21 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X0_Y50_N57 138 Clock yes Periphery Clock PCLK20 --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always4~0 LABCELL_X2_Y60_N39 3 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout HSSIRXPLDPCSINTERFACE_X0_Y14_N57 137 Clock yes Regional Clock RCLK63 --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|av_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|always4~0 LABCELL_X4_Y59_N54 4 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|LDOWN_N_int FF_X1_Y85_N32 183 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|dcfifo:fifo_inst|dcfifo_gsl1:auto_generated|a_graycounter_ro6:rdptr_g1p|_~0 LABCELL_X4_Y87_N54 27 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|dcfifo:fifo_inst|dcfifo_gsl1:auto_generated|valid_wrreq~0 LABCELL_X2_Y85_N54 24 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:0:ldc_inst|status FF_X3_Y85_N50 6 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|LDOWN_N_int FF_X2_Y64_N44 184 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|dcfifo:fifo_inst|dcfifo_gsl1:auto_generated|a_graycounter_ro6:rdptr_g1p|_~0 LABCELL_X7_Y62_N27 27 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|dcfifo:fifo_inst|dcfifo_gsl1:auto_generated|valid_wrreq~0 MLABCELL_X6_Y63_N54 23 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:1:ldc_inst|status FF_X2_Y64_N26 6 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|LDOWN_N_int FF_X2_Y71_N2 185 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|dcfifo:fifo_inst|dcfifo_gsl1:auto_generated|a_graycounter_ro6:rdptr_g1p|_~0 MLABCELL_X15_Y70_N9 27 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|dcfifo:fifo_inst|dcfifo_gsl1:auto_generated|valid_wrreq~0 LABCELL_X4_Y70_N0 26 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:2:ldc_inst|status FF_X2_Y71_N8 6 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|LDOWN_N_int FF_X20_Y8_N44 184 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|dcfifo:fifo_inst|dcfifo_gsl1:auto_generated|a_graycounter_ro6:rdptr_g1p|_~0 LABCELL_X17_Y11_N21 27 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|dcfifo:fifo_inst|dcfifo_gsl1:auto_generated|valid_wrreq~0 LABCELL_X23_Y11_N6 23 Clock enable, Write enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:\gen_slink:3:ldc_inst|status FF_X2_Y8_N38 6 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|rx_ready_wReset MLABCELL_X6_Y52_N48 164 Async. clear no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|user_logic_phy_controller:phy_controller_inst|Selector10~0 LABCELL_X4_Y41_N27 2 Clock enable no -- -- --
RxBlock:RxBlock_inst|Xcvr_Road:road_inst|user_logic_phy_controller:phy_controller_inst|phy_mgmt_fsm.waitrequest FF_X3_Y45_N5 14 Clock enable no -- -- --
RxBlock:RxBlock_inst|reset_block:\gen_reset_board:reset1_inst|consolidated_reset MLABCELL_X3_Y45_N48 410 Async. clear, Sync. clear no -- -- --
RxBlock:RxBlock_inst|reset_block:\gen_reset_board:reset2_inst|consolidated_reset MLABCELL_X170_Y65_N48 370 Async. clear no -- -- --
RxBlock:RxBlock_inst|user_logic_reconfig_controller_rslb:reconfig2_controller_inst|proc_sync~0 MLABCELL_X154_Y14_N21 21 Clock enable no -- -- --
RxBlock:RxBlock_inst|user_logic_reconfig_controller_rslb:reconfig2_controller_inst|reconfig_mgmt_address[0]~1 LABCELL_X155_Y14_N48 2 Clock enable no -- -- --
RxBlock:RxBlock_inst|user_logic_reconfig_controller_rslb:reconfig2_controller_inst|reconfig_mgmt_address[3]~2 LABCELL_X155_Y14_N42 2 Clock enable no -- -- --
RxBlock:RxBlock_inst|user_logic_reconfig_controller_rslb_1xcvr:reconfig1_controller_inst|channel[2]~0 LABCELL_X16_Y49_N6 9 Clock enable no -- -- --
RxBlock:RxBlock_inst|user_logic_reconfig_controller_rslb_1xcvr:reconfig1_controller_inst|reconfig_mgmt_address[3]~2 LABCELL_X18_Y49_N0 2 Clock enable no -- -- --
RxBlock:RxBlock_inst|user_logic_reconfig_controller_rslb_1xcvr:reconfig1_controller_inst|reconfig_mgmt_fsm~10 LABCELL_X16_Y49_N9 4 Clock enable no -- -- --
RxBlock:RxBlock_inst|user_logic_reconfig_controller_rslb_1xcvr:reconfig1_controller_inst|reconfig_mgmt_fsm~9 LABCELL_X16_Y49_N48 2 Clock enable no -- -- --
TFBlock:inst2|TFProcessVMEInputConsts:INPUTPROCESSORCONSTS|fifo_32_to_64:VMECONSTSBUFFER|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_o6l1:auto_generated|_~0 LABCELL_X91_Y38_N9 4 Clock enable no -- -- --
TFBlock:inst2|TFProcessVMEInputConsts:INPUTPROCESSORCONSTS|fifo_32_to_64:VMECONSTSBUFFER|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_o6l1:auto_generated|altsyncram_rv61:fifo_ram|q_b[0] M10K_X96_Y38_N0 78 Sync. clear no -- -- --
TFBlock:inst2|TFProcessVMEInputConsts:INPUTPROCESSORCONSTS|fifo_32_to_64:VMECONSTSBUFFER|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_o6l1:auto_generated|valid_rdreq~0 LABCELL_X94_Y38_N36 16 Clock enable no -- -- --
TFBlock:inst2|TFProcessVMEInputConsts:INPUTPROCESSORCONSTS|fifo_32_to_64:VMECONSTSBUFFER|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_o6l1:auto_generated|valid_wrreq~0 LABCELL_X91_Y38_N30 17 Clock enable, Write enable no -- -- --
TFBlock:inst2|TFProcessVMEOutput:OUTPUTPROCESSOR|fifo_32_to_32_clockinterface:SLOWCONSTSFIFO|dcfifo:dcfifo_component|dcfifo_g6l1:auto_generated|int_rdempty LABCELL_X40_Y54_N9 16 Clock enable no -- -- --
TFBlock:inst2|TFProcessVMEOutput:OUTPUTPROCESSOR|fifo_32_to_32_clockinterface:SLOWCONSTSFIFO|dcfifo:dcfifo_component|dcfifo_g6l1:auto_generated|valid_wrreq~0 LABCELL_X48_Y54_N30 20 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFConstantsReadCheck:READCHECKER|Selector2~3 LABCELL_X55_Y54_N45 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFConstantsReadCheck:READCHECKER|address_cntclr FF_X55_Y54_N14 9 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFConstantsReadCheck:READCHECKER|loadingconsts_cntclr FF_X52_Y54_N52 3 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFConstantsReadCheck:READCHECKER|lpm_mux_76x32:MUX|lpm_mux:LPM_MUX_component|mux_bee:auto_generated|sel_dffe5a[4] FF_X73_Y54_N32 64 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFConstantsReadCheck:READCHECKER|lpm_mux_76x32:MUX|lpm_mux:LPM_MUX_component|mux_bee:auto_generated|sel_dffe6a[5] FF_X58_Y54_N20 32 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFConstantsReadCheck:READCHECKER|state.loadingconsts FF_X57_Y54_N53 1563 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:0:ACONSTMEMSTITCHED|large_wren LABCELL_X119_Y48_N54 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:0:ACONSTMEMSTITCHED|small_wren LABCELL_X119_Y48_N27 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:10:ACONSTMEMSTITCHED|large_wren LABCELL_X147_Y56_N45 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:10:ACONSTMEMSTITCHED|small_wren LABCELL_X147_Y56_N51 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:11:ACONSTMEMSTITCHED|large_wren MLABCELL_X97_Y39_N54 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:11:ACONSTMEMSTITCHED|small_wren MLABCELL_X97_Y39_N36 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:12:ACONSTMEMSTITCHED|large_wren LABCELL_X112_Y40_N54 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:12:ACONSTMEMSTITCHED|small_wren LABCELL_X112_Y40_N39 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:13:ACONSTMEMSTITCHED|large_wren LABCELL_X93_Y42_N51 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:13:ACONSTMEMSTITCHED|small_wren LABCELL_X93_Y42_N54 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:14:ACONSTMEMSTITCHED|large_wren LABCELL_X91_Y44_N27 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:14:ACONSTMEMSTITCHED|small_wren LABCELL_X91_Y44_N9 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:15:ACONSTMEMSTITCHED|large_wren MLABCELL_X90_Y40_N54 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:15:ACONSTMEMSTITCHED|small_wren MLABCELL_X90_Y40_N39 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:16:ACONSTMEMSTITCHED|large_wren LABCELL_X91_Y44_N33 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:16:ACONSTMEMSTITCHED|small_wren LABCELL_X91_Y44_N30 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:17:ACONSTMEMSTITCHED|large_wren LABCELL_X135_Y44_N6 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:17:ACONSTMEMSTITCHED|small_wren LABCELL_X135_Y44_N24 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:18:ACONSTMEMSTITCHED|large_wren LABCELL_X140_Y48_N33 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:18:ACONSTMEMSTITCHED|small_wren LABCELL_X140_Y48_N24 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:19:ACONSTMEMSTITCHED|large_wren LABCELL_X139_Y48_N33 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:19:ACONSTMEMSTITCHED|small_wren LABCELL_X139_Y48_N0 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:1:ACONSTMEMSTITCHED|large_wren MLABCELL_X141_Y52_N39 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:1:ACONSTMEMSTITCHED|small_wren MLABCELL_X141_Y52_N6 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:20:ACONSTMEMSTITCHED|large_wren MLABCELL_X102_Y44_N57 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:20:ACONSTMEMSTITCHED|small_wren MLABCELL_X102_Y44_N0 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:21:ACONSTMEMSTITCHED|large_wren MLABCELL_X102_Y44_N33 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:21:ACONSTMEMSTITCHED|small_wren MLABCELL_X102_Y44_N24 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:22:ACONSTMEMSTITCHED|large_wren LABCELL_X69_Y42_N57 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:22:ACONSTMEMSTITCHED|small_wren LABCELL_X69_Y42_N24 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:23:ACONSTMEMSTITCHED|large_wren MLABCELL_X68_Y40_N51 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:23:ACONSTMEMSTITCHED|small_wren MLABCELL_X68_Y40_N42 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:24:ACONSTMEMSTITCHED|large_wren LABCELL_X57_Y40_N3 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:24:ACONSTMEMSTITCHED|small_wren LABCELL_X57_Y40_N18 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:25:ACONSTMEMSTITCHED|large_wren LABCELL_X65_Y48_N0 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:25:ACONSTMEMSTITCHED|small_wren LABCELL_X65_Y48_N57 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:26:ACONSTMEMSTITCHED|large_wren LABCELL_X58_Y44_N54 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:26:ACONSTMEMSTITCHED|small_wren LABCELL_X58_Y44_N24 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:27:ACONSTMEMSTITCHED|large_wren LABCELL_X58_Y44_N21 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:27:ACONSTMEMSTITCHED|small_wren LABCELL_X58_Y44_N48 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:28:ACONSTMEMSTITCHED|large_wren LABCELL_X91_Y48_N6 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:28:ACONSTMEMSTITCHED|small_wren LABCELL_X91_Y48_N36 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:29:ACONSTMEMSTITCHED|large_wren LABCELL_X91_Y48_N57 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:29:ACONSTMEMSTITCHED|small_wren LABCELL_X91_Y48_N24 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:2:ACONSTMEMSTITCHED|large_wren LABCELL_X117_Y48_N18 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:2:ACONSTMEMSTITCHED|small_wren LABCELL_X117_Y48_N48 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:30:ACONSTMEMSTITCHED|large_wren LABCELL_X94_Y52_N21 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:30:ACONSTMEMSTITCHED|small_wren LABCELL_X94_Y52_N51 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:31:ACONSTMEMSTITCHED|large_wren MLABCELL_X102_Y56_N54 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:31:ACONSTMEMSTITCHED|small_wren MLABCELL_X102_Y56_N24 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:32:ACONSTMEMSTITCHED|large_wren LABCELL_X71_Y55_N9 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:32:ACONSTMEMSTITCHED|small_wren LABCELL_X71_Y55_N39 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:33:ACONSTMEMSTITCHED|large_wren LABCELL_X71_Y55_N54 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:33:ACONSTMEMSTITCHED|small_wren LABCELL_X71_Y55_N12 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:34:ACONSTMEMSTITCHED|large_wren MLABCELL_X68_Y56_N39 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:34:ACONSTMEMSTITCHED|small_wren MLABCELL_X68_Y56_N30 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:35:ACONSTMEMSTITCHED|large_wren MLABCELL_X68_Y56_N45 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:35:ACONSTMEMSTITCHED|small_wren MLABCELL_X68_Y56_N57 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:36:ACONSTMEMSTITCHED|large_wren MLABCELL_X76_Y56_N18 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:36:ACONSTMEMSTITCHED|small_wren MLABCELL_X76_Y56_N51 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:37:ACONSTMEMSTITCHED|large_wren MLABCELL_X76_Y56_N30 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:37:ACONSTMEMSTITCHED|small_wren MLABCELL_X76_Y56_N0 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:38:ACONSTMEMSTITCHED|large_wren LABCELL_X114_Y60_N51 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:38:ACONSTMEMSTITCHED|small_wren LABCELL_X114_Y60_N42 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:39:ACONSTMEMSTITCHED|large_wren LABCELL_X114_Y60_N39 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:39:ACONSTMEMSTITCHED|small_wren LABCELL_X114_Y60_N6 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:3:ACONSTMEMSTITCHED|large_wren LABCELL_X117_Y48_N45 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:3:ACONSTMEMSTITCHED|small_wren LABCELL_X117_Y48_N24 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:40:ACONSTMEMSTITCHED|large_wren LABCELL_X110_Y64_N9 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:40:ACONSTMEMSTITCHED|small_wren LABCELL_X110_Y64_N0 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:41:ACONSTMEMSTITCHED|large_wren LABCELL_X110_Y64_N45 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:41:ACONSTMEMSTITCHED|small_wren LABCELL_X110_Y64_N51 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:42:ACONSTMEMSTITCHED|large_wren MLABCELL_X76_Y56_N33 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:42:ACONSTMEMSTITCHED|small_wren MLABCELL_X76_Y56_N39 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:43:ACONSTMEMSTITCHED|large_wren MLABCELL_X76_Y54_N27 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:43:ACONSTMEMSTITCHED|small_wren MLABCELL_X76_Y54_N54 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:44:ACONSTMEMSTITCHED|large_wren LABCELL_X65_Y48_N39 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:44:ACONSTMEMSTITCHED|small_wren LABCELL_X65_Y48_N30 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:45:ACONSTMEMSTITCHED|large_wren LABCELL_X65_Y48_N51 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:45:ACONSTMEMSTITCHED|small_wren LABCELL_X65_Y48_N18 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:46:ACONSTMEMSTITCHED|large_wren LABCELL_X57_Y48_N18 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:46:ACONSTMEMSTITCHED|small_wren LABCELL_X57_Y48_N12 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:47:ACONSTMEMSTITCHED|large_wren LABCELL_X57_Y48_N33 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:47:ACONSTMEMSTITCHED|small_wren LABCELL_X57_Y48_N0 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:48:ACONSTMEMSTITCHED|large_wren LABCELL_X61_Y52_N24 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:48:ACONSTMEMSTITCHED|small_wren LABCELL_X61_Y52_N57 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:49:ACONSTMEMSTITCHED|large_wren LABCELL_X103_Y54_N27 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:49:ACONSTMEMSTITCHED|small_wren LABCELL_X103_Y54_N54 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:4:ACONSTMEMSTITCHED|large_wren LABCELL_X137_Y52_N30 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:4:ACONSTMEMSTITCHED|small_wren LABCELL_X137_Y52_N24 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:50:ACONSTMEMSTITCHED|large_wren LABCELL_X116_Y55_N9 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:50:ACONSTMEMSTITCHED|small_wren LABCELL_X116_Y55_N39 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:51:ACONSTMEMSTITCHED|large_wren MLABCELL_X76_Y56_N54 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:51:ACONSTMEMSTITCHED|small_wren MLABCELL_X76_Y56_N15 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:52:ACONSTMEMSTITCHED|large_wren LABCELL_X114_Y60_N12 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:52:ACONSTMEMSTITCHED|small_wren LABCELL_X114_Y60_N54 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:53:ACONSTMEMSTITCHED|large_wren MLABCELL_X52_Y59_N42 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:53:ACONSTMEMSTITCHED|small_wren MLABCELL_X52_Y59_N48 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:54:ACONSTMEMSTITCHED|large_wren LABCELL_X47_Y45_N42 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:54:ACONSTMEMSTITCHED|small_wren LABCELL_X47_Y45_N0 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:55:ACONSTMEMSTITCHED|large_wren LABCELL_X47_Y45_N21 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:55:ACONSTMEMSTITCHED|small_wren LABCELL_X47_Y45_N36 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:56:ACONSTMEMSTITCHED|large_wren LABCELL_X50_Y44_N57 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:56:ACONSTMEMSTITCHED|small_wren LABCELL_X50_Y44_N12 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:57:ACONSTMEMSTITCHED|large_wren LABCELL_X50_Y44_N54 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:57:ACONSTMEMSTITCHED|small_wren LABCELL_X50_Y44_N51 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:58:ACONSTMEMSTITCHED|large_wren LABCELL_X50_Y44_N24 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:58:ACONSTMEMSTITCHED|small_wren LABCELL_X50_Y47_N18 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:59:ACONSTMEMSTITCHED|large_wren LABCELL_X50_Y40_N48 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:59:ACONSTMEMSTITCHED|small_wren LABCELL_X50_Y40_N24 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:5:ACONSTMEMSTITCHED|large_wren LABCELL_X134_Y58_N36 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:5:ACONSTMEMSTITCHED|small_wren LABCELL_X134_Y58_N9 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:60:ACONSTMEMSTITCHED|large_wren LABCELL_X66_Y64_N18 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:60:ACONSTMEMSTITCHED|small_wren LABCELL_X66_Y64_N24 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:61:ACONSTMEMSTITCHED|large_wren LABCELL_X72_Y61_N51 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:61:ACONSTMEMSTITCHED|small_wren LABCELL_X72_Y61_N54 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:62:ACONSTMEMSTITCHED|large_wren LABCELL_X79_Y62_N18 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:62:ACONSTMEMSTITCHED|small_wren LABCELL_X79_Y62_N24 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:63:ACONSTMEMSTITCHED|large_wren LABCELL_X79_Y62_N33 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:63:ACONSTMEMSTITCHED|small_wren LABCELL_X79_Y62_N48 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:64:ACONSTMEMSTITCHED|large_wren LABCELL_X53_Y56_N48 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:64:ACONSTMEMSTITCHED|small_wren LABCELL_X53_Y56_N54 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:65:ACONSTMEMSTITCHED|large_wren LABCELL_X50_Y54_N30 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:65:ACONSTMEMSTITCHED|small_wren LABCELL_X50_Y54_N51 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:66:ACONSTMEMSTITCHED|large_wren LABCELL_X39_Y53_N57 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:66:ACONSTMEMSTITCHED|small_wren LABCELL_X39_Y53_N24 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:67:ACONSTMEMSTITCHED|large_wren LABCELL_X37_Y56_N45 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:67:ACONSTMEMSTITCHED|small_wren LABCELL_X37_Y56_N36 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:68:ACONSTMEMSTITCHED|large_wren LABCELL_X61_Y52_N51 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:68:ACONSTMEMSTITCHED|small_wren LABCELL_X61_Y52_N48 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:69:ACONSTMEMSTITCHED|large_wren LABCELL_X50_Y54_N54 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:69:ACONSTMEMSTITCHED|small_wren LABCELL_X50_Y54_N39 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:6:ACONSTMEMSTITCHED|large_wren LABCELL_X149_Y60_N33 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:6:ACONSTMEMSTITCHED|small_wren LABCELL_X149_Y60_N48 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:70:ACONSTMEMSTITCHED|large_wren MLABCELL_X36_Y56_N45 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:70:ACONSTMEMSTITCHED|small_wren MLABCELL_X36_Y56_N36 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:71:ACONSTMEMSTITCHED|large_wren MLABCELL_X36_Y56_N9 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:71:ACONSTMEMSTITCHED|small_wren MLABCELL_X36_Y56_N0 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:72:ACONSTMEMSTITCHED|large_wren MLABCELL_X36_Y56_N54 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:72:ACONSTMEMSTITCHED|small_wren MLABCELL_X36_Y56_N12 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:73:ACONSTMEMSTITCHED|large_wren MLABCELL_X36_Y58_N9 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:73:ACONSTMEMSTITCHED|small_wren MLABCELL_X36_Y58_N12 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:74:ACONSTMEMSTITCHED|large_wren LABCELL_X56_Y60_N42 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:74:ACONSTMEMSTITCHED|small_wren LABCELL_X56_Y60_N48 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:75:ACONSTMEMSTITCHED|large_wren MLABCELL_X52_Y58_N21 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:75:ACONSTMEMSTITCHED|small_wren MLABCELL_X52_Y58_N54 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:76:ACONSTMEMSTITCHED|large_wren LABCELL_X56_Y50_N9 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:76:ACONSTMEMSTITCHED|small_wren LABCELL_X56_Y50_N24 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:77:ACONSTMEMSTITCHED|large_wren LABCELL_X55_Y54_N30 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:77:ACONSTMEMSTITCHED|small_wren LABCELL_X55_Y54_N48 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:7:ACONSTMEMSTITCHED|large_wren LABCELL_X149_Y60_N9 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:7:ACONSTMEMSTITCHED|small_wren LABCELL_X149_Y60_N36 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:8:ACONSTMEMSTITCHED|large_wren LABCELL_X145_Y62_N42 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:8:ACONSTMEMSTITCHED|small_wren LABCELL_X145_Y62_N48 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:9:ACONSTMEMSTITCHED|large_wren LABCELL_X145_Y62_N57 4 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|TFConstantsMemory:CONSTSMEM|TFStitchedDualportRAM:\gen_CONSTMEMRAMS:9:ACONSTMEMSTITCHED|small_wren LABCELL_X145_Y62_N24 1 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|controller~1 LABCELL_X106_Y66_N42 21 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|pixlayermap[0] FF_X113_Y34_N8 486 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|pixlayermap[2] FF_X113_Y34_N29 486 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|sct_const_0_7~0 MLABCELL_X113_Y44_N9 108 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|sct_const_1_8~0 MLABCELL_X113_Y44_N39 108 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|sctlayermap[0] FF_X135_Y42_N17 235 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFConstantsMemoryBlock:CONSTANTSMEM|TFConstantsMemoryMUX:CONSTMEMMUX|sctlayermap[4] FF_X142_Y44_N41 109 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|internal_reset LABCELL_X79_Y26_N54 58 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|lpm_counter:track_counter|cntr_qfi:auto_generated|_~0 LABCELL_X126_Y25_N24 32 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|scfifo:tf_eventtrailerfifo_inst|scfifo_blb1:auto_generated|a_dpfifo_d981:dpfifo|cntr_gra:rd_ptr_msb|_~0 LABCELL_X77_Y28_N24 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|scfifo:tf_eventtrailerfifo_inst|scfifo_blb1:auto_generated|a_dpfifo_d981:dpfifo|cntr_hra:wr_ptr|_~0 LABCELL_X77_Y28_N48 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|scfifo:tf_eventtrailerfifo_inst|scfifo_blb1:auto_generated|a_dpfifo_d981:dpfifo|cntr_tr6:usedw_counter|_~0 LABCELL_X77_Y28_N45 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|scfifo:tf_eventtrailerfifo_inst|scfifo_blb1:auto_generated|a_dpfifo_d981:dpfifo|rd_ptr_lsb~1 LABCELL_X77_Y28_N33 1 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|scfifo:tf_eventtrailerfifo_inst|scfifo_blb1:auto_generated|a_dpfifo_d981:dpfifo|valid_rreq LABCELL_X77_Y28_N12 5 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|scfifo:tf_eventtrailerfifo_inst|scfifo_blb1:auto_generated|a_dpfifo_d981:dpfifo|valid_wreq LABCELL_X77_Y28_N36 7 Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|scfifo:tfeventheaderfifo_inst|scfifo_dlb1:auto_generated|a_dpfifo_d981:dpfifo|cntr_gra:rd_ptr_msb|_~0 LABCELL_X79_Y26_N33 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|scfifo:tfeventheaderfifo_inst|scfifo_dlb1:auto_generated|a_dpfifo_d981:dpfifo|cntr_hra:wr_ptr|_~0 LABCELL_X77_Y26_N27 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|scfifo:tfeventheaderfifo_inst|scfifo_dlb1:auto_generated|a_dpfifo_d981:dpfifo|cntr_tr6:usedw_counter|_~0 LABCELL_X77_Y26_N0 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|scfifo:tfeventheaderfifo_inst|scfifo_dlb1:auto_generated|a_dpfifo_d981:dpfifo|rd_ptr_lsb~1 LABCELL_X79_Y26_N42 1 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|scfifo:tfeventheaderfifo_inst|scfifo_dlb1:auto_generated|a_dpfifo_d981:dpfifo|valid_rreq LABCELL_X77_Y26_N18 5 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|scfifo:tfeventheaderfifo_inst|scfifo_dlb1:auto_generated|a_dpfifo_d981:dpfifo|valid_wreq MLABCELL_X76_Y26_N57 7 Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|state.waitfortrack FF_X93_Y30_N35 18 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|state~71 LABCELL_X93_Y30_N12 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFFitDEMUX:FITDEMUX|track_count_sclr FF_X126_Y25_N50 33 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|TFNestedLoop8L:NESTEDLOOP|counter_8:COUNTER0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X79_Y66_N36 6 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|TFNestedLoop8L:NESTEDLOOP|counter_8:COUNTER1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X116_Y70_N0 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|TFNestedLoop8L:NESTEDLOOP|counter_8:COUNTER2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X116_Y70_N27 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|TFNestedLoop8L:NESTEDLOOP|counter_8:COUNTER3|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X116_Y70_N57 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|TFNestedLoop8L:NESTEDLOOP|counter_8:COUNTER4|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X100_Y70_N48 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|TFNestedLoop8L:NESTEDLOOP|reset0 LABCELL_X79_Y66_N15 6 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|TFNestedLoop8L:NESTEDLOOP|reset1 LABCELL_X116_Y70_N6 4 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|TFNestedLoop8L:NESTEDLOOP|reset2 LABCELL_X116_Y70_N42 5 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|TFNestedLoop8L:NESTEDLOOP|reset3 LABCELL_X116_Y70_N21 3 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|TFNestedLoop8L:NESTEDLOOP|reset4 LABCELL_X100_Y70_N45 7 Clock enable, Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|TFNestedLoop8L:NESTEDLOOP|reset5 MLABCELL_X105_Y66_N42 8 Clock enable, Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|TFNestedLoop8L:NESTEDLOOP|reset6 MLABCELL_X105_Y66_N39 9 Clock enable, Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|TFNestedLoop8L:NESTEDLOOP|reset7 MLABCELL_X105_Y66_N54 5 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|cnt_reset FF_X106_Y66_N41 34 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|counter_8:PIXCOUNT0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X107_Y66_N36 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|counter_8:PIXCOUNT1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X107_Y66_N42 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|counter_8:PIXCOUNT2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X107_Y66_N45 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|counter_8:SCTCOUNT0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X107_Y66_N0 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|counter_8:SCTCOUNT1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X107_Y66_N39 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|counter_8:SCTCOUNT2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X107_Y66_N33 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|counter_8:SCTCOUNT3|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X107_Y66_N9 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|counter_8:SCTCOUNT4|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X107_Y66_N15 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|ram_wren FF_X103_Y66_N31 9 Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|road[0]~0 LABCELL_X106_Y66_N15 34 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomCombiner:COMBINER|state.writing FF_X103_Y66_N2 15 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitFIFO:FITFIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|_~4 LABCELL_X118_Y33_N54 9 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitFIFO:FITFIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|pulse_ram_output~0 LABCELL_X118_Y33_N15 17 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitFIFO:FITFIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|ram_read_address[0]~8 MLABCELL_X121_Y32_N18 7 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitFIFO:FITFIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|valid_wreq LABCELL_X117_Y33_N12 30 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X49_Y67_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X39_Y67_N42 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X56_Y82_N48 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X64_Y83_N21 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X66_Y89_N36 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X65_Y87_N0 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X107_Y89_N21 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual MLABCELL_X146_Y91_N36 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X127_Y89_N21 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:9:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X100_Y65_N30 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X39_Y66_N21 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X39_Y65_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X47_Y81_N42 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X66_Y73_N0 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X50_Y88_N42 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X48_Y85_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual MLABCELL_X92_Y89_N3 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X128_Y90_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X109_Y87_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:9:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X64_Y63_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X32_Y63_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X40_Y63_N42 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X56_Y77_N12 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X57_Y79_N9 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X55_Y85_N27 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X57_Y81_N48 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X88_Y89_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X100_Y94_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X106_Y87_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:9:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X64_Y60_N33 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X24_Y63_N42 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X26_Y61_N51 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X33_Y77_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X56_Y79_N9 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X24_Y87_N42 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X56_Y87_N48 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X77_Y95_N42 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X110_Y95_N6 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X125_Y89_N27 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR3|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:9:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X45_Y63_N21 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X24_Y62_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual MLABCELL_X25_Y60_N18 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X57_Y74_N42 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X47_Y75_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual MLABCELL_X20_Y84_N51 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X39_Y85_N27 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X64_Y93_N15 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X112_Y93_N6 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X125_Y82_N42 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR4|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:9:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X56_Y61_N15 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X33_Y60_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X40_Y59_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X40_Y73_N18 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X55_Y75_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X34_Y83_N27 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual MLABCELL_X68_Y82_N42 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual MLABCELL_X73_Y89_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X114_Y89_N54 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual LABCELL_X129_Y81_N27 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:CONSTSR5|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:9:ASHIFTREG|shift_taps_jk41:auto_generated|cntr_fcf:cntr1|cout_actual MLABCELL_X73_Y62_N12 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_mk41:auto_generated|cntr_jcf:cntr1|cout_actual LABCELL_X32_Y55_N30 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_mk41:auto_generated|cntr_jcf:cntr1|cout_actual LABCELL_X31_Y53_N15 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX0|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_mk41:auto_generated|cntr_jcf:cntr1|cout_actual MLABCELL_X20_Y51_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_mk41:auto_generated|cntr_jcf:cntr1|cout_actual LABCELL_X47_Y57_N54 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_mk41:auto_generated|cntr_jcf:cntr1|cout_actual LABCELL_X39_Y55_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX1|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_mk41:auto_generated|cntr_jcf:cntr1|cout_actual LABCELL_X39_Y53_N18 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_mk41:auto_generated|cntr_jcf:cntr1|cout_actual LABCELL_X24_Y57_N18 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_mk41:auto_generated|cntr_jcf:cntr1|cout_actual LABCELL_X21_Y55_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_PIX2|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_mk41:auto_generated|cntr_jcf:cntr1|cout_actual MLABCELL_X20_Y53_N54 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_SCT|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_mk41:auto_generated|cntr_jcf:cntr1|cout_actual LABCELL_X28_Y83_N54 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_SCT|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_mk41:auto_generated|cntr_jcf:cntr1|cout_actual MLABCELL_X68_Y88_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_SCT|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_mk41:auto_generated|cntr_jcf:cntr1|cout_actual LABCELL_X106_Y81_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_SCT|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_mk41:auto_generated|cntr_jcf:cntr1|cout_actual LABCELL_X74_Y57_N54 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR_SCT|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_mk41:auto_generated|cntr_jcf:cntr1|cout_actual LABCELL_X65_Y57_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X24_Y70_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X15_Y66_N30 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X12_Y65_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X31_Y64_N15 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X11_Y64_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X9_Y62_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X11_Y61_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X18_Y58_N51 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X16_Y57_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X48_Y83_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X49_Y80_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X39_Y79_N6 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X49_Y78_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X39_Y78_N9 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X36_Y76_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X33_Y75_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X25_Y72_N54 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X33_Y71_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X42_Y89_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X39_Y88_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X26_Y90_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X4_Y89_N51 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X7_Y87_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X7_Y86_N30 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X8_Y85_N48 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X11_Y84_N51 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFPixRecCalculator:PIXRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X24_Y85_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFRecChiSquareCalculator:ACHISQUARECALC|compare1~0 LABCELL_X26_Y96_N45 72 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFRecChiSquareCalculator:ACHISQUARECALC|compare2~1 MLABCELL_X113_Y94_N9 38 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFRecChiSquareCalculator:ACHISQUARECALC|shiftreg_20x6:OFLMAPSR|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_r151:auto_generated|cntr_uaf:cntr1|cout_actual MLABCELL_X83_Y92_N21 3 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X45_Y92_N36 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X39_Y91_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X37_Y93_N51 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X48_Y96_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X61_Y99_N18 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X50_Y99_N18 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X49_Y94_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X55_Y92_N18 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC0|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X55_Y94_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X95_Y93_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X103_Y95_N3 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X105_Y98_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X102_Y99_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X87_Y96_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X80_Y97_N3 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X80_Y93_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X90_Y91_N33 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC1|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X79_Y97_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X144_Y95_N18 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X150_Y95_N33 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X146_Y94_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X142_Y99_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X129_Y98_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X128_Y97_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X121_Y100_N18 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X131_Y100_N54 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC2|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X132_Y97_N39 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X124_Y96_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X131_Y96_N36 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X125_Y88_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X137_Y86_N48 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X129_Y86_N18 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X128_Y84_N51 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X129_Y83_N51 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X129_Y80_N30 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC3|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X134_Y81_N27 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X81_Y66_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X90_Y65_N0 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X82_Y64_N36 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X71_Y60_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X55_Y60_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X50_Y64_N18 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X47_Y63_N6 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X73_Y62_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitter:RECFITTER|TFSctRecCalculator:SCTRECCALC4|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X87_Y61_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitterOutputShiftRegister:RECOUTPUTSR|shiftreg_20x17:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_d351:auto_generated|cntr_icf:cntr1|cout_actual LABCELL_X57_Y76_N54 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitterOutputShiftRegister:RECOUTPUTSR|shiftreg_20x17:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_d351:auto_generated|cntr_icf:cntr1|cout_actual MLABCELL_X105_Y72_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|TFRecFitterOutputShiftRegister:RECOUTPUTSR|shiftreg_20x17:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_d351:auto_generated|cntr_icf:cntr1|cout_actual LABCELL_X91_Y92_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|altshift_taps:loose_reg_rtl_0|shift_taps_0ou:auto_generated|cntr_kcf:cntr1|cout_actual MLABCELL_X6_Y50_N21 7 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|altshift_taps:nom_chisquare_reg_rtl_0|shift_taps_qpu:auto_generated|cntr_mcf:cntr1|cout_actual LABCELL_X39_Y46_N24 11 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|passes~0 MLABCELL_X44_Y46_N24 57 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitter:NOMFITTER|tight_reg[0] FF_X34_Y50_N14 65 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|cntr_ocf:cntr1|cout_actual LABCELL_X132_Y68_N6 7 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|decode_9ea:wr_decode|w_anode119w[2]~0 LABCELL_X132_Y68_N51 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|cntr_ocf:cntr1|cout_actual LABCELL_X119_Y73_N24 7 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|decode_9ea:wr_decode|w_anode119w[2]~0 LABCELL_X119_Y73_N30 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|cntr_ocf:cntr1|cout_actual LABCELL_X128_Y72_N24 8 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|decode_9ea:wr_decode|w_anode119w[2]~0 LABCELL_X129_Y72_N42 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:3:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|cntr_ocf:cntr1|cout_actual MLABCELL_X131_Y74_N18 7 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:3:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|decode_9ea:wr_decode|w_anode119w[2]~0 MLABCELL_X131_Y74_N24 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:4:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|cntr_ocf:cntr1|cout_actual LABCELL_X118_Y72_N24 7 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:4:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|decode_9ea:wr_decode|w_anode119w[2]~0 LABCELL_X118_Y72_N54 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:5:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|cntr_ocf:cntr1|cout_actual LABCELL_X107_Y72_N24 7 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:5:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|decode_9ea:wr_decode|w_anode119w[2]~0 LABCELL_X107_Y72_N12 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:6:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|cntr_ocf:cntr1|cout_actual LABCELL_X93_Y67_N48 7 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:6:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|decode_9ea:wr_decode|w_anode119w[2]~0 LABCELL_X106_Y67_N18 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|cntr_ocf:cntr1|cout_actual LABCELL_X91_Y64_N27 9 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|decode_9ea:wr_decode|w_anode119w[2]~0 LABCELL_X103_Y64_N15 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|cntr_ocf:cntr1|counter_reg_bit[6] FF_X124_Y69_N20 24 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|cntr_ocf:cntr1|cout_actual MLABCELL_X124_Y69_N54 7 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|decode_9ea:wr_decode|w_anode111w[2] LABCELL_X114_Y39_N33 20 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|decode_9ea:wr_decode|w_anode119w[2]~0 MLABCELL_X124_Y69_N24 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|decode_9ea:wr_decode|w_anode98w[2] LABCELL_X114_Y39_N30 20 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:9:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|cntr_ocf:cntr1|counter_reg_bit[6] FF_X136_Y46_N20 17 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:9:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|cntr_ocf:cntr1|cout_actual LABCELL_X136_Y46_N33 7 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:9:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|decode_9ea:wr_decode|w_anode111w[2] LABCELL_X136_Y46_N51 13 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:9:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|decode_9ea:wr_decode|w_anode119w[2]~0 LABCELL_X119_Y46_N33 14 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomFitterShiftRegister:SHIFTREGISTER|shiftreg_20x66:\gen_SHIFTREGISTERS:9:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_h351:auto_generated|dpram_cgn1:dpram2|decode_9ea:wr_decode|w_anode98w[2] LABCELL_X136_Y46_N24 13 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomLayerOrganizer:LAYERORGANIZER|pixlayer_0_out[12]~3 LABCELL_X136_Y68_N3 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomLayerOrganizer:LAYERORGANIZER|pixlayer_0_out[15]~0 LABCELL_X137_Y68_N27 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomLayerOrganizer:LAYERORGANIZER|pixlayer_0_out[26]~7 LABCELL_X119_Y73_N48 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomLayerOrganizer:LAYERORGANIZER|pixlayer_1_out[26]~5 LABCELL_X129_Y72_N36 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomLayerOrganizer:LAYERORGANIZER|pixlayer_1_out[7]~0 LABCELL_X118_Y71_N18 22 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomLayerOrganizer:LAYERORGANIZER|pixlayer_2_out[0]~0 LABCELL_X127_Y72_N36 22 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomLayerOrganizer:LAYERORGANIZER|pixlayer_2_out[13]~6 MLABCELL_X131_Y74_N6 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomLayerOrganizer:LAYERORGANIZER|pixlayer_2_out[15]~3 MLABCELL_X131_Y74_N27 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomLayerOrganizer:LAYERORGANIZER|sctlayer_0_out[12]~3 LABCELL_X114_Y70_N21 22 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomLayerOrganizer:LAYERORGANIZER|sctlayer_0_out[5]~0 LABCELL_X114_Y70_N0 22 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomLayerOrganizer:LAYERORGANIZER|sctlayer_1_out[12]~2 LABCELL_X107_Y70_N18 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomLayerOrganizer:LAYERORGANIZER|sctlayer_2_out[11]~5 LABCELL_X103_Y67_N33 21 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomLayerOrganizer:LAYERORGANIZER|sctlayer_2_out[3]~0 LABCELL_X107_Y70_N39 22 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomLayerOrganizer:LAYERORGANIZER|sctlayer_3_out[0]~0 LABCELL_X106_Y67_N3 22 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomLayerOrganizer:LAYERORGANIZER|sctlayer_4_out[0]~0 LABCELL_X103_Y64_N3 22 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomLayerOrganizer:LAYERORGANIZER|sctlayer_4_out[13]~3 LABCELL_X91_Y64_N21 22 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomRoadFIFO:NOMROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|_~3 LABCELL_X108_Y66_N6 8 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomRoadFIFO:NOMROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|pulse_ram_output~2 LABCELL_X109_Y66_N57 6 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomRoadFIFO:NOMROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|ram_read_address[0]~8 LABCELL_X109_Y66_N21 7 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFNomFitterBlock:NOMFITTER|TFNomRoadFIFO:NOMROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|valid_wreq LABCELL_X108_Y38_N9 27 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X106_Y27_N18 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 MLABCELL_X102_Y27_N51 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X100_Y27_N0 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER3|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X103_Y34_N39 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER4|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X98_Y34_N54 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset0 MLABCELL_X102_Y27_N39 4 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset1 MLABCELL_X102_Y27_N57 4 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset2 MLABCELL_X102_Y27_N30 4 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset3 LABCELL_X98_Y34_N15 3 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset4 LABCELL_X103_Y34_N30 9 Clock enable, Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset5 LABCELL_X103_Y34_N24 8 Clock enable, Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset6 LABCELL_X103_Y34_N42 3 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|cnt_reset FF_X107_Y34_N41 33 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|counter_8:PIXCOUNT0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X112_Y34_N0 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|counter_8:PIXCOUNT1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X112_Y34_N57 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|counter_8:SCTCOUNT0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X112_Y34_N15 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|counter_8:SCTCOUNT1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 MLABCELL_X102_Y34_N57 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|counter_8:SCTCOUNT2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 MLABCELL_X102_Y34_N27 5 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|counter_8:SCTCOUNT3|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 MLABCELL_X102_Y34_N30 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|counter_8:SCTCOUNT4|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X112_Y34_N3 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|ram_wren FF_X106_Y34_N28 8 Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|road[0]~0 LABCELL_X110_Y34_N42 40 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixCombiner:COMBINER|state.writing FF_X107_Y34_N20 23 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|_~4 LABCELL_X119_Y33_N6 9 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|pulse_ram_output~0 LABCELL_X118_Y33_N24 17 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|ram_read_address[0]~8 LABCELL_X118_Y27_N15 7 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|valid_wreq LABCELL_X119_Y33_N3 30 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X116_Y29_N12 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X109_Y27_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X91_Y27_N18 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X122_Y27_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X99_Y25_N48 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X125_Y22_N21 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X110_Y29_N27 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X100_Y28_N15 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X93_Y24_N6 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X125_Y21_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X91_Y21_N9 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X91_Y17_N21 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_fk41:auto_generated|cntr_ccf:cntr1|cout_actual LABCELL_X77_Y31_N12 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_fk41:auto_generated|cntr_ccf:cntr1|cout_actual LABCELL_X74_Y24_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_fk41:auto_generated|cntr_ccf:cntr1|cout_actual MLABCELL_X76_Y25_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericShiftRegister:GUESSEDHITSR_PIXCOL|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_qk41:auto_generated|cntr_ncf:cntr1|counter_reg_bit[5] FF_X103_Y24_N17 38 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericShiftRegister:GUESSEDHITSR_PIXCOL|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_qk41:auto_generated|cntr_ncf:cntr1|cout_actual LABCELL_X100_Y24_N12 6 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericShiftRegister:GUESSEDHITSR_PIXROW|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_qk41:auto_generated|cntr_ncf:cntr1|counter_reg_bit[5] FF_X116_Y22_N47 38 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFGenericShiftRegister:GUESSEDHITSR_PIXROW|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_qk41:auto_generated|cntr_ncf:cntr1|cout_actual LABCELL_X116_Y22_N24 6 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X99_Y22_N27 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X103_Y20_N30 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X103_Y19_N15 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X114_Y19_N3 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X125_Y20_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X125_Y18_N18 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X127_Y17_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X97_Y16_N54 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X114_Y17_N6 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X114_Y25_N17 63 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X117_Y24_N17 64 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X107_Y25_N47 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:3:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X98_Y24_N47 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:4:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X80_Y34_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:5:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X102_Y28_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:6:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X102_Y28_N47 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X116_Y28_N47 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|mux_1ab:rd_mux|l1_w1_n0_mux_dataout~0 LABCELL_X110_Y26_N9 59 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|mux_1ab:rd_mux|l1_w3_n0_mux_dataout~0 LABCELL_X112_Y29_N24 30 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X127_Y24_N47 22 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixRoadFIFO:PIXROADFIFO|fifo_188x256_128:FIFO|scfifo:scfifo_component|scfifo_kug1:auto_generated|a_dpfifo_bge1:dpfifo|_~3 LABCELL_X108_Y34_N24 9 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixRoadFIFO:PIXROADFIFO|fifo_188x256_128:FIFO|scfifo:scfifo_component|scfifo_kug1:auto_generated|a_dpfifo_bge1:dpfifo|pulse_ram_output~2 LABCELL_X109_Y34_N48 7 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixRoadFIFO:PIXROADFIFO|fifo_188x256_128:FIFO|scfifo:scfifo_component|scfifo_kug1:auto_generated|a_dpfifo_bge1:dpfifo|ram_read_address[0]~8 LABCELL_X108_Y34_N54 8 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER0|TFPixRoadFIFO:PIXROADFIFO|fifo_188x256_128:FIFO|scfifo:scfifo_component|scfifo_kug1:auto_generated|a_dpfifo_bge1:dpfifo|valid_wreq LABCELL_X110_Y34_N54 26 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X91_Y32_N51 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X80_Y35_N15 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X80_Y35_N12 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER3|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X80_Y35_N0 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER4|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X91_Y35_N33 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset0 LABCELL_X80_Y35_N3 4 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset1 LABCELL_X80_Y35_N42 5 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset2 LABCELL_X80_Y35_N18 4 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset3 LABCELL_X80_Y35_N57 3 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset4 LABCELL_X91_Y35_N48 6 Clock enable, Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset5 LABCELL_X91_Y35_N24 6 Clock enable, Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset6 LABCELL_X91_Y35_N57 3 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|cnt_reset FF_X91_Y32_N17 30 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|counter_8:PIXCOUNT0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 MLABCELL_X90_Y33_N12 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|counter_8:PIXCOUNT1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X95_Y33_N27 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|counter_8:SCTCOUNT0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X95_Y33_N57 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|counter_8:SCTCOUNT1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X80_Y33_N24 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|counter_8:SCTCOUNT2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 MLABCELL_X90_Y33_N18 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|counter_8:SCTCOUNT3|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X95_Y33_N18 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|counter_8:SCTCOUNT4|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X95_Y33_N21 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|ram_wren FF_X90_Y33_N44 8 Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|road[0]~0 LABCELL_X95_Y33_N15 38 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixCombiner:COMBINER|state.writing FF_X91_Y33_N44 23 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|_~4 LABCELL_X118_Y29_N33 9 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|pulse_ram_output~0 LABCELL_X118_Y29_N42 17 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|ram_read_address[0]~8 LABCELL_X128_Y30_N51 7 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|valid_wreq LABCELL_X117_Y29_N6 30 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X41_Y31_N42 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X39_Y30_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X53_Y31_N54 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X58_Y33_N0 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X61_Y30_N54 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST0SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X49_Y29_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X42_Y25_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X41_Y24_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X72_Y21_N42 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X69_Y25_N48 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X61_Y24_N15 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:CONST1SMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X58_Y21_N18 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_fk41:auto_generated|cntr_ccf:cntr1|cout_actual LABCELL_X74_Y29_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_fk41:auto_generated|cntr_ccf:cntr1|cout_actual LABCELL_X72_Y31_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericConstArrShiftRegister:GUESSCONSTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_fk41:auto_generated|cntr_ccf:cntr1|cout_actual LABCELL_X56_Y27_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericShiftRegister:GUESSEDHITSR_PIXCOL|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_qk41:auto_generated|cntr_ncf:cntr1|counter_reg_bit[5] FF_X94_Y23_N47 38 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericShiftRegister:GUESSEDHITSR_PIXCOL|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_qk41:auto_generated|cntr_ncf:cntr1|cout_actual LABCELL_X94_Y23_N3 6 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericShiftRegister:GUESSEDHITSR_PIXROW|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_qk41:auto_generated|cntr_ncf:cntr1|counter_reg_bit[5] FF_X94_Y25_N47 38 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFGenericShiftRegister:GUESSEDHITSR_PIXROW|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_qk41:auto_generated|cntr_ncf:cntr1|cout_actual LABCELL_X94_Y25_N57 6 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X34_Y26_N15 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X42_Y23_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X45_Y22_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X42_Y20_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X71_Y22_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X55_Y23_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X53_Y22_N15 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X56_Y20_N0 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitter:PIXFITTER|TFPixRecCalculator:PIXRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X33_Y21_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X98_Y22_N47 63 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X95_Y28_N47 64 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X99_Y25_N47 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:3:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X68_Y32_N47 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:4:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X69_Y30_N47 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:5:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X91_Y31_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:6:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X108_Y32_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X93_Y25_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|mux_1ab:rd_mux|l1_w1_n0_mux_dataout~0 LABCELL_X93_Y29_N57 59 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|mux_1ab:rd_mux|l1_w3_n0_mux_dataout~0 LABCELL_X91_Y29_N18 30 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X74_Y27_N17 22 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixRoadFIFO:PIXROADFIFO|fifo_188x256_128:FIFO|scfifo:scfifo_component|scfifo_kug1:auto_generated|a_dpfifo_bge1:dpfifo|_~3 LABCELL_X94_Y33_N36 9 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixRoadFIFO:PIXROADFIFO|fifo_188x256_128:FIFO|scfifo:scfifo_component|scfifo_kug1:auto_generated|a_dpfifo_bge1:dpfifo|pulse_ram_output~2 MLABCELL_X92_Y33_N39 6 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixRoadFIFO:PIXROADFIFO|fifo_188x256_128:FIFO|scfifo:scfifo_component|scfifo_kug1:auto_generated|a_dpfifo_bge1:dpfifo|ram_read_address[0]~8 LABCELL_X91_Y33_N0 7 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFPixFitterBlock:PIXFITTER1|TFPixRoadFIFO:PIXROADFIFO|fifo_188x256_128:FIFO|scfifo:scfifo_component|scfifo_kug1:auto_generated|a_dpfifo_bge1:dpfifo|valid_wreq LABCELL_X94_Y33_N33 26 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFRoadOrganizerBlock:ROADORGANIZER|TFRoadOrganizer:ORGANIZER|Mux1~0 LABCELL_X155_Y37_N3 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFRoadOrganizerBlock:ROADORGANIZER|TFRoadOrganizer:ORGANIZER|all_iter[1]~4 MLABCELL_X102_Y37_N42 2 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFRoadOrganizerBlock:ROADORGANIZER|TFRoadOrganizer:ORGANIZER|pixlayermap[0] FF_X113_Y63_N26 31 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFRoadOrganizerBlock:ROADORGANIZER|TFRoadOrganizer:ORGANIZER|pixlayermap[2] FF_X112_Y64_N44 31 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFRoadOrganizerBlock:ROADORGANIZER|TFRoadOrganizer:ORGANIZER|sctlayermap[0] FF_X106_Y62_N5 17 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFRoadOrganizerBlock:ROADORGANIZER|TFRoadOrganizer:ORGANIZER|sctlayermap[4] FF_X106_Y62_N20 17 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFRoadOrganizerBlock:ROADORGANIZER|TFRoadOrganizerSctFO:SCTFANOUT|scteor_1~0 LABCELL_X110_Y62_N0 15 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFRoadOrganizerBlock:ROADORGANIZER|TFRoadOrganizerSctFO:SCTFANOUT|scteor_2~0 LABCELL_X106_Y62_N33 15 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X172_Y43_N54 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X173_Y43_N6 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X171_Y43_N54 5 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER3|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 MLABCELL_X167_Y43_N39 6 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER4|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X172_Y43_N21 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset0 LABCELL_X172_Y43_N51 4 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset1 LABCELL_X173_Y43_N12 4 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset2 LABCELL_X171_Y43_N51 6 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset3 LABCELL_X171_Y43_N39 6 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset4 MLABCELL_X167_Y43_N45 6 Clock enable, Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset5 MLABCELL_X167_Y43_N15 8 Clock enable, Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset6 MLABCELL_X167_Y43_N21 5 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|cnt_reset FF_X174_Y43_N29 28 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|counter_8:PIXCOUNT0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 MLABCELL_X174_Y43_N54 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|counter_8:PIXCOUNT1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 MLABCELL_X174_Y43_N12 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|counter_8:PIXCOUNT2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 MLABCELL_X174_Y43_N18 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|counter_8:SCTCOUNT0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X157_Y43_N39 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|counter_8:SCTCOUNT1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 MLABCELL_X174_Y43_N48 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|counter_8:SCTCOUNT2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 MLABCELL_X174_Y43_N45 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|counter_8:SCTCOUNT3|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X157_Y43_N54 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|ram_wren FF_X157_Y43_N22 8 Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|road[0]~0 LABCELL_X157_Y43_N48 39 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctCombiner:COMBINER|state.writing FF_X157_Y43_N26 23 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|_~4 LABCELL_X145_Y35_N15 9 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|pulse_ram_output~0 LABCELL_X144_Y35_N12 17 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|ram_read_address[0]~8 LABCELL_X144_Y31_N57 7 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|valid_wreq LABCELL_X144_Y35_N27 30 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X159_Y65_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X177_Y63_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X173_Y61_N27 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X155_Y69_N54 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X172_Y64_N42 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X171_Y63_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFGenericShiftRegister:GUESSCONSTSR|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_fk41:auto_generated|cntr_ccf:cntr1|cout_actual LABCELL_X157_Y65_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X180_Y65_N51 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X175_Y64_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X171_Y66_N39 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X170_Y68_N30 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X171_Y67_N51 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X172_Y66_N6 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X159_Y70_N36 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X181_Y73_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X173_Y73_N57 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X172_Y48_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X173_Y46_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X171_Y39_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:3:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X150_Y32_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:4:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X150_Y34_N17 63 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:5:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X150_Y35_N17 62 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:6:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X150_Y33_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X142_Y35_N47 62 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|mux_1ab:rd_mux|l1_w16_n0_mux_dataout~0 LABCELL_X149_Y35_N15 29 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X142_Y33_N47 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|mux_1ab:rd_mux|l1_w0_n0_mux_dataout~0 LABCELL_X149_Y33_N21 29 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:9:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X139_Y31_N17 13 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|_~3 LABCELL_X164_Y43_N18 9 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|pulse_ram_output~2 LABCELL_X159_Y43_N18 6 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|ram_read_address[0]~8 MLABCELL_X165_Y43_N12 7 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER0|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|valid_wreq LABCELL_X166_Y43_N48 26 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X155_Y37_N21 5 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X157_Y37_N6 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X157_Y37_N45 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER3|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X157_Y37_N27 5 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER4|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X157_Y35_N51 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset0 LABCELL_X157_Y37_N33 5 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset1 LABCELL_X157_Y37_N48 5 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset2 LABCELL_X157_Y37_N12 4 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset3 LABCELL_X157_Y35_N45 5 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset4 LABCELL_X156_Y36_N39 7 Clock enable, Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset5 LABCELL_X156_Y36_N42 6 Clock enable, Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset6 LABCELL_X156_Y36_N48 3 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|cnt_reset FF_X156_Y37_N8 32 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|counter_8:PIXCOUNT0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X159_Y38_N51 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|counter_8:PIXCOUNT1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X157_Y38_N18 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|counter_8:PIXCOUNT2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X163_Y37_N12 5 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|counter_8:SCTCOUNT0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X156_Y35_N36 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|counter_8:SCTCOUNT1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X156_Y35_N54 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|counter_8:SCTCOUNT2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X149_Y38_N57 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|counter_8:SCTCOUNT3|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X149_Y36_N21 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|ram_wren FF_X157_Y38_N28 8 Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|road[0]~0 MLABCELL_X154_Y38_N27 43 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctCombiner:COMBINER|state.writing FF_X156_Y38_N32 23 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|_~4 LABCELL_X145_Y28_N0 11 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|pulse_ram_output~0 LABCELL_X145_Y28_N54 17 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|ram_read_address[0]~8 LABCELL_X150_Y29_N54 7 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|valid_wreq MLABCELL_X146_Y28_N51 31 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X171_Y39_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual MLABCELL_X167_Y36_N12 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X171_Y45_N57 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X155_Y39_N15 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X164_Y36_N18 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X166_Y39_N48 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFGenericShiftRegister:GUESSCONSTSR|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_fk41:auto_generated|cntr_ccf:cntr1|cout_actual LABCELL_X150_Y39_N36 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X164_Y34_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X168_Y30_N51 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X175_Y33_N27 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X171_Y35_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X145_Y32_N36 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X163_Y32_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X168_Y37_N12 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X168_Y34_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X166_Y33_N54 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X161_Y27_N47 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X174_Y38_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X150_Y29_N47 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:3:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X152_Y30_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:4:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X150_Y26_N17 63 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:5:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X150_Y27_N17 62 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:6:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X150_Y28_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X137_Y28_N17 62 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|mux_1ab:rd_mux|l1_w16_n0_mux_dataout~0 LABCELL_X149_Y27_N21 29 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X145_Y31_N47 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|mux_1ab:rd_mux|l1_w0_n0_mux_dataout~0 LABCELL_X150_Y31_N18 29 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:9:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X150_Y25_N17 13 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|_~3 LABCELL_X156_Y38_N24 9 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|pulse_ram_output~2 LABCELL_X150_Y38_N24 6 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|ram_read_address[0]~8 LABCELL_X152_Y38_N9 7 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER1|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|valid_wreq LABCELL_X155_Y38_N18 26 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 MLABCELL_X170_Y50_N9 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 MLABCELL_X170_Y50_N48 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 MLABCELL_X170_Y50_N51 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER3|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X168_Y50_N51 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER4|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X168_Y50_N18 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset0 MLABCELL_X170_Y50_N24 3 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset1 MLABCELL_X170_Y50_N12 4 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset2 MLABCELL_X170_Y50_N42 4 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset3 LABCELL_X168_Y50_N42 3 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset4 MLABCELL_X167_Y50_N39 6 Clock enable, Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset5 MLABCELL_X167_Y50_N42 7 Clock enable, Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset6 MLABCELL_X167_Y50_N27 4 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|cnt_reset FF_X168_Y50_N26 33 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|counter_8:PIXCOUNT0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X163_Y47_N36 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|counter_8:PIXCOUNT1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X163_Y47_N42 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|counter_8:PIXCOUNT2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X163_Y47_N39 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|counter_8:SCTCOUNT0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X163_Y47_N48 5 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|counter_8:SCTCOUNT1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X161_Y46_N0 5 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|counter_8:SCTCOUNT2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X163_Y47_N21 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|counter_8:SCTCOUNT3|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X161_Y46_N18 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|ram_wren FF_X166_Y50_N52 8 Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|road[0]~0 LABCELL_X158_Y46_N15 45 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctCombiner:COMBINER|state.writing FF_X166_Y50_N14 23 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|_~4 LABCELL_X137_Y29_N33 10 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|pulse_ram_output~0 LABCELL_X140_Y29_N21 17 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|ram_read_address[0]~8 LABCELL_X139_Y34_N51 7 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|valid_wreq LABCELL_X140_Y29_N30 30 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X145_Y79_N6 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X150_Y73_N6 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X161_Y75_N24 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X159_Y77_N0 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X150_Y72_N18 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual MLABCELL_X146_Y72_N21 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFGenericShiftRegister:GUESSCONSTSR|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_fk41:auto_generated|cntr_ccf:cntr1|cout_actual LABCELL_X155_Y73_N54 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X131_Y75_N0 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X156_Y76_N54 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X157_Y75_N36 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X174_Y86_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual MLABCELL_X179_Y81_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X139_Y81_N54 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X142_Y80_N33 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X157_Y78_N6 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X152_Y79_N27 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X174_Y44_N47 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X173_Y51_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X174_Y44_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:3:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X171_Y52_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:4:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X149_Y38_N47 63 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:5:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X140_Y36_N17 62 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:6:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X149_Y37_N47 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X150_Y36_N17 62 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|mux_1ab:rd_mux|l1_w16_n0_mux_dataout~0 LABCELL_X144_Y36_N27 29 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X158_Y40_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|mux_1ab:rd_mux|l1_w0_n0_mux_dataout~0 LABCELL_X152_Y40_N54 29 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:9:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X155_Y42_N17 13 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|_~3 MLABCELL_X165_Y46_N30 10 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|pulse_ram_output~2 LABCELL_X157_Y46_N48 6 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|ram_read_address[0]~8 LABCELL_X159_Y46_N51 7 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER2|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|valid_wreq MLABCELL_X165_Y46_N18 26 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X126_Y40_N27 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X127_Y40_N18 5 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X126_Y40_N0 5 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER3|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X127_Y40_N54 5 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|counter_8:COUNTER4|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X127_Y40_N3 4 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset0 LABCELL_X126_Y40_N18 4 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset1 LABCELL_X127_Y40_N15 6 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset2 LABCELL_X126_Y40_N57 6 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset3 LABCELL_X128_Y40_N15 5 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset4 LABCELL_X125_Y39_N54 7 Clock enable, Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset5 LABCELL_X125_Y39_N12 7 Clock enable, Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|TFNestedLoop7L:NESTEDLOOP|reset6 LABCELL_X125_Y39_N42 4 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|cnt_reset FF_X128_Y40_N59 28 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|counter_8:PIXCOUNT0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X128_Y38_N27 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|counter_8:PIXCOUNT1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X132_Y38_N24 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|counter_8:PIXCOUNT2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X135_Y39_N24 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|counter_8:SCTCOUNT0|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X128_Y38_N54 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|counter_8:SCTCOUNT1|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X135_Y39_N9 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|counter_8:SCTCOUNT2|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X135_Y39_N51 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|counter_8:SCTCOUNT3|lpm_counter:LPM_COUNTER_component|cntr_8ei:auto_generated|_~0 LABCELL_X128_Y38_N48 3 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|ram_wren FF_X129_Y40_N10 8 Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|road[0]~0 LABCELL_X135_Y39_N27 43 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctCombiner:COMBINER|state.writing FF_X129_Y40_N56 23 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|_~4 LABCELL_X136_Y30_N57 9 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|pulse_ram_output~0 LABCELL_X137_Y30_N21 17 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|ram_read_address[0]~8 LABCELL_X139_Y30_N30 7 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitFIFO:FIFO|fifo_256x256_128:FIFO|scfifo:scfifo_component|scfifo_gug1:auto_generated|a_dpfifo_7ge1:dpfifo|valid_wreq LABCELL_X137_Y30_N15 30 Clock enable, Write enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X41_Y45_N27 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X49_Y43_N51 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X41_Y41_N36 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X41_Y42_N30 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X34_Y39_N6 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFGenericConstArrShiftRegister:CONSTSMALLSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_hk41:auto_generated|cntr_ecf:cntr1|cout_actual LABCELL_X58_Y37_N21 4 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFGenericShiftRegister:GUESSCONSTSR|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_fk41:auto_generated|cntr_ccf:cntr1|cout_actual LABCELL_X42_Y43_N51 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:0:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X33_Y44_N24 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:1:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X33_Y43_N6 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:2:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X32_Y39_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:3:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X33_Y40_N54 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:4:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X50_Y39_N42 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:5:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X42_Y36_N15 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:6:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X42_Y35_N21 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:7:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X50_Y34_N33 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|TFGenericChiArrShiftRegister:CHIPARTSR|TFGenericShiftRegister:SHIFTREG|altshift_taps:\gen_SHIFTREGISTERS:8:ASHIFTREG|shift_taps_gk41:auto_generated|cntr_dcf:cntr1|cout_actual LABCELL_X50_Y35_N18 5 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|TFSctRecCalculator:SCTRECCALC|altshift_taps:ofl_mh_reg_rtl_0|shift_taps_3ou:auto_generated|cntr_2bf:cntr1|cout_actual MLABCELL_X131_Y77_N18 4 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|altshift_taps:chisquare_reg_rtl_0|shift_taps_5ru:auto_generated|cntr_hcf:cntr1|cout_actual LABCELL_X135_Y23_N27 8 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitter:SCTFITTER|altshift_taps:passes_reg_rtl_0|shift_taps_tnu:auto_generated|cntr_ccf:cntr1|cout_actual LABCELL_X135_Y20_N18 6 Sync. clear no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:0:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X128_Y36_N47 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:1:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X127_Y34_N47 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:2:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X136_Y41_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:3:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X132_Y42_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:4:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X142_Y37_N47 63 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:5:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X139_Y36_N17 62 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:6:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X127_Y36_N47 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X134_Y36_N47 62 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:7:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|mux_1ab:rd_mux|l1_w16_n0_mux_dataout~0 LABCELL_X136_Y37_N36 29 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X145_Y37_N17 61 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:8:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|dpram_9gn1:dpram2|mux_1ab:rd_mux|l1_w0_n0_mux_dataout~0 LABCELL_X137_Y36_N51 29 Sync. load no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctFitterShiftRegister:SHIFTREGISTER|shiftreg_20x64:\gen_SHIFTREGISTERS:9:ASHIFTREG|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_f351:auto_generated|cntr_lcf:cntr1|counter_reg_bit[5] FF_X137_Y39_N47 13 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|_~3 LABCELL_X136_Y40_N12 8 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|pulse_ram_output~2 MLABCELL_X131_Y40_N36 6 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|ram_read_address[0]~8 LABCELL_X132_Y40_N21 7 Clock enable no -- -- --
TFBlock:inst2|TrackFitter:ATRACKFITTER|TFSctFitterBlock:SCTFITTER3|TFSctRoadFIFO:SCTROADFIFO|fifo_200x256_128:FIFO|scfifo:scfifo_component|scfifo_5ug1:auto_generated|a_dpfifo_sfe1:dpfifo|valid_wreq LABCELL_X136_Y40_N48 26 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX0HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_rdreq~0 LABCELL_X49_Y115_N15 23 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX0HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_wrreq~0 LABCELL_X42_Y114_N3 23 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX1HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_rdreq~0 LABCELL_X49_Y115_N54 24 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX1HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_wrreq~0 LABCELL_X41_Y116_N6 23 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX2HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_rdreq~0 LABCELL_X37_Y116_N45 27 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX2HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_wrreq~0 LABCELL_X33_Y116_N39 28 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX3HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_rdreq~0 LABCELL_X49_Y115_N45 23 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX3HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_wrreq~0 LABCELL_X32_Y115_N6 25 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX4HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_rdreq~0 LABCELL_X49_Y115_N0 23 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX4HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_wrreq~0 LABCELL_X45_Y113_N36 25 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX5HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_rdreq~0 LABCELL_X49_Y115_N9 23 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:PIX5HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_wrreq~0 LABCELL_X40_Y115_N42 24 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:SCT0HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_rdreq~0 LABCELL_X55_Y111_N48 22 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:SCT0HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_wrreq~0 LABCELL_X53_Y110_N9 25 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:SCT1HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_rdreq~0 LABCELL_X49_Y112_N15 24 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:SCT1HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_wrreq~0 LABCELL_X41_Y112_N9 25 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:SCT2HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_rdreq~0 LABCELL_X55_Y111_N30 22 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:SCT2HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_wrreq~0 LABCELL_X37_Y114_N6 22 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:SCT3HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_rdreq~0 LABCELL_X69_Y112_N33 22 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:SCT3HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_wrreq~0 LABCELL_X74_Y112_N12 24 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:SCT4HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_rdreq~0 LABCELL_X58_Y112_N57 29 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_hitcount:SCT4HITCOUNTFIFO|dcfifo:dcfifo_component|dcfifo_vtl1:auto_generated|valid_wrreq~0 MLABCELL_X73_Y111_N54 22 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_layermap:LAYERMAPFIFO|dcfifo:dcfifo_component|dcfifo_t0m1:auto_generated|valid_rdreq~0 LABCELL_X49_Y112_N6 24 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_layermap:LAYERMAPFIFO|dcfifo:dcfifo_component|dcfifo_t0m1:auto_generated|valid_wrreq~0 LABCELL_X57_Y108_N45 23 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX0FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|valid_rdreq~0 LABCELL_X32_Y108_N18 25 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX0FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|valid_wrreq~0 LABCELL_X28_Y107_N39 25 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX1FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|valid_rdreq~0 LABCELL_X50_Y107_N45 26 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX1FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|valid_wrreq~0 LABCELL_X45_Y108_N45 25 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX2FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|valid_rdreq~0 MLABCELL_X20_Y109_N57 25 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX2FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|valid_wrreq~0 LABCELL_X17_Y109_N27 25 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX3FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|valid_rdreq~0 LABCELL_X39_Y111_N21 26 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX3FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|valid_wrreq~0 LABCELL_X32_Y111_N48 25 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX4FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|valid_rdreq~0 LABCELL_X40_Y109_N27 28 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX4FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|valid_wrreq~0 LABCELL_X39_Y110_N54 24 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX5FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|valid_rdreq~0 LABCELL_X45_Y111_N33 25 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_pixlayer:PIX5FIFO|dcfifo:dcfifo_component|dcfifo_f1m1:auto_generated|valid_wrreq~0 LABCELL_X47_Y111_N24 24 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_road:ROADFIFO|dcfifo:dcfifo_component|dcfifo_11m1:auto_generated|valid_rdreq~0 LABCELL_X47_Y105_N9 26 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_road:ROADFIFO|dcfifo:dcfifo_component|dcfifo_11m1:auto_generated|valid_wrreq~0 LABCELL_X48_Y105_N42 26 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_sctlayer:SCT0FIFO|dcfifo:dcfifo_component|dcfifo_31m1:auto_generated|valid_rdreq~0 LABCELL_X57_Y110_N57 25 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_sctlayer:SCT0FIFO|dcfifo:dcfifo_component|dcfifo_31m1:auto_generated|valid_wrreq~0 LABCELL_X65_Y110_N36 26 Clock enable, Write enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_sctlayer:SCT1FIFO|dcfifo:dcfifo_component|dcfifo_31m1:auto_generated|valid_rdreq~0 LABCELL_X47_Y109_N45 25 Clock enable no -- -- --
TFInputBufferLogic:TFInputBufferLogic_inst|DOOutputCatcher:ADOOUTPUTCATCHER|fifo_dotf_sctlayer:SCT1FIFO|dcfifo:dcfifo_component|dcfifo_31m1:auto_generated|valid_wrreq~0 LABCELL_X53_Y109_N54 25 Clock enable, Wri