DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_pll0:pll0|pll1~FRACTIONAL_PLL  
    -- PLL Type Integer PLL
    -- PLL Location FRACTIONALPLL_X81_Y112_N0
    -- PLL Feedback clock type Global Clock
    -- PLL Bandwidth Auto (Low)
        -- PLL Bandwidth Range 1200000 to 600000 Hz
    -- Reference Clock Frequency 125.0 MHz
    -- Reference Clock Sourced by Dedicated Pin
    -- PLL VCO Frequency 400.0 MHz
    -- PLL Operation Mode Normal
    -- PLL Freq Min Lock 93.750000 MHz
    -- PLL Freq Max Lock 250.000000 MHz
    -- PLL Enable On
    -- PLL Fractional Division N/A
    -- M Counter 16
    -- N Counter 5
    -- PLL Refclk Select  
            -- PLL Refclk Select Location PLLREFCLKSELECT_X81_Y118_N0
            -- PLL Reference Clock Input 0 source clk_2
            -- PLL Reference Clock Input 1 source ref_clk1
            -- ADJPLLIN source N/A
            -- CORECLKIN source N/A
            -- IQTXRXCLKIN source N/A
            -- PLLIQCLKIN source N/A
            -- RXIQCLKIN source N/A
            -- CLKIN(0) source N/A
            -- CLKIN(1) source N/A
            -- CLKIN(2) source extmem_pll_refclk~input
            -- CLKIN(3) source N/A
    -- PLL Output Counter  
        -- DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_pll0:pll0|pll4~PLL_OUTPUT_COUNTER  
            -- Output Clock Frequency 200.0 MHz
            -- Output Clock Location PLLOUTPUTCOUNTER_X81_Y107_N1
            -- C Counter Odd Divider Even Duty Enable Off
            -- Duty Cycle 50.0000
            -- Phase Shift 225.000000 degrees
            -- C Counter 2
            -- C Counter PH Mux PRST 2
            -- C Counter PRST 2
        -- DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_pll0:pll0|pll7~PLL_OUTPUT_COUNTER  
            -- Output Clock Frequency 22.222222 MHz
            -- Output Clock Location PLLOUTPUTCOUNTER_X81_Y109_N1
            -- C Counter Odd Divider Even Duty Enable Off
            -- Duty Cycle 50.0000
            -- Phase Shift 0.000000 degrees
            -- C Counter 18
            -- C Counter PH Mux PRST 0
            -- C Counter PRST 1
        -- DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_pll0:pll0|pll6~PLL_OUTPUT_COUNTER  
            -- Output Clock Frequency 66.666666 MHz
            -- Output Clock Location PLLOUTPUTCOUNTER_X81_Y108_N1
            -- C Counter Odd Divider Even Duty Enable Off
            -- Duty Cycle 50.0000
            -- Phase Shift 0.000000 degrees
            -- C Counter 6
            -- C Counter PH Mux PRST 0
            -- C Counter PRST 1
        -- DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_pll0:pll0|pll2_phy~PLL_OUTPUT_COUNTER  
            -- Output Clock Frequency 400.0 MHz
            -- Output Clock Location PLLOUTPUTCOUNTER_X81_Y117_N1
            -- C Counter Odd Divider Even Duty Enable Off
            -- Duty Cycle 50.0000
            -- Phase Shift 0.000000 degrees
            -- C Counter 1
            -- C Counter PH Mux PRST 0
            -- C Counter PRST 1
        -- DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_pll0:pll0|pll3~PLL_OUTPUT_COUNTER  
            -- Output Clock Frequency 400.0 MHz
            -- Output Clock Location PLLOUTPUTCOUNTER_X81_Y118_N1
            -- C Counter Odd Divider Even Duty Enable Off
            -- Duty Cycle 50.0000
            -- Phase Shift 270.000000 degrees
            -- C Counter 1
            -- C Counter PH Mux PRST 6
            -- C Counter PRST 1
        -- DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|RLDRAMII_pll0:pll0|pll1_phy~PLL_OUTPUT_COUNTER  
            -- Output Clock Frequency 200.0 MHz
            -- Output Clock Location PLLOUTPUTCOUNTER_X81_Y116_N1
            -- C Counter Odd Divider Even Duty Enable Off
            -- Duty Cycle 50.0000
            -- Phase Shift 0.000000 degrees
            -- C Counter 2
            -- C Counter PH Mux PRST 0
            -- C Counter PRST 1
   
pll_main:pll_main_inst|pll_main_0002:pll_main_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL  
    -- PLL Type Integer PLL
    -- PLL Location FRACTIONALPLL_X0_Y105_N0
    -- PLL Feedback clock type Global Clock
    -- PLL Bandwidth Auto (Low)
        -- PLL Bandwidth Range 2100000 to 1400000 Hz
    -- Reference Clock Frequency 100.0 MHz
    -- Reference Clock Sourced by Dedicated Pin
    -- PLL VCO Frequency 1100.0 MHz
    -- PLL Operation Mode Normal
    -- PLL Freq Min Lock 54.545455 MHz
    -- PLL Freq Max Lock 145.454545 MHz
    -- PLL Enable On
    -- PLL Fractional Division N/A
    -- M Counter 11
    -- N Counter 1
    -- PLL Refclk Select  
            -- PLL Refclk Select Location PLLREFCLKSELECT_X0_Y111_N0
            -- PLL Reference Clock Input 0 source clk_0
            -- PLL Reference Clock Input 1 source ref_clk1
            -- ADJPLLIN source N/A
            -- CORECLKIN source N/A
            -- IQTXRXCLKIN source N/A
            -- PLLIQCLKIN source N/A
            -- RXIQCLKIN source N/A
            -- CLKIN(0) source master_clock~input
            -- CLKIN(1) source N/A
            -- CLKIN(2) source N/A
            -- CLKIN(3) source N/A
    -- PLL Output Counter  
        -- pll_main:pll_main_inst|pll_main_0002:pll_main_inst|altera_pll:altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER  
            -- Output Clock Frequency 100.0 MHz
            -- Output Clock Location PLLOUTPUTCOUNTER_X0_Y97_N1
            -- C Counter Odd Divider Even Duty Enable On
            -- Duty Cycle 50.0000
            -- Phase Shift 0.000000 degrees
            -- C Counter 11
            -- C Counter PH Mux PRST 0
            -- C Counter PRST 1
        -- pll_main:pll_main_inst|pll_main_0002:pll_main_inst|altera_pll:altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER  
            -- Output Clock Frequency 110.0 MHz
            -- Output Clock Location PLLOUTPUTCOUNTER_X0_Y99_N1
            -- C Counter Odd Divider Even Duty Enable Off
            -- Duty Cycle 50.0000
            -- Phase Shift 0.000000 degrees
            -- C Counter 10
            -- C Counter PH Mux PRST 0
            -- C Counter PRST 1
        -- pll_main:pll_main_inst|pll_main_0002:pll_main_inst|altera_pll:altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER  
            -- Output Clock Frequency 10.0 MHz
            -- Output Clock Location PLLOUTPUTCOUNTER_X0_Y98_N1
            -- C Counter Odd Divider Even Duty Enable Off
            -- Duty Cycle 50.0000
            -- Phase Shift 0.000000 degrees
            -- C Counter 110
            -- C Counter PH Mux PRST 0
            -- C Counter PRST 1