Name  
RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|Tx_2_1Gbps:xcvr_inst|altera_xcvr_custom:tx_2_1gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_plls:gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].pll.cmu_pll.tx_pll  
    -- PLL Type CMU PLL
    -- PLL Location CHANNELPLL_X0_Y41_N33
    -- PLL Bandwidth Auto (Medium)
    -- Reference Clock Frequency 100.0 MHz
    -- Reference Clock Sourced by Dedicated Pin
    -- Output Clock Frequency 3200.0 MHz
    -- L counter PD Clock Disable On
    -- M Counter 32
    -- PCIE Frequency Control pcie_100mhz
    -- PD L Counter 1
    -- PFD L Counter 1
    -- PFD Feedback Source vcoclk
    -- Powerdown Off
    -- Reference Clock Divider 1
    -- Reverse Serial Loopback Off
    -- Reference Clock Select Source ref_iqclk0
    -- Clock Divider  
        -- RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|Tx_2_1Gbps:xcvr_inst|altera_xcvr_custom:tx_2_1gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb  
            -- Location HSSIPMATXCGB_X0_Y35_N33
            -- Clock Divider Type Local
            -- Auto Negotiation Off
            -- Mode 20
            -- x1 Clock Source ch1_txpll_b
            -- x1 Div M Selection 1
            -- xN Clock Source cgb_x1_m_div
            -- Data Rate 6400.0 Mbps
   
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_plls:gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].pll.cmu_pll.tx_pll  
    -- PLL Type CMU PLL
    -- PLL Location CHANNELPLL_X183_Y53_N33
    -- PLL Bandwidth Auto (Medium)
    -- Reference Clock Frequency 100.0 MHz
    -- Reference Clock Sourced by Dedicated Pin
    -- Output Clock Frequency 3200.0 MHz
    -- L counter PD Clock Disable On
    -- M Counter 32
    -- PCIE Frequency Control pcie_100mhz
    -- PD L Counter 1
    -- PFD L Counter 1
    -- PFD Feedback Source vcoclk
    -- Powerdown Off
    -- Reference Clock Divider 1
    -- Reverse Serial Loopback Off
    -- Reference Clock Select Source ref_iqclk5
    -- Clock Divider  
        -- RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb  
            -- Location HSSIPMATXCGB_X183_Y43_N33
            -- Clock Divider Type Local
            -- Auto Negotiation Off
            -- Mode 20
            -- x1 Clock Source ch1_txpll_t
            -- x1 Div M Selection 1
            -- xN Clock Source cgb_x1_m_div
            -- Data Rate 6400.0 Mbps
        -- RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb  
            -- Location HSSIPMATXCGB_X183_Y47_N33
            -- Clock Divider Type Local
            -- Auto Negotiation Off
            -- Mode 20
            -- x1 Clock Source ch1_txpll_t
            -- x1 Div M Selection 1
            -- xN Clock Source cgb_x1_m_div
            -- Data Rate 6400.0 Mbps
        -- RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb  
            -- Location HSSIPMATXCGB_X183_Y39_N33
            -- Clock Divider Type Local
            -- Auto Negotiation Off
            -- Mode 20
            -- x1 Clock Source ch1_txpll_t
            -- x1 Div M Selection 1
            -- xN Clock Source cgb_x1_m_div
            -- Data Rate 6400.0 Mbps
        -- RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb  
            -- Location HSSIPMATXCGB_X183_Y35_N33
            -- Clock Divider Type Local
            -- Auto Negotiation Off
            -- Mode 20
            -- x1 Clock Source ch1_txpll_t
            -- x1 Div M Selection 1
            -- xN Clock Source cgb_x1_m_div
            -- Data Rate 6400.0 Mbps
   
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_plls:gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].pll.cmu_pll.tx_pll  
    -- PLL Type CMU PLL
    -- PLL Location CHANNELPLL_X183_Y17_N33
    -- PLL Bandwidth Auto (Medium)
    -- Reference Clock Frequency 100.0 MHz
    -- Reference Clock Sourced by Dedicated Pin
    -- Output Clock Frequency 3200.0 MHz
    -- L counter PD Clock Disable On
    -- M Counter 32
    -- PCIE Frequency Control pcie_100mhz
    -- PD L Counter 1
    -- PFD L Counter 1
    -- PFD Feedback Source vcoclk
    -- Powerdown Off
    -- Reference Clock Divider 1
    -- Reverse Serial Loopback Off
    -- Reference Clock Select Source ref_iqclk2
    -- Clock Divider  
        -- RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb  
            -- Location HSSIPMATXCGB_X183_Y19_N33
            -- Clock Divider Type Local
            -- Auto Negotiation Off
            -- Mode 20
            -- x1 Clock Source ch1_txpll_b
            -- x1 Div M Selection 1
            -- xN Clock Source cgb_x1_m_div
            -- Data Rate 6400.0 Mbps
        -- RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb  
            -- Location HSSIPMATXCGB_X183_Y31_N33
            -- Clock Divider Type Local
            -- Auto Negotiation Off
            -- Mode 20
            -- x1 Clock Source ch1_txpll_b
            -- x1 Div M Selection 1
            -- xN Clock Source cgb_x1_m_div
            -- Data Rate 6400.0 Mbps
        -- RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb  
            -- Location HSSIPMATXCGB_X183_Y27_N33
            -- Clock Divider Type Local
            -- Auto Negotiation Off
            -- Mode 20
            -- x1 Clock Source ch1_txpll_b
            -- x1 Div M Selection 1
            -- xN Clock Source cgb_x1_m_div
            -- Data Rate 6400.0 Mbps
        -- RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb  
            -- Location HSSIPMATXCGB_X183_Y23_N33
            -- Clock Divider Type Local
            -- Auto Negotiation Off
            -- Mode 20
            -- x1 Clock Source ch1_txpll_b
            -- x1 Div M Selection 1
            -- xN Clock Source cgb_x1_m_div
            -- Data Rate 6400.0 Mbps
   
RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_plls:gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].pll.cmu_pll.tx_pll  
    -- PLL Type CMU PLL
    -- PLL Location CHANNELPLL_X0_Y17_N33
    -- PLL Bandwidth Auto (Medium)
    -- Reference Clock Frequency 100.0 MHz
    -- Reference Clock Sourced by Dedicated Pin
    -- Output Clock Frequency 3200.0 MHz
    -- L counter PD Clock Disable On
    -- M Counter 32
    -- PCIE Frequency Control pcie_100mhz
    -- PD L Counter 1
    -- PFD L Counter 1
    -- PFD Feedback Source vcoclk
    -- Powerdown Off
    -- Reference Clock Divider 1
    -- Reverse Serial Loopback Off
    -- Reference Clock Select Source ref_iqclk1
    -- Clock Divider  
        -- RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb  
            -- Location HSSIPMATXCGB_X0_Y19_N33
            -- Clock Divider Type Local
            -- Auto Negotiation Off
            -- Mode 20
            -- x1 Clock Source ch1_txpll_b
            -- x1 Div M Selection 1
            -- xN Clock Source cgb_x1_m_div
            -- Data Rate 6400.0 Mbps
        -- RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb  
            -- Location HSSIPMATXCGB_X0_Y31_N33
            -- Clock Divider Type Local
            -- Auto Negotiation Off
            -- Mode 20
            -- x1 Clock Source ch1_txpll_b
            -- x1 Div M Selection 1
            -- xN Clock Source cgb_x1_m_div
            -- Data Rate 6400.0 Mbps
        -- RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb  
            -- Location HSSIPMATXCGB_X0_Y23_N33
            -- Clock Divider Type Local
            -- Auto Negotiation Off
            -- Mode 20
            -- x1 Clock Source ch1_txpll_b
            -- x1 Div M Selection 1
            -- xN Clock Source cgb_x1_m_div
            -- Data Rate 6400.0 Mbps
        -- RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb  
            -- Location HSSIPMATXCGB_X0_Y27_N33
            -- Clock Divider Type Local
            -- Auto Negotiation Off
            -- Mode 20
            -- x1 Clock Source ch1_txpll_b
            -- x1 Div M Selection 1
            -- xN Clock Source cgb_x1_m_div
            -- Data Rate 6400.0 Mbps