Name  
gen_datain~input  
    -- Receiver Channel Location IOIBUF_X0_Y38_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|Tx_2_1Gbps:xcvr_inst|altera_xcvr_custom:tx_2_1gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X0_Y38_N34
        -- Mode 20
        -- Data Rate 6400.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|Tx_2_1Gbps:xcvr_inst|altera_xcvr_custom:tx_2_1gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X0_Y38_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|Tx_2_1Gbps:xcvr_inst|altera_xcvr_custom:tx_2_1gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X0_Y37_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|Tx_2_1Gbps:xcvr_inst|altera_xcvr_custom:tx_2_1gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X0_Y38_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_GenData:gendata_inst|Tx_2_1Gbps:xcvr_inst|altera_xcvr_custom:tx_2_1gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X0_Y37_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 3200.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 16
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 1
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk0
   
datain_fromAMB[3]~input  
    -- Receiver Channel Location IOIBUF_X0_Y14_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X0_Y14_N34
        -- Mode 20
        -- Data Rate 2000.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X0_Y14_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X0_Y13_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X0_Y14_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X0_Y13_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 1000.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 10
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 2
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk2
   
datain_fromAMB[2]~input  
    -- Receiver Channel Location IOIBUF_X0_Y50_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X0_Y50_N34
        -- Mode 20
        -- Data Rate 2000.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X0_Y50_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X0_Y49_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X0_Y50_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X0_Y49_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 1000.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 10
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 2
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk5
   
datain_fromAMB[1]~input  
    -- Receiver Channel Location IOIBUF_X0_Y46_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X0_Y46_N34
        -- Mode 20
        -- Data Rate 2000.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X0_Y46_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X0_Y45_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X0_Y46_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X0_Y45_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 1000.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 10
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 2
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk0
   
datain_fromAMB[0]~input  
    -- Receiver Channel Location IOIBUF_X0_Y58_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X0_Y58_N34
        -- Mode 20
        -- Data Rate 2000.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X0_Y58_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X0_Y57_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X0_Y58_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_Road:road_inst|Rx_4_2Gbps:xcvr_inst|altera_xcvr_custom:rx_4_2gbps_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X0_Y57_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 1000.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 10
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 2
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk5
   
hitdatain3[3]~input  
    -- Receiver Channel Location IOIBUF_X183_Y50_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X183_Y50_N34
        -- Mode 20
        -- Data Rate 6400.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X183_Y50_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X183_Y49_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X183_Y50_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X183_Y49_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 3200.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 16
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 1
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk5
   
hitdatain3[2]~input  
    -- Receiver Channel Location IOIBUF_X183_Y42_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X183_Y42_N34
        -- Mode 20
        -- Data Rate 6400.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X183_Y42_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X183_Y41_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X183_Y42_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X183_Y41_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 3200.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 16
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 1
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk0
   
hitdatain3[1]~input  
    -- Receiver Channel Location IOIBUF_X183_Y38_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X183_Y38_N34
        -- Mode 20
        -- Data Rate 6400.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X183_Y38_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X183_Y37_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X183_Y38_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X183_Y37_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 3200.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 16
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 1
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk0
   
hitdatain3[0]~input  
    -- Receiver Channel Location IOIBUF_X183_Y46_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X183_Y46_N34
        -- Mode 20
        -- Data Rate 6400.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X183_Y46_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X183_Y45_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X183_Y46_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr3_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X183_Y45_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 3200.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 16
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 1
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk0
   
hitdatain2[3]~input  
    -- Receiver Channel Location IOIBUF_X183_Y34_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X183_Y34_N34
        -- Mode 20
        -- Data Rate 6400.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X183_Y34_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X183_Y33_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X183_Y34_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X183_Y33_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 3200.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 16
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 1
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk1
   
hitdatain2[2]~input  
    -- Receiver Channel Location IOIBUF_X183_Y30_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X183_Y30_N34
        -- Mode 20
        -- Data Rate 6400.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X183_Y30_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X183_Y29_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X183_Y30_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X183_Y29_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 3200.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 16
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 1
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk1
   
hitdatain2[1]~input  
    -- Receiver Channel Location IOIBUF_X183_Y26_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X183_Y26_N34
        -- Mode 20
        -- Data Rate 6400.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X183_Y26_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X183_Y25_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X183_Y26_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X183_Y25_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 3200.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 16
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 1
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk1
   
hitdatain2[0]~input  
    -- Receiver Channel Location IOIBUF_X183_Y22_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X183_Y22_N34
        -- Mode 20
        -- Data Rate 6400.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X183_Y22_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X183_Y21_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X183_Y22_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr2_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X183_Y21_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 3200.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 16
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 1
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk2
   
hitdatain1[3]~input  
    -- Receiver Channel Location IOIBUF_X0_Y34_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X0_Y34_N34
        -- Mode 20
        -- Data Rate 6400.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X0_Y34_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X0_Y33_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X0_Y34_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X0_Y33_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 3200.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 16
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 1
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk0
   
hitdatain1[2]~input  
    -- Receiver Channel Location IOIBUF_X0_Y26_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X0_Y26_N34
        -- Mode 20
        -- Data Rate 6400.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X0_Y26_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X0_Y25_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X0_Y26_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[2].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X0_Y25_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 3200.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 16
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 1
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk0
   
hitdatain1[1]~input  
    -- Receiver Channel Location IOIBUF_X0_Y30_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X0_Y30_N34
        -- Mode 20
        -- Data Rate 6400.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X0_Y30_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X0_Y29_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X0_Y30_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X0_Y29_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 3200.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 16
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 1
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk0
   
hitdatain1[0]~input  
    -- Receiver Channel Location IOIBUF_X0_Y22_N39
    -- Receiver Deserializer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_deser
        -- Receiver Deserializer Location HSSIPMARXDESER_X0_Y22_N34
        -- Mode 20
        -- Data Rate 6400.0 Mbps
        -- Auto Negotiation Off
        -- Enable Bit Slip False
        -- Signal Detect Clock Enable On
    -- Receiver Buffer  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf
        -- Receiver Buffer Location HSSIPMARXBUF_X0_Y22_N35
        -- DC Gain 0
        -- AC Gain 0
        -- Termination 100 Ohms
        -- Equalization Bandwidth Selection N/A
        -- Serial Loopback N/A
        -- VCCELA Supply Voltage N/A
    -- Receiver Interface  
        -- Receiver Data Source PCS
    -- HSSI Common PCS PMA Interface PPM Detector  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_common_pcs_pma_interface_rbc:inst_av_hssi_common_pcs_pma_interface|wys
        -- HSSI Common PCS PMA Interface Location HSSICOMMONPCSPMAINTERFACE_X0_Y21_N61
        -- PPM Threshold (+/-) for freqlock (hd_smrt_com_pcs_pma_if_ppmsel) ppmsel_1000
        -- Enable early detection of PPM violation after lock (hd_smrt_com_pcs_pma_if_ppm_deassert_early) deassert_early_dis
        -- Automatic Speed Negotiation (hd_smrt_com_pcs_pma_if_auto_speed_ena) dis_auto_speed_ena
        -- PPM Counter Limit (hd_smrt_com_pcs_pma_if_ppm_gen1_2_cnt) cnt_32k
        -- PPM Detector Start cycle after eidle exit (hd_smrt_com_pcs_pma_if_ppm_post_eidle_delay) cnt_200_cycles
    -- Receiver Standard PCS  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys
        -- Receiver Standard PCS Location HSSI8GRXPCS_X0_Y22_N59
        -- Protocol basic
        -- PCS Low Latency Configuration dis_pcs_bypass
        -- Word Aligner Mode auto_align_pld_ctrl
        -- Run Length Check en_runlength_dw
        -- Rate Match Mode dis_rm
        -- 8b10b Decoder en_8b10b_ibm
        -- Byte Deserializer en_bds_by_2
        -- Byte Order Block Mode en_pcs_ctrl_nine_bit_bo
        -- Phase Compensation FIFO Mode low_latency
    -- Receiver PLL  
        -- Name RxBlock:RxBlock_inst|Xcvr_Hits:xcvr1_inst|Rx_4:xcvr_inst|altera_xcvr_custom:rx_4_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
        -- PLL Location CHANNELPLL_X0_Y21_N33
        -- PLL Type CDR PLL
        -- PLL Bandwidth Type Auto (Medium)
        -- PLL Bandwidth Range 2 to 4 MHz
        -- Reference Clock Frequency 100.0 MHz
        -- Output Clock Frequency 3200.0 MHz
        -- L Counter PD Clock Disable Off
        -- M Counter 16
        -- PCIE Frequency Control pcie_100mhz
        -- PD L Counter 1
        -- PFD L Counter 2
        -- Powerdown Off
        -- Reference Clock Divider 1
        -- Reverse Serial Loopback Off
        -- Reference Clock Selection ref_iqclk1