Name Pin # I/O Bank X coordinate Y coordinate Z coordinate Output Register Slew Rate PCI I/O Enabled Open Drain TRI Primitive Bus Hold Weak Pull Up I/O Standard Current Strength Termination Termination Control Block Output Buffer Pre-emphasis Voltage Output Differential Output Buffer Delay Output Buffer Delay Control Location assigned by Output Enable Source Output Enable Group
dataout1[0] AE32 B0L 0 19 38 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout1[0](n) AE31 B0L 0 19 36 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout1[1] AA32 B0L 0 27 38 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout1[1](n) AA31 B0L 0 27 36 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout1[2] AC32 B0L 0 23 38 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout1[2](n) AC31 B0L 0 23 36 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout1[3] W32 B0L 0 31 38 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout1[3](n) W31 B0L 0 31 36 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout2[0] AE3 B0R 183 19 38 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout2[0](n) AE4 B0R 183 19 36 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout2[1] AC3 B0R 183 23 38 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout2[1](n) AC4 B0R 183 23 36 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout2[2] AA3 B0R 183 27 38 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout2[2](n) AA4 B0R 183 27 36 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout2[3] W3 B0R 183 31 38 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout2[3](n) W4 B0R 183 31 36 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout3[0] N3 B1R 183 43 38 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout3[0](n) N4 B1R 183 43 36 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout3[1] U3 B1R 183 35 38 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout3[1](n) U4 B1R 183 35 36 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout3[2] R3 B1R 183 39 38 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout3[2](n) R4 B1R 183 39 36 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout3[3] L3 B1R 183 47 38 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dataout3[3](n) L4 B1R 183 47 36 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
dir_trans AE18 3D 79 0 0 no 1 no no no no Off 3.0-V LVTTL Default Series 50 Ohm without Calibration -- no no 0 Off User - -
mem_a[0] A25 8B 31 137 17 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[10] D25 8B 31 137 51 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[11] C26 8B 27 137 57 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[12] D23 8B 38 137 34 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[13] H23 8B 40 137 0 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[14] C25 8B 31 137 34 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[15] F23 8B 36 137 0 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[16] K24 8B 40 137 34 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[17] L23 8B 34 137 91 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[18] K23 8B 34 137 74 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[19] H24 8B 32 137 17 no 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[1] B26 8B 27 137 40 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[2] E23 8B 38 137 51 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[3] A26 8B 31 137 0 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[4] L29 8A 26 137 51 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[5] C23 8B 38 137 17 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[6] J25 8B 27 137 74 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[7] F25 8B 29 137 0 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[8] E24 8B 34 137 57 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_a[9] K25 8B 27 137 91 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_ba[0] D24 8B 34 137 40 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_ba[1] G23 8B 36 137 17 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_ba[2] G24 8B 32 137 0 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_ck J26 8A 19 137 34 yes 1 no no yes no Off Differential 1.8-V HSTL Class I Default Series 50 Ohm without Calibration -- no no 0 Off User - -
mem_ck_n K26 8A 19 137 51 yes 1 no no yes no Off Differential 1.8-V HSTL Class I Default Series 50 Ohm without Calibration -- no no 0 Off User - -
mem_cs_n[0] L24 8B 40 137 51 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_dk[0] F22 8C 44 137 0 yes 1 no no yes no Off Differential 1.8-V HSTL Class I Default Series 50 Ohm without Calibration -- no no 0 Off User - -
mem_dk[1] D29 8A 14 137 40 yes 1 no no yes no Off Differential 1.8-V HSTL Class I Default Series 50 Ohm without Calibration -- no no 0 Off User - -
mem_dk_n[0] G22 8C 44 137 17 yes 1 no no yes no Off Differential 1.8-V HSTL Class I Default Series 50 Ohm without Calibration -- no no 0 Off User - -
mem_dk_n[1] E29 8A 14 137 57 yes 1 no no yes no Off Differential 1.8-V HSTL Class I Default Series 50 Ohm without Calibration -- no no 0 Off User - -
mem_dm[0] D30 8A 14 137 74 yes 1 no no yes no Off 1.8-V HSTL Class I Default Series 50 Ohm with Calibration DOVME:DOVME_inst|RLDRAMII:b2v_inst|RLDRAMII_0002:rldramii_inst|altera_mem_if_oct_arriav:oct0|sd1a_0 no no 0 Off User - -
mem_ref_n J23 8B 40 137 17 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
mem_we_n B24 8B 38 137 0 yes 1 no no no no Off 1.8-V HSTL Class I 12mA Off -- no no 0 Off User - -
merge_dataout U32 B1L 0 35 38 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
merge_dataout(n) U31 B1L 0 35 36 no no no no no no Off 1.5-V PCML Default OCT 100 Ohms -- no no 0 Off User - -
transceivers_OE AH16 4D 103 0 57 no 1 no no no no Off 3.0-V LVTTL Default Series 50 Ohm without Calibration -- no no 0 Off User - -