Statistic Top DataOrganizer:DataOrganizer_inst TFBlock:TFBlock_inst sld_hub:auto_hub hard_block:auto_generated_inst
Logic utilization (ALMs needed / total ALMs on device) 18970 / 190240 ( 10 % ) 33392 / 190240 ( 18 % ) 37268 / 190240 ( 20 % ) 64 / 190240 ( < 1 % ) 1 / 190240 ( < 1 % )
ALMs needed [=A-B+C] 18970 33392 37268 64 1
    [A] ALMs used in final placement [=a+b+c+d] 20758 / 190240 ( 11 % ) 35812 / 190240 ( 19 % ) 46045 / 190240 ( 24 % ) 63 / 190240 ( < 1 % ) 1 / 190240 ( < 1 % )
        [a] ALMs used for LUT logic and registers 7345 12897 14341 31 0
        [b] ALMs used for LUT logic 7128 10911 4054 23 1
        [c] ALMs used for registers 6025 8264 22240 9 0
        [d] ALMs used for memory (up to half of total ALMs) 260 3740 5410 0 0
    [B] Estimate of ALMs recoverable by dense packing 1997 / 190240 ( 1 % ) 2798 / 190240 ( 1 % ) 9691 / 190240 ( 5 % ) 9 / 190240 ( < 1 % ) 0 / 190240 ( 0 % )
    [C] Estimate of ALMs unavailable [=a+b+c+d] 209 / 190240 ( < 1 % ) 378 / 190240 ( < 1 % ) 914 / 190240 ( < 1 % ) 10 / 190240 ( < 1 % ) 0 / 190240 ( 0 % )
        [a] Due to location constrained logic 15 0 6 0 0
        [b] Due to LAB-wide signal conflicts 49 14 685 10 0
        [c] Due to LAB input limits 134 364 223 0 0
        [d] Due to virtual I/Os 11 0 0 0 0
           
Difficulty packing design Low Low Low Low Low
           
Total LABs:  partially or completely used 3120 / 19024 ( 16 % ) 4878 / 19024 ( 26 % ) 9309 / 19024 ( 49 % ) 12 / 19024 ( < 1 % ) 2 / 19024 ( < 1 % )
    -- Logic LABs 3094 4504 8768 12 2
    -- Memory LABs (up to half of total LABs) 26 374 541 0 0
           
Combinational ALUT usage for logic 25498 42544 44770 93 2
    -- 7 input functions 94 388 4 1 0
    -- 6 input functions 5007 10987 2623 11 0
    -- 5 input functions 3959 3059 821 23 0
    -- 4 input functions 4635 18214 527 14 0
    -- <=3 input functions 11344 5514 30953 44 2
Combinational ALUT usage for route-throughs 5728 6644 24605 7 0
Memory ALUT usage 459 4382 9842 0 0
    -- 64-address deep 0 0 0 0 0
    -- 32-address deep 459 4382 9842 0 0
           
Dedicated logic registers 0 0 0 0 0
    -- By type:          
        -- Primary logic registers 26738 / 380480 ( 7 % ) 42320 / 380480 ( 11 % ) 73160 / 380480 ( 19 % ) 78 / 380480 ( < 1 % ) 0 / 380480 ( 0 % )
        -- Secondary logic registers 1376 / 380480 ( < 1 % ) 1236 / 380480 ( < 1 % ) 1077 / 380480 ( < 1 % ) 2 / 380480 ( < 1 % ) 0 / 380480 ( 0 % )
    -- By function:          
        -- Design implementation registers 27205 43188 73296 78 0
        -- Routing optimization registers 909 368 941 2 0
           
           
Virtual pins 22 0 0 0 0
I/O pins 105 0 0 0 142
I/O registers 0 0 0 0 232
Total block memory bits 4881024 2271649 4832371 0 0
Total block memory implementation bits 6103040 2949120 6635520 0 0
JTAG 0 / 1 ( 0 % ) 0 / 1 ( 0 % ) 0 / 1 ( 0 % ) 0 / 1 ( 0 % ) 1 / 1 ( 100 % )
M10K block 596 / 2414 ( 24 % ) 288 / 2414 ( 11 % ) 648 / 2414 ( 26 % ) 0 / 2414 ( 0 % ) 0 / 2414 ( 0 % )
DSP block 0 / 1156 ( 0 % ) 0 / 1156 ( 0 % ) 575 / 1156 ( 49 % ) 0 / 1156 ( 0 % ) 0 / 1156 ( 0 % )
Remote update block 0 / 1 ( 0 % ) 0 / 1 ( 0 % ) 0 / 1 ( 0 % ) 0 / 1 ( 0 % ) 1 / 1 ( 100 % )
DLL 0 / 4 ( 0 % ) 0 / 4 ( 0 % ) 0 / 4 ( 0 % ) 0 / 4 ( 0 % ) 1 / 4 ( 25 % )
ASMI block 0 / 1 ( 0 % ) 0 / 1 ( 0 % ) 0 / 1 ( 0 % ) 0 / 1 ( 0 % ) 1 / 1 ( 100 % )
Clock enable block 8 / 352 ( 2 % ) 0 / 352 ( 0 % ) 0 / 352 ( 0 % ) 0 / 352 ( 0 % ) 38 / 352 ( 10 % )
Impedance control block 0 / 4 ( 0 % ) 0 / 4 ( 0 % ) 0 / 4 ( 0 % ) 0 / 4 ( 0 % ) 1 / 4 ( 25 % )
Double data rate I/O output circuitry 0 / 2332 ( 0 % ) 0 / 2332 ( 0 % ) 0 / 2332 ( 0 % ) 0 / 2332 ( 0 % ) 126 / 2332 ( 5 % )
Double data rate I/O input circuitry 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 36 / 704 ( 5 % )
Double data rate I/O output circuitry 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 65 / 704 ( 9 % )
Double data rate I/O output enable circuitry 0 / 748 ( 0 % ) 0 / 748 ( 0 % ) 0 / 748 ( 0 % ) 0 / 748 ( 0 % ) 40 / 748 ( 5 % )
Impedance logic block 0 / 16 ( 0 % ) 0 / 16 ( 0 % ) 0 / 16 ( 0 % ) 0 / 16 ( 0 % ) 2 / 16 ( 12 % )
DQS pin delay chain 0 / 44 ( 0 % ) 0 / 44 ( 0 % ) 0 / 44 ( 0 % ) 0 / 44 ( 0 % ) 2 / 44 ( 4 % )
Delay chain 0 / 2288 ( 0 % ) 0 / 2288 ( 0 % ) 0 / 2288 ( 0 % ) 0 / 2288 ( 0 % ) 117 / 2288 ( 5 % )
Pin configuration 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 39 / 704 ( 5 % )
DQS pin configuration 0 / 44 ( 0 % ) 0 / 44 ( 0 % ) 0 / 44 ( 0 % ) 0 / 44 ( 0 % ) 4 / 44 ( 9 % )
Signal Splitter 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 3 / 704 ( < 1 % )
Leveling delay chain 0 / 64 ( 0 % ) 0 / 64 ( 0 % ) 0 / 64 ( 0 % ) 0 / 64 ( 0 % ) 6 / 64 ( 9 % )
Clock Phase Select 0 / 308 ( 0 % ) 0 / 308 ( 0 % ) 0 / 308 ( 0 % ) 0 / 308 ( 0 % ) 17 / 308 ( 5 % )
PHY Clock Buffer 0 / 12 ( 0 % ) 0 / 12 ( 0 % ) 0 / 12 ( 0 % ) 0 / 12 ( 0 % ) 1 / 12 ( 8 % )
HSSI AVMM Interface 0 / 12 ( 0 % ) 0 / 12 ( 0 % ) 0 / 12 ( 0 % ) 0 / 12 ( 0 % ) 8 / 12 ( 66 % )
Read FIFO Read Clock Select Block 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 36 / 704 ( 5 % )
LFIFO 0 / 44 ( 0 % ) 0 / 44 ( 0 % ) 0 / 44 ( 0 % ) 0 / 44 ( 0 % ) 4 / 44 ( 9 % )
Channel PLL 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 21 / 24 ( 87 % )
Fractional PLL 0 / 16 ( 0 % ) 0 / 16 ( 0 % ) 0 / 16 ( 0 % ) 0 / 16 ( 0 % ) 2 / 16 ( 12 % )
Standard RX PCS 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 17 / 24 ( 70 % )
Standard TX PCS 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 13 / 24 ( 54 % )
HSSI Common PCS PMA Interface 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 17 / 24 ( 70 % )
HSSI Common PLD PCS Interface 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 17 / 24 ( 70 % )
HSSI PMA Aux. block 0 / 2 ( 0 % ) 0 / 2 ( 0 % ) 0 / 2 ( 0 % ) 0 / 2 ( 0 % ) 2 / 2 ( 100 % )
HSSI PMA CDR REFCLK Select Mux 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 21 / 24 ( 87 % )
HSSI PMA RX Buffer 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 17 / 24 ( 70 % )
HSSI PMA RX Deserializer 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 17 / 24 ( 70 % )
HSSI PMA TX Buffer 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 13 / 24 ( 54 % )
Clock Divider 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 13 / 24 ( 54 % )
HSSI PMA TX Serializer 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 13 / 24 ( 54 % )
HSSI refclk divider 0 / 36 ( 0 % ) 0 / 36 ( 0 % ) 0 / 36 ( 0 % ) 0 / 36 ( 0 % ) 3 / 36 ( 8 % )
HSSI RX PCS PMA Interface 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 17 / 24 ( 70 % )
HSSI RX PLD PCS Interface 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 17 / 24 ( 70 % )
HSSI TX PCS PMA Interface 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 13 / 24 ( 54 % )
HSSI TX PLD PCS Interface 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 0 / 24 ( 0 % ) 13 / 24 ( 54 % )
IR FIFO USERDES Block 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 0 / 704 ( 0 % ) 36 / 704 ( 5 % )
PLL DLL Output 0 / 16 ( 0 % ) 0 / 16 ( 0 % ) 0 / 16 ( 0 % ) 0 / 16 ( 0 % ) 1 / 16 ( 6 % )
PLL LVDS Output 0 / 32 ( 0 % ) 0 / 32 ( 0 % ) 0 / 32 ( 0 % ) 0 / 32 ( 0 % ) 2 / 32 ( 6 % )
PLL Output Counter 0 / 144 ( 0 % ) 0 / 144 ( 0 % ) 0 / 144 ( 0 % ) 0 / 144 ( 0 % ) 9 / 144 ( 6 % )
PLL Reconfiguration Block 0 / 16 ( 0 % ) 0 / 16 ( 0 % ) 0 / 16 ( 0 % ) 0 / 16 ( 0 % ) 2 / 16 ( 12 % )
PLL Reference Clock Select Block 0 / 16 ( 0 % ) 0 / 16 ( 0 % ) 0 / 16 ( 0 % ) 0 / 16 ( 0 % ) 2 / 16 ( 12 % )
VFIFO 0 / 44 ( 0 % ) 0 / 44 ( 0 % ) 0 / 44 ( 0 % ) 0 / 44 ( 0 % ) 4 / 44 ( 9 % )
           
Connections          
    -- Input Connections 31342 70703 86507 118 1600
    -- Registered Input Connections 27207 62949 75654 87 0
    -- Output Connections 24470 896 303 239 164362
    -- Registered Output Connections 22588 804 302 238 0
           
Internal Connections          
    -- Total Connections 243667 363755 492273 834 190859
    -- Registered Connections 142804 239479 323982 650 108
           
External Connections          
    -- Top 140 23143 889 244 31396
    -- DataOrganizer:DataOrganizer_inst 23143 0 0 0 48456
    -- TFBlock:TFBlock_inst 889 0 0 0 85921
    -- sld_hub:auto_hub 244 0 0 0 113
    -- hard_block:auto_generated_inst 31396 48456 85921 113 76
           
Partition Interface          
    -- Input Ports 87 685 349 15 2557
    -- Output Ports 53 442 104 33 1827
    -- Bidir Ports 106 0 0 0 0
           
Registered Ports          
    -- Registered Input Ports 0 134 174 3 0
    -- Registered Output Ports 0 389 102 22 0
           
Port Connectivity          
    -- Input Ports driven by GND 0 0 0 5 42
    -- Output Ports driven by GND 0 11 0 1 0
    -- Input Ports driven by VCC 0 0 0 0 0
    -- Output Ports driven by VCC 0 0 0 0 0
    -- Input Ports with no Source 0 0 0 1 0
    -- Output Ports with no Source 0 0 0 0 0
    -- Input Ports with no Fanout 0 159 33 2 1357
    -- Output Ports with no Fanout 0 33 1 22 0