Resource Usage %
Logic utilization (ALMs needed / total ALMs on device) 82,903 / 190,240 44 %
ALMs needed [=A-B+C] 82,903  
    [A] ALMs used in final placement [=a+b+c+d] 102,673 / 190,240 54 %
        [a] ALMs used for LUT logic and registers 34,612  
        [b] ALMs used for LUT logic 22,115  
        [c] ALMs used for registers 36,536  
        [d] ALMs used for memory (up to half of total ALMs) 9,410  
    [B] Estimate of ALMs recoverable by dense packing 21,278 / 190,240 11 %
    [C] Estimate of ALMs unavailable [=a+b+c+d] 1,508 / 190,240 < 1 %
        [a] Due to location constrained logic 21  
        [b] Due to LAB-wide signal conflicts 757  
        [c] Due to LAB input limits 719  
        [d] Due to virtual I/Os 11  
     
Difficulty packing design Low  
     
Total LABs:  partially or completely used 17,151 / 19,024 90 %
    -- Logic LABs 16,210  
    -- Memory LABs (up to half of total LABs) 941  
     
Combinational ALUT usage for logic 98,224  
    -- 7 input functions 487  
    -- 6 input functions 18,628  
    -- 5 input functions 7,862  
    -- 4 input functions 23,390  
    -- <=3 input functions 47,857  
Combinational ALUT usage for route-throughs 36,984  
Memory ALUT usage 14,683  
    -- 64-address deep 0  
    -- 32-address deep 14,683  
     
Dedicated logic registers 145,987  
    -- By type:    
        -- Primary logic registers 142,296 / 380,480 37 %
        -- Secondary logic registers 3,691 / 380,480 < 1 %
    -- By function:    
        -- Design implementation registers 143,767  
        -- Routing optimization registers 2,220  
     
Virtual pins 22  
I/O pins 247 / 656 38 %
    -- Clock pins 11 / 32 34 %
    -- Dedicated input pins 37 / 59 63 %
I/O registers 232  
     
Global signals 48  
M10K blocks 1,532 / 2,414 63 %
Total MLAB memory bits 343,022  
Total block memory bits 11,985,044 / 24,719,360 48 %
Total block memory implementation bits 15,687,680 / 24,719,360 63 %
Total DSP Blocks 575 / 1,156 50 %
Fractional PLLs 2 / 16 13 %
Global clocks 16 / 16 100 %
Quadrant clocks 2 / 88 2 %
Horizontal periphery clocks and Vertical periphery clocks 38 / 248 15 %
SERDES Transmitters 0 / 176 0 %
SERDES Receivers 0 / 176 0 %
JTAGs 1 / 1 100 %
ASMI blocks 1 / 1 100 %
CRC blocks 0 / 1 0 %
Remote update blocks 1 / 1 100 %
Hard IPs 0 / 2 0 %
Standard RX PCSs 17 / 24 71 %
HSSI PMA RX Deserializers 17 / 24 71 %
Standard TX PCSs 13 / 24 54 %
HSSI PMA TX Serializers 13 / 24 54 %
Channel PLLs 21 / 24 88 %
Impedance control blocks 1 / 4 25 %
Hard Memory Controllers 0 / 4 0 %
Average interconnect usage (total/H/V) 29% / 29% / 29%  
Peak interconnect usage (total/H/V) 60% / 59% / 64%  
Maximum fan-out 151544  
Highest non-global fan-out 21309  
Total fan-out 990357  
Average fan-out 3.31