Html last updated 2015-10-06 23:15:15.587363



I1_RxLDC

Compile Started Compile Time Processor AUXCommon Version nInfo nWarnings nErrors fMax[0] fMax[1] Fitter Effort
2015-10-05 22:00:05 1:10:28 1b86d47 4266279 1D 1CEE 5941 312 0 129.03 MHz/100.0 MHz 153.96 MHz/150.02 MHz AUTO
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20151005_231033 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 27,804 / 158,500 ( 18 % )
Total registers 46051
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,073,710 / 21,032,960 ( 48 % )
Total RAM Blocks 1,274 / 2,054 ( 62 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI PMA TX Serializers 20 / 24 ( 83 % )
Total PLLs 15 / 40 ( 38 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 1b86d476ebbc587e946201ab7dcd0afe29adee97
Author: FTK User
Date: Mon Oct 5 15:11:53 2015 -0700

  input 1 to 150 instead of 200 default


commit f9bef6a5159a9e373364c0b8bfa01bfe44f2f58c
Author: FTK User
Date: Wed Sep 23 04:23:39 2015 -0700

  turning off smart recompile

AUXCommon Git Logs


commit 6426627967cbed6d97310d4fc7ed8a370121a18c
Author: unknown
Date: Tue Sep 29 14:05:43 2015 +0200

  bug fix in L1IDsynccheck


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.

2015-10-04 22:00:07 1:02:34 f9bef6a 4266279 1D 1CEE 5941 312 0 141.4 MHz/100.0 MHz 158.83 MHz/200.0 MHz AUTO
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20151004_230241 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 28,158 / 158,500 ( 18 % )
Total registers 46299
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,073,710 / 21,032,960 ( 48 % )
Total RAM Blocks 1,274 / 2,054 ( 62 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI PMA TX Serializers 20 / 24 ( 83 % )
Total PLLs 15 / 40 ( 38 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit f9bef6a5159a9e373364c0b8bfa01bfe44f2f58c
Author: FTK User
Date: Wed Sep 23 04:23:39 2015 -0700

  turning off smart recompile


commit ffec1a87d547be2fdc64bbe306dc862f013f0c7c
Author: FTK User
Date: Wed Sep 23 04:13:31 2015 -0700

  don't know why this file disappeared

AUXCommon Git Logs


commit 6426627967cbed6d97310d4fc7ed8a370121a18c
Author: unknown
Date: Tue Sep 29 14:05:43 2015 +0200

  bug fix in L1IDsynccheck


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.

2015-10-03 22:00:07 1:03:21 f9bef6a 4266279 1D 1CEE 5941 312 0 141.4 MHz/100.0 MHz 158.83 MHz/200.0 MHz AUTO
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20151003_230328 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 28,158 / 158,500 ( 18 % )
Total registers 46299
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,073,710 / 21,032,960 ( 48 % )
Total RAM Blocks 1,274 / 2,054 ( 62 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI PMA TX Serializers 20 / 24 ( 83 % )
Total PLLs 15 / 40 ( 38 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit f9bef6a5159a9e373364c0b8bfa01bfe44f2f58c
Author: FTK User
Date: Wed Sep 23 04:23:39 2015 -0700

  turning off smart recompile


commit ffec1a87d547be2fdc64bbe306dc862f013f0c7c
Author: FTK User
Date: Wed Sep 23 04:13:31 2015 -0700

  don't know why this file disappeared

AUXCommon Git Logs


commit 6426627967cbed6d97310d4fc7ed8a370121a18c
Author: unknown
Date: Tue Sep 29 14:05:43 2015 +0200

  bug fix in L1IDsynccheck


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.

2015-10-02 22:00:07 1:02:52 f9bef6a 4266279 1D 1CEE 5941 312 0 141.4 MHz/100.0 MHz 158.83 MHz/200.0 MHz AUTO
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20151002_230259 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 28,158 / 158,500 ( 18 % )
Total registers 46299
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,073,710 / 21,032,960 ( 48 % )
Total RAM Blocks 1,274 / 2,054 ( 62 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI PMA TX Serializers 20 / 24 ( 83 % )
Total PLLs 15 / 40 ( 38 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit f9bef6a5159a9e373364c0b8bfa01bfe44f2f58c
Author: FTK User
Date: Wed Sep 23 04:23:39 2015 -0700

  turning off smart recompile


commit ffec1a87d547be2fdc64bbe306dc862f013f0c7c
Author: FTK User
Date: Wed Sep 23 04:13:31 2015 -0700

  don't know why this file disappeared

AUXCommon Git Logs


commit 6426627967cbed6d97310d4fc7ed8a370121a18c
Author: unknown
Date: Tue Sep 29 14:05:43 2015 +0200

  bug fix in L1IDsynccheck


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.

2015-10-01 22:00:07 1:03:17 f9bef6a 4266279 1D 1CEE 5941 312 0 141.4 MHz/100.0 MHz 158.83 MHz/200.0 MHz AUTO
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20151001_230324 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 28,158 / 158,500 ( 18 % )
Total registers 46299
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,073,710 / 21,032,960 ( 48 % )
Total RAM Blocks 1,274 / 2,054 ( 62 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI PMA TX Serializers 20 / 24 ( 83 % )
Total PLLs 15 / 40 ( 38 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit f9bef6a5159a9e373364c0b8bfa01bfe44f2f58c
Author: FTK User
Date: Wed Sep 23 04:23:39 2015 -0700

  turning off smart recompile


commit ffec1a87d547be2fdc64bbe306dc862f013f0c7c
Author: FTK User
Date: Wed Sep 23 04:13:31 2015 -0700

  don't know why this file disappeared

AUXCommon Git Logs


commit 6426627967cbed6d97310d4fc7ed8a370121a18c
Author: unknown
Date: Tue Sep 29 14:05:43 2015 +0200

  bug fix in L1IDsynccheck


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.

2015-09-30 22:00:07 1:02:42 f9bef6a 4266279 1D 1CEE 5941 312 0 141.4 MHz/100.0 MHz 158.83 MHz/200.0 MHz AUTO
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150930_230249 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 28,158 / 158,500 ( 18 % )
Total registers 46299
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,073,710 / 21,032,960 ( 48 % )
Total RAM Blocks 1,274 / 2,054 ( 62 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI PMA TX Serializers 20 / 24 ( 83 % )
Total PLLs 15 / 40 ( 38 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit f9bef6a5159a9e373364c0b8bfa01bfe44f2f58c
Author: FTK User
Date: Wed Sep 23 04:23:39 2015 -0700

  turning off smart recompile


commit ffec1a87d547be2fdc64bbe306dc862f013f0c7c
Author: FTK User
Date: Wed Sep 23 04:13:31 2015 -0700

  don't know why this file disappeared

AUXCommon Git Logs


commit 6426627967cbed6d97310d4fc7ed8a370121a18c
Author: unknown
Date: Tue Sep 29 14:05:43 2015 +0200

  bug fix in L1IDsynccheck


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.

2015-09-29 22:00:07 1:03:22 f9bef6a 4266279 1D 1CEE 5941 312 0 141.4 MHz/100.0 MHz 158.83 MHz/200.0 MHz AUTO
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150929_230329 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 28,158 / 158,500 ( 18 % )
Total registers 46299
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,073,710 / 21,032,960 ( 48 % )
Total RAM Blocks 1,274 / 2,054 ( 62 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI PMA TX Serializers 20 / 24 ( 83 % )
Total PLLs 15 / 40 ( 38 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit f9bef6a5159a9e373364c0b8bfa01bfe44f2f58c
Author: FTK User
Date: Wed Sep 23 04:23:39 2015 -0700

  turning off smart recompile


commit ffec1a87d547be2fdc64bbe306dc862f013f0c7c
Author: FTK User
Date: Wed Sep 23 04:13:31 2015 -0700

  don't know why this file disappeared

AUXCommon Git Logs


commit 6426627967cbed6d97310d4fc7ed8a370121a18c
Author: unknown
Date: Tue Sep 29 14:05:43 2015 +0200

  bug fix in L1IDsynccheck


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.

2015-09-28 22:00:07 1:00:20 f9bef6a d4193c3 1D 1CEE 5941 312 0 145.56 MHz/100.0 MHz 168.07 MHz/200.0 MHz AUTO
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150928_230027 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 28,247 / 158,500 ( 18 % )
Total registers 46330
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,073,710 / 21,032,960 ( 48 % )
Total RAM Blocks 1,274 / 2,054 ( 62 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI PMA TX Serializers 20 / 24 ( 83 % )
Total PLLs 15 / 40 ( 38 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit f9bef6a5159a9e373364c0b8bfa01bfe44f2f58c
Author: FTK User
Date: Wed Sep 23 04:23:39 2015 -0700

  turning off smart recompile


commit ffec1a87d547be2fdc64bbe306dc862f013f0c7c
Author: FTK User
Date: Wed Sep 23 04:13:31 2015 -0700

  don't know why this file disappeared

AUXCommon Git Logs


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.

2015-09-27 22:00:07 0:59:00 f9bef6a d4193c3 1D 1CEE 5941 312 0 145.56 MHz/100.0 MHz 168.07 MHz/200.0 MHz AUTO
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150927_225907 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 28,247 / 158,500 ( 18 % )
Total registers 46330
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,073,710 / 21,032,960 ( 48 % )
Total RAM Blocks 1,274 / 2,054 ( 62 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI PMA TX Serializers 20 / 24 ( 83 % )
Total PLLs 15 / 40 ( 38 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit f9bef6a5159a9e373364c0b8bfa01bfe44f2f58c
Author: FTK User
Date: Wed Sep 23 04:23:39 2015 -0700

  turning off smart recompile


commit ffec1a87d547be2fdc64bbe306dc862f013f0c7c
Author: FTK User
Date: Wed Sep 23 04:13:31 2015 -0700

  don't know why this file disappeared

AUXCommon Git Logs


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.

2015-09-26 22:00:07 0:56:50 f9bef6a d4193c3 1D 1CEE 5941 312 0 145.56 MHz/100.0 MHz 168.07 MHz/200.0 MHz AUTO
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150926_225657 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 28,247 / 158,500 ( 18 % )
Total registers 46330
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,073,710 / 21,032,960 ( 48 % )
Total RAM Blocks 1,274 / 2,054 ( 62 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI PMA TX Serializers 20 / 24 ( 83 % )
Total PLLs 15 / 40 ( 38 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit f9bef6a5159a9e373364c0b8bfa01bfe44f2f58c
Author: FTK User
Date: Wed Sep 23 04:23:39 2015 -0700

  turning off smart recompile


commit ffec1a87d547be2fdc64bbe306dc862f013f0c7c
Author: FTK User
Date: Wed Sep 23 04:13:31 2015 -0700

  don't know why this file disappeared

AUXCommon Git Logs


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.

2015-09-25 22:00:07 0:58:16 f9bef6a d4193c3 1D 1CEE 5941 312 0 145.56 MHz/100.0 MHz 168.07 MHz/200.0 MHz AUTO
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150925_225823 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 28,247 / 158,500 ( 18 % )
Total registers 46330
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,073,710 / 21,032,960 ( 48 % )
Total RAM Blocks 1,274 / 2,054 ( 62 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI PMA TX Serializers 20 / 24 ( 83 % )
Total PLLs 15 / 40 ( 38 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit f9bef6a5159a9e373364c0b8bfa01bfe44f2f58c
Author: FTK User
Date: Wed Sep 23 04:23:39 2015 -0700

  turning off smart recompile


commit ffec1a87d547be2fdc64bbe306dc862f013f0c7c
Author: FTK User
Date: Wed Sep 23 04:13:31 2015 -0700

  don't know why this file disappeared

AUXCommon Git Logs


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.

2015-09-24 22:00:07 0:56:44 f9bef6a c30e857 1D 1CEE 5941 312 0 145.56 MHz/100.0 MHz 168.07 MHz/200.0 MHz AUTO
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150924_225651 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 28,247 / 158,500 ( 18 % )
Total registers 46330
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,073,710 / 21,032,960 ( 48 % )
Total RAM Blocks 1,274 / 2,054 ( 62 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI PMA TX Serializers 20 / 24 ( 83 % )
Total PLLs 15 / 40 ( 38 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit f9bef6a5159a9e373364c0b8bfa01bfe44f2f58c
Author: FTK User
Date: Wed Sep 23 04:23:39 2015 -0700

  turning off smart recompile


commit ffec1a87d547be2fdc64bbe306dc862f013f0c7c
Author: FTK User
Date: Wed Sep 23 04:13:31 2015 -0700

  don't know why this file disappeared

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-24 04:56:07 0:03:10 f9bef6a c30e857 N/A 0 0 2 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150924_045917 .

Leading Errors

Error (213009): File name "Rx.sof" does not exist or can't be read
Error (213009): File name "I1_RxLDC.pof" does not exist or can't be read

Processor Git Logs


commit f9bef6a5159a9e373364c0b8bfa01bfe44f2f58c
Author: FTK User
Date: Wed Sep 23 04:23:39 2015 -0700

  turning off smart recompile


commit ffec1a87d547be2fdc64bbe306dc862f013f0c7c
Author: FTK User
Date: Wed Sep 23 04:13:31 2015 -0700

  don't know why this file disappeared

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-23 22:00:08 0:03:14 f9bef6a c30e857 N/A 2723 69 17 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150923_220322 .

Leading Errors

Error (12002): Port "aclr" does not exist in macrofunction "gen_cntr" File: D:/Projects/ftk/Nightlies/AUXCommon/remote_update/epcqio.vhd Line: 1934
Error (12002): Port "clk_en" does not exist in macrofunction "gen_cntr" File: D:/Projects/ftk/Nightlies/AUXCommon/remote_update/epcqio.vhd Line: 1934
Error (12002): Port "clock" does not exist in macrofunction "gen_cntr" File: D:/Projects/ftk/Nightlies/AUXCommon/remote_update/epcqio.vhd Line: 1934
Error (12002): Port "q[0]" does not exist in macrofunction "gen_cntr" File: D:/Projects/ftk/Nightlies/AUXCommon/remote_update/epcqio.vhd Line: 1934
Error (12002): Port "q[1]" does not exist in macrofunction "gen_cntr" File: D:/Projects/ftk/Nightlies/AUXCommon/remote_update/epcqio.vhd Line: 1934
Error (12002): Port "q[2]" does not exist in macrofunction "gen_cntr" File: D:/Projects/ftk/Nightlies/AUXCommon/remote_update/epcqio.vhd Line: 1934
Error (12002): Port "sclr" does not exist in macrofunction "gen_cntr" File: D:/Projects/ftk/Nightlies/AUXCommon/remote_update/epcqio.vhd Line: 1934
Error (12002): Port "aclr" does not exist in macrofunction "addbyte_cntr" File: D:/Projects/ftk/Nightlies/AUXCommon/remote_update/epcqio.vhd Line: 1915
Error (12002): Port "clk_en" does not exist in macrofunction "addbyte_cntr" File: D:/Projects/ftk/Nightlies/AUXCommon/remote_update/epcqio.vhd Line: 1915
Error (12002): Port "clock" does not exist in macrofunction "addbyte_cntr" File: D:/Projects/ftk/Nightlies/AUXCommon/remote_update/epcqio.vhd Line: 1915
Error (12002): Port "q[0]" does not exist in macrofunction "addbyte_cntr" File: D:/Projects/ftk/Nightlies/AUXCommon/remote_update/epcqio.vhd Line: 1915
...

Processor Git Logs


commit f9bef6a5159a9e373364c0b8bfa01bfe44f2f58c
Author: FTK User
Date: Wed Sep 23 04:23:39 2015 -0700

  turning off smart recompile


commit ffec1a87d547be2fdc64bbe306dc862f013f0c7c
Author: FTK User
Date: Wed Sep 23 04:13:31 2015 -0700

  don't know why this file disappeared

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-23 04:26:35 1:27:39 f9bef6a c30e857 1D 1CEE 5941 312 0 145.56 MHz/100.0 MHz 168.07 MHz/200.0 MHz AUTO
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150923_055414 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 28,247 / 158,500 ( 18 % )
Total registers 46330
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,073,710 / 21,032,960 ( 48 % )
Total RAM Blocks 1,274 / 2,054 ( 62 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI PMA TX Serializers 20 / 24 ( 83 % )
Total PLLs 15 / 40 ( 38 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit f9bef6a5159a9e373364c0b8bfa01bfe44f2f58c
Author: FTK User
Date: Wed Sep 23 04:23:39 2015 -0700

  turning off smart recompile


commit ffec1a87d547be2fdc64bbe306dc862f013f0c7c
Author: FTK User
Date: Wed Sep 23 04:13:31 2015 -0700

  don't know why this file disappeared

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-23 04:14:22 0:00:48 ffec1a8 c30e857 N/A 7 1 2 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150923_041510 .

Leading Errors

Error (213009): File name "Rx.sof" does not exist or can't be read
Error (213009): File name "I1_RxLDC.pof" does not exist or can't be read

Processor Git Logs


commit ffec1a87d547be2fdc64bbe306dc862f013f0c7c
Author: FTK User
Date: Wed Sep 23 04:13:31 2015 -0700

  don't know why this file disappeared


commit e5cd6c892c79c411467bcabe11c716fa9349a472
Author: FTK User
Date: Mon Sep 21 08:14:04 2015 -0700

  switch nightly compile ot 15

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-22 22:00:08 0:00:34 e5cd6c8 c30e857 N/A 7 1 2 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150922_220042 .

Leading Errors

Error (213009): File name "Rx.sof" does not exist or can't be read
Error (213009): File name "I1_RxLDC.pof" does not exist or can't be read

Processor Git Logs


commit e5cd6c892c79c411467bcabe11c716fa9349a472
Author: FTK User
Date: Mon Sep 21 08:14:04 2015 -0700

  switch nightly compile ot 15


commit 1fc875aaf2ea912633609e12fe896d3b02a6f7da
Author: Karol Krizka
Date: Fri Sep 18 11:01:53 2015 +0200

  Added scrited compiles to I1.

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-21 22:00:06 0:57:09 e5cd6c8 c30e857 1D 1CEE 5941 314 0 145.56 MHz/100.0 MHz 168.07 MHz/200.0 MHz AUTO
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150921_225715 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 28,247 / 158,500 ( 18 % )
Total registers 46330
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,073,710 / 21,032,960 ( 48 % )
Total RAM Blocks 1,274 / 2,054 ( 62 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI PMA TX Serializers 20 / 24 ( 83 % )
Total PLLs 15 / 40 ( 38 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit e5cd6c892c79c411467bcabe11c716fa9349a472
Author: FTK User
Date: Mon Sep 21 08:14:04 2015 -0700

  switch nightly compile ot 15


commit 1fc875aaf2ea912633609e12fe896d3b02a6f7da
Author: Karol Krizka
Date: Fri Sep 18 11:01:53 2015 +0200

  Added scrited compiles to I1.

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-20 22:00:07 0:00:22 1fc875a c30e857 N/A 31 0 34 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150920_220029 .

Leading Errors

Error (125036): Assignment value SINGLE IMAGE for assignment INTERNAL_FLASH_UPDATE_MODE is illegal File: D:/Projects/ftk/Nightlies/Input1_new/RxLDC/Rx.qsf Line: 437
Error (125048): Error reading Quartus II Settings File D:/Projects/ftk/Nightlies/Input1_new/RxLDC/Rx.qsf, line 511 File: D:/Projects/ftk/Nightlies/Input1_new/RxLDC/Rx.qsf Line: 511
Error (125048): Error reading Quartus II Settings File D:/Projects/ftk/Nightlies/Input1_new/RxLDC/Rx.qsf, line 512 File: D:/Projects/ftk/Nightlies/Input1_new/RxLDC/Rx.qsf Line: 512
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 1fc875aaf2ea912633609e12fe896d3b02a6f7da
Author: Karol Krizka
Date: Fri Sep 18 11:01:53 2015 +0200

  Added scrited compiles to I1.


commit 02f785a980a37266cc992dbe36b1d479b2cfeef0
Author: Karol Krizka
Date: Mon Aug 31 15:09:25 2015 +0200

  Add aux_dcfifo to RxLDC qsf.

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-19 22:00:06 0:00:22 1fc875a c30e857 N/A 31 0 34 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150919_220028 .

Leading Errors

Error (125036): Assignment value SINGLE IMAGE for assignment INTERNAL_FLASH_UPDATE_MODE is illegal File: D:/Projects/ftk/Nightlies/Input1_new/RxLDC/Rx.qsf Line: 437
Error (125048): Error reading Quartus II Settings File D:/Projects/ftk/Nightlies/Input1_new/RxLDC/Rx.qsf, line 511 File: D:/Projects/ftk/Nightlies/Input1_new/RxLDC/Rx.qsf Line: 511
Error (125048): Error reading Quartus II Settings File D:/Projects/ftk/Nightlies/Input1_new/RxLDC/Rx.qsf, line 512 File: D:/Projects/ftk/Nightlies/Input1_new/RxLDC/Rx.qsf Line: 512
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 1fc875aaf2ea912633609e12fe896d3b02a6f7da
Author: Karol Krizka
Date: Fri Sep 18 11:01:53 2015 +0200

  Added scrited compiles to I1.


commit 02f785a980a37266cc992dbe36b1d479b2cfeef0
Author: Karol Krizka
Date: Mon Aug 31 15:09:25 2015 +0200

  Add aux_dcfifo to RxLDC qsf.

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-18 22:00:08 0:01:29 1fc875a c30e857 N/A 31 0 34 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150918_220137 .

Leading Errors

Error (125036): Assignment value SINGLE IMAGE for assignment INTERNAL_FLASH_UPDATE_MODE is illegal File: D:/Projects/ftk/Nightlies/Input1_new/RxLDC/Rx.qsf Line: 437
Error (125048): Error reading Quartus II Settings File D:/Projects/ftk/Nightlies/Input1_new/RxLDC/Rx.qsf, line 511 File: D:/Projects/ftk/Nightlies/Input1_new/RxLDC/Rx.qsf Line: 511
Error (125048): Error reading Quartus II Settings File D:/Projects/ftk/Nightlies/Input1_new/RxLDC/Rx.qsf, line 512 File: D:/Projects/ftk/Nightlies/Input1_new/RxLDC/Rx.qsf Line: 512
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 1fc875aaf2ea912633609e12fe896d3b02a6f7da
Author: Karol Krizka
Date: Fri Sep 18 11:01:53 2015 +0200

  Added scrited compiles to I1.


commit 02f785a980a37266cc992dbe36b1d479b2cfeef0
Author: Karol Krizka
Date: Mon Aug 31 15:09:25 2015 +0200

  Add aux_dcfifo to RxLDC qsf.

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-17 22:00:08 0:01:05 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150917_220113 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-16 22:00:08 0:01:01 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150916_220109 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-15 22:00:08 0:00:59 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150915_220107 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-14 22:00:07 0:01:01 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150914_220108 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-13 22:00:08 0:01:05 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150913_220113 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-12 22:00:08 0:01:01 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150912_220109 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-11 22:00:08 0:01:23 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150911_220131 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-10 22:00:08 0:01:04 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150910_220112 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-09 22:00:08 0:01:05 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150909_220113 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-08 22:00:08 0:01:06 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150908_220114 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-07 22:00:08 0:01:07 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150907_220115 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-06 22:00:08 0:01:13 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150906_220121 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-05 22:00:08 0:01:05 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150905_220113 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-04 22:00:08 0:01:05 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150904_220113 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-03 22:00:08 0:01:07 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150903_220115 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-02 22:00:10 0:01:02 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150902_220112 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-01 22:00:08 0:01:06 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150901_220114 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-08-31 22:00:08 0:01:25 2ccba2d 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150831_220133 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-08-17 22:00:07 0:52:35 2ccba2d 309e0b2 1D 1A5D 6552 439 0 146.13 MHz/100.0 MHz 162.44 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150817_225242 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,685 / 158,500 ( 19 % )
Total registers 48803
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-16 22:00:08 0:53:12 2ccba2d 309e0b2 1D 1A45 6552 439 0 137.68 MHz/100.0 MHz 163.43 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150816_225320 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,771 / 158,500 ( 19 % )
Total registers 48843
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-15 22:00:08 0:51:44 2ccba2d 309e0b2 1D 1A2D 6552 439 0 146.2 MHz/100.0 MHz 162.47 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150815_225152 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,733 / 158,500 ( 19 % )
Total registers 48845
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-14 22:00:08 0:51:02 2ccba2d 309e0b2 1D 1A15 6552 439 0 130.72 MHz/100.0 MHz 159.62 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150814_225110 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,804 / 158,500 ( 19 % )
Total registers 48884
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-13 22:00:08 1:08:11 2ccba2d 309e0b2 1D 19FD 6552 439 0 134.99 MHz/100.0 MHz 164.07 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150813_230819 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,770 / 158,500 ( 19 % )
Total registers 48910
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-12 22:00:08 1:14:03 2ccba2d 309e0b2 1D 19E5 6552 439 0 140.94 MHz/100.0 MHz 159.67 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150812_231411 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,748 / 158,500 ( 19 % )
Total registers 48859
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-11 22:00:08 1:14:49 2ccba2d 309e0b2 1D 19CD 6552 439 0 135.32 MHz/100.0 MHz 162.87 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150811_231457 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,796 / 158,500 ( 19 % )
Total registers 48929
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-10 22:00:07 1:13:42 2ccba2d 309e0b2 1D 19B5 6552 439 0 146.24 MHz/100.0 MHz 160.15 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150810_231349 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,846 / 158,500 ( 19 % )
Total registers 48902
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-09 22:00:08 1:13:46 2ccba2d 309e0b2 1D 199D 6552 439 0 151.15 MHz/100.0 MHz 161.0 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150809_231354 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,698 / 158,500 ( 19 % )
Total registers 48896
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-08 22:00:08 1:14:08 2ccba2d 309e0b2 1D 1985 6552 439 0 138.97 MHz/100.0 MHz 157.58 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150808_231416 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,744 / 158,500 ( 19 % )
Total registers 48844
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-07 22:00:07 1:08:30 2ccba2d 309e0b2 1D 196D 6552 439 0 141.8 MHz/100.0 MHz 159.41 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150807_230837 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,730 / 158,500 ( 19 % )
Total registers 48863
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-06 22:00:06 0:55:02 2ccba2d 309e0b2 1D 1955 6552 439 0 143.2 MHz/100.0 MHz 166.22 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150806_225508 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,728 / 158,500 ( 19 % )
Total registers 48862
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-05 22:00:08 1:02:42 2ccba2d 309e0b2 1D 193D 6552 439 0 147.12 MHz/100.0 MHz 161.32 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150805_230250 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,768 / 158,500 ( 19 % )
Total registers 48909
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-04 22:00:08 1:02:18 2ccba2d 309e0b2 1D 1925 6552 439 0 137.8 MHz/100.0 MHz 157.88 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150804_230226 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,740 / 158,500 ( 19 % )
Total registers 48894
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-03 22:00:07 0:53:43 2ccba2d 309e0b2 1D 190D 6552 439 0 142.13 MHz/100.0 MHz 164.83 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150803_225350 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,729 / 158,500 ( 19 % )
Total registers 48833
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-02 22:00:07 1:13:15 2ccba2d 309e0b2 1D 18F5 6552 439 0 144.7 MHz/100.0 MHz 151.72 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150802_231322 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,796 / 158,500 ( 19 % )
Total registers 48853
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-01 22:00:08 1:11:41 2ccba2d 309e0b2 1D 18DD 6552 439 0 145.05 MHz/100.0 MHz 147.08 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150801_231149 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,780 / 158,500 ( 19 % )
Total registers 48872
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-07-31 22:00:08 1:11:32 2ccba2d 309e0b2 1D 18C5 6552 439 0 136.43 MHz/100.0 MHz 159.9 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150731_231140 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,794 / 158,500 ( 19 % )
Total registers 48897
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-07-30 22:00:06 1:08:32 2ccba2d 309e0b2 1D 18AD 6552 439 0 142.41 MHz/100.0 MHz 159.85 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150730_230838 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,749 / 158,500 ( 19 % )
Total registers 48850
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-07-29 22:00:06 0:58:08 2ccba2d 309e0b2 1D 1895 6552 439 0 152.42 MHz/100.0 MHz 156.3 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150729_225814 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,747 / 158,500 ( 19 % )
Total registers 48840
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-07-28 22:00:08 0:57:35 2ccba2d 309e0b2 1D 187D 6552 439 0 137.25 MHz/100.0 MHz 167.22 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150728_225743 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,685 / 158,500 ( 19 % )
Total registers 48899
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-07-27 22:00:07 1:08:11 2ccba2d 309e0b2 1D 1865 6552 439 0 138.77 MHz/100.0 MHz 159.44 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150727_230818 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,868 / 158,500 ( 19 % )
Total registers 48844
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-07-26 22:00:08 0:58:08 2ccba2d 309e0b2 1D 184D 6618 439 0 131.03 MHz/100.0 MHz 163.85 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150726_225816 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 30,753 / 158,500 ( 19 % )
Total registers 48891
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,089,186 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 2ccba2d86b98a94c6b76958f7409483301d842f8
Author: Karol Krizka
Date: Sun Jul 26 15:42:30 2015 +0200

  AMB L1ID sync check.


commit 5ecf1cc723c5c1f4e56a7ca8063cfee54e76fea1
Author: Karol Krizka
Date: Sat Jul 18 17:48:36 2015 +0200

  Connect unused statuses.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-07-25 22:00:08 0:56:39 f7198f9 ac61546 1D 1835 6536 419 0 136.39 MHz/100.0 MHz 160.0 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150725_225647 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 29,699 / 158,500 ( 19 % )
Total registers 46726
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,084,592 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit f7198f9ce3a32abde07d39f988a92bbaf1cb1ce6
Author: U-ELECSHOP\ftk
Date: Fri Jul 24 09:55:14 2015 -0700

  copy to the right spot


commit b439e8835177977521221e21ce172b4ab3a86bb0
Author: U-ELECSHOP\ftk
Date: Wed Jul 22 08:19:50 2015 -0700

  don't remove

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-24 22:00:08 0:56:29 f7198f9 ac61546 1D 181D 6536 419 0 130.16 MHz/100.0 MHz 165.4 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150724_225637 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 29,742 / 158,500 ( 19 % )
Total registers 46740
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,084,592 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit f7198f9ce3a32abde07d39f988a92bbaf1cb1ce6
Author: U-ELECSHOP\ftk
Date: Fri Jul 24 09:55:14 2015 -0700

  copy to the right spot


commit b439e8835177977521221e21ce172b4ab3a86bb0
Author: U-ELECSHOP\ftk
Date: Wed Jul 22 08:19:50 2015 -0700

  don't remove

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-24 09:58:25 0:54:40 f7198f9 ac61546 1D 1811 6536 419 0 132.01 MHz/100.0 MHz 166.97 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150724_105305 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 29,683 / 158,500 ( 19 % )
Total registers 46669
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,084,592 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit f7198f9ce3a32abde07d39f988a92bbaf1cb1ce6
Author: U-ELECSHOP\ftk
Date: Fri Jul 24 09:55:14 2015 -0700

  copy to the right spot


commit b439e8835177977521221e21ce172b4ab3a86bb0
Author: U-ELECSHOP\ftk
Date: Wed Jul 22 08:19:50 2015 -0700

  don't remove

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-22 08:20:24 1:01:03 b439e88 ac61546 1D 17DF 6536 419 0 122.2 MHz/100.0 MHz 165.23 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150722_092127 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 29,739 / 158,500 ( 19 % )
Total registers 46708
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,084,592 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit b439e8835177977521221e21ce172b4ab3a86bb0
Author: U-ELECSHOP\ftk
Date: Wed Jul 22 08:19:50 2015 -0700

  don't remove


commit daa625d42abe0f36430bf4e36e9dda6bf08094e2
Author: U-ELECSHOP\ftk
Date: Wed Jul 22 07:06:57 2015 -0700

  on this windows bash wants y:

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-22 04:51:05 1:08:27 69a9712 ac61546 1D 17DB 6537 419 0 136.28 MHz/100.0 MHz 158.6 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150722_055932 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 29,781 / 158,500 ( 19 % )
Total registers 46698
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,084,592 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 69a971229213c0c876d00c0cd2a23bfede03e1ff
Author: U-ELECSHOP\ftk
Date: Wed Jul 22 03:15:41 2015 -0700

  struggle to get the copies to work


commit 5831ed174d754f58a564a5e4cfb2701f480a4a74
Author: U-ELECSHOP\ftk
Date: Mon Jul 20 07:52:16 2015 -0700

  moving instead of copying

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-21 22:00:09 1:04:25 5831ed1 ac61546 1D 17D5 6537 419 0 136.59 MHz/100.0 MHz 159.77 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150721_230434 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 29,689 / 158,500 ( 19 % )
Total registers 46691
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,084,592 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 5831ed174d754f58a564a5e4cfb2701f480a4a74
Author: U-ELECSHOP\ftk
Date: Mon Jul 20 07:52:16 2015 -0700

  moving instead of copying


commit edf51d9120be5591cf64c35abaa65070d96e693d
Author: Jamie Saxon
Date: Fri Jul 17 12:51:32 2015 +0200

  compile versioning

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-21 08:29:41 1:04:06 5831ed1 ac61546 1D 17C7 6536 419 0 122.74 MHz/100.0 MHz 161.37 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150721_093347 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 29,724 / 158,500 ( 19 % )
Total registers 46772
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,084,592 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 5831ed174d754f58a564a5e4cfb2701f480a4a74
Author: U-ELECSHOP\ftk
Date: Mon Jul 20 07:52:16 2015 -0700

  moving instead of copying


commit edf51d9120be5591cf64c35abaa65070d96e693d
Author: Jamie Saxon
Date: Fri Jul 17 12:51:32 2015 +0200

  compile versioning

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-20 07:52:25 1:04:21 5831ed1 ac61546 1D 17AE 6536 419 0 132.15 MHz/100.0 MHz 164.37 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150720_085646 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 29,710 / 158,500 ( 19 % )
Total registers 46746
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,084,592 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 5831ed174d754f58a564a5e4cfb2701f480a4a74
Author: U-ELECSHOP\ftk
Date: Mon Jul 20 07:52:16 2015 -0700

  moving instead of copying


commit edf51d9120be5591cf64c35abaa65070d96e693d
Author: Jamie Saxon
Date: Fri Jul 17 12:51:32 2015 +0200

  compile versioning

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-20 04:54:33 1:05:35 edf51d9 ac61546 1D 17AB 6536 419 0 135.06 MHz/100.0 MHz 161.66 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150720_060008 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 29,679 / 158,500 ( 19 % )
Total registers 46741
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,084,592 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit edf51d9120be5591cf64c35abaa65070d96e693d
Author: Jamie Saxon
Date: Fri Jul 17 12:51:32 2015 +0200

  compile versioning


commit 13352d3824acbd682ed8e151b1405419331eb69c
Author: U-ELECSHOP\ftk
Date: Thu Jul 16 11:25:10 2015 -0700

  fixing compile.sh for ftk account

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-17 05:53:13 1:00:03 edf51d9 ac61546 1D 1764 6538 419 0 - - STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150717_065316 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 29,746 / 158,500 ( 19 % )
Total registers 46706
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,084,592 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit edf51d9120be5591cf64c35abaa65070d96e693d
Author: Jamie Saxon
Date: Fri Jul 17 12:51:32 2015 +0200

  compile versioning


commit 13352d3824acbd682ed8e151b1405419331eb69c
Author: U-ELECSHOP\ftk
Date: Thu Jul 16 11:25:10 2015 -0700

  fixing compile.sh for ftk account

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-15 22:00:09 0:58:39 175d04d ac61546 1D 01 0E 6536 419 0 139.47 MHz/100.0 MHz 162.28 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150715_225848 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 29,739 / 158,500 ( 19 % )
Total registers 46646
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,084,592 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 175d04dd35d97bed6cbd8e4e6fe31bd7748a9e75
Author: U-ELECSHOP\ftk
Date: Tue Jul 14 15:25:30 2015 -0700

  changes for ftk account


commit 5024102ab870390449d93e54bf70985f9561a0db
Author: Jamie Saxon
Date: Wed Jul 8 03:23:21 2015 -0700

  compile script: point to right log

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-15 10:48:14 1:12:18 175d04d ac61546 1D 01 0E 6536 419 0 139.47 MHz/100.0 MHz 162.28 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150715_120032 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 29,739 / 158,500 ( 19 % )
Total registers 46646
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,084,592 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 175d04dd35d97bed6cbd8e4e6fe31bd7748a9e75
Author: U-ELECSHOP\ftk
Date: Tue Jul 14 15:25:30 2015 -0700

  changes for ftk account


commit 5024102ab870390449d93e54bf70985f9561a0db
Author: Jamie Saxon
Date: Wed Jul 8 03:23:21 2015 -0700

  compile script: point to right log

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-15 04:00:40 1:14:01 175d04d ac61546 1D 01 0E 6530 421 0 139.47 MHz/100.0 MHz 162.28 MHz/160.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I1_RxLDC_20150715_051441 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 29,739 / 158,500 ( 19 % )
Total registers 46646
Total pins 189 / 656 ( 29 % )
Total virtual pins 0
Total block memory bits 10,084,592 / 21,032,960 ( 48 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 4 / 24 ( 17 % )
Total HSSI PMA RX Deserializers 4 / 24 ( 17 % )
Total HSSI TX PCSs 20 / 24 ( 83 % )
Total HSSI TX Channels 20 / 24 ( 83 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 175d04dd35d97bed6cbd8e4e6fe31bd7748a9e75
Author: U-ELECSHOP\ftk
Date: Tue Jul 14 15:25:30 2015 -0700

  changes for ftk account


commit 5024102ab870390449d93e54bf70985f9561a0db
Author: Jamie Saxon
Date: Wed Jul 8 03:23:21 2015 -0700

  compile script: point to right log

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.



I2_RxLDC

Compile Started Compile Time Processor AUXCommon Version nInfo nWarnings nErrors fMax[0] fMax[1] Fitter Effort
2015-10-06 20:00:08 0:51:55 c878d24 4266279 2D 1F0B 6177 864 0 117.87 MHz/100.0 MHz 159.87 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20151006_205203 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 31,732 / 158,500 ( 20 % )
Total registers 64709
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,155,348 / 21,032,960 ( 29 % )
Total RAM Blocks 848 / 2,054 ( 41 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI PMA TX Serializers 17 / 24 ( 71 % )
Total PLLs 14 / 40 ( 35 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit c878d24337b558fab34fc6e7d0753f0e5d8acf58
Author: Karol Krizka
Date: Wed Sep 23 11:42:52 2015 +0200

  Updated to Q15. Added improves support for ROS dumping.


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15

AUXCommon Git Logs


commit 6426627967cbed6d97310d4fc7ed8a370121a18c
Author: unknown
Date: Tue Sep 29 14:05:43 2015 +0200

  bug fix in L1IDsynccheck


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.

2015-10-05 20:00:08 0:56:33 c878d24 4266279 2D 1EF3 6177 864 0 115.3 MHz/100.0 MHz 154.94 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20151005_205641 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 31,840 / 158,500 ( 20 % )
Total registers 64790
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,155,348 / 21,032,960 ( 29 % )
Total RAM Blocks 848 / 2,054 ( 41 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI PMA TX Serializers 17 / 24 ( 71 % )
Total PLLs 14 / 40 ( 35 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit c878d24337b558fab34fc6e7d0753f0e5d8acf58
Author: Karol Krizka
Date: Wed Sep 23 11:42:52 2015 +0200

  Updated to Q15. Added improves support for ROS dumping.


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15

AUXCommon Git Logs


commit 6426627967cbed6d97310d4fc7ed8a370121a18c
Author: unknown
Date: Tue Sep 29 14:05:43 2015 +0200

  bug fix in L1IDsynccheck


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.

2015-10-04 20:00:08 0:56:09 c878d24 4266279 2D 1EDB 6177 864 0 114.23 MHz/100.0 MHz 154.7 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20151004_205617 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 31,712 / 158,500 ( 20 % )
Total registers 64732
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,155,348 / 21,032,960 ( 29 % )
Total RAM Blocks 848 / 2,054 ( 41 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI PMA TX Serializers 17 / 24 ( 71 % )
Total PLLs 14 / 40 ( 35 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit c878d24337b558fab34fc6e7d0753f0e5d8acf58
Author: Karol Krizka
Date: Wed Sep 23 11:42:52 2015 +0200

  Updated to Q15. Added improves support for ROS dumping.


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15

AUXCommon Git Logs


commit 6426627967cbed6d97310d4fc7ed8a370121a18c
Author: unknown
Date: Tue Sep 29 14:05:43 2015 +0200

  bug fix in L1IDsynccheck


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.

2015-10-03 20:00:08 0:54:56 c878d24 4266279 2D 1EC3 6177 864 0 115.13 MHz/100.0 MHz 153.87 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20151003_205504 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 31,655 / 158,500 ( 20 % )
Total registers 64761
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,155,348 / 21,032,960 ( 29 % )
Total RAM Blocks 848 / 2,054 ( 41 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI PMA TX Serializers 17 / 24 ( 71 % )
Total PLLs 14 / 40 ( 35 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit c878d24337b558fab34fc6e7d0753f0e5d8acf58
Author: Karol Krizka
Date: Wed Sep 23 11:42:52 2015 +0200

  Updated to Q15. Added improves support for ROS dumping.


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15

AUXCommon Git Logs


commit 6426627967cbed6d97310d4fc7ed8a370121a18c
Author: unknown
Date: Tue Sep 29 14:05:43 2015 +0200

  bug fix in L1IDsynccheck


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.

2015-10-02 20:00:08 0:55:31 c878d24 4266279 2D 1EAB 6177 864 0 120.61 MHz/100.0 MHz 159.8 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20151002_205539 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 31,706 / 158,500 ( 20 % )
Total registers 64713
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,155,348 / 21,032,960 ( 29 % )
Total RAM Blocks 848 / 2,054 ( 41 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI PMA TX Serializers 17 / 24 ( 71 % )
Total PLLs 14 / 40 ( 35 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit c878d24337b558fab34fc6e7d0753f0e5d8acf58
Author: Karol Krizka
Date: Wed Sep 23 11:42:52 2015 +0200

  Updated to Q15. Added improves support for ROS dumping.


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15

AUXCommon Git Logs


commit 6426627967cbed6d97310d4fc7ed8a370121a18c
Author: unknown
Date: Tue Sep 29 14:05:43 2015 +0200

  bug fix in L1IDsynccheck


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.

2015-10-01 20:00:08 0:56:08 c878d24 4266279 2D 1E93 6177 864 0 118.3 MHz/100.0 MHz 159.77 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20151001_205616 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 31,741 / 158,500 ( 20 % )
Total registers 64663
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,155,348 / 21,032,960 ( 29 % )
Total RAM Blocks 848 / 2,054 ( 41 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI PMA TX Serializers 17 / 24 ( 71 % )
Total PLLs 14 / 40 ( 35 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit c878d24337b558fab34fc6e7d0753f0e5d8acf58
Author: Karol Krizka
Date: Wed Sep 23 11:42:52 2015 +0200

  Updated to Q15. Added improves support for ROS dumping.


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15

AUXCommon Git Logs


commit 6426627967cbed6d97310d4fc7ed8a370121a18c
Author: unknown
Date: Tue Sep 29 14:05:43 2015 +0200

  bug fix in L1IDsynccheck


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.

2015-09-30 20:00:08 0:54:28 c878d24 4266279 2D 1E7B 6177 864 0 116.9 MHz/100.0 MHz 152.51 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150930_205436 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 31,751 / 158,500 ( 20 % )
Total registers 64634
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,155,348 / 21,032,960 ( 29 % )
Total RAM Blocks 848 / 2,054 ( 41 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI PMA TX Serializers 17 / 24 ( 71 % )
Total PLLs 14 / 40 ( 35 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit c878d24337b558fab34fc6e7d0753f0e5d8acf58
Author: Karol Krizka
Date: Wed Sep 23 11:42:52 2015 +0200

  Updated to Q15. Added improves support for ROS dumping.


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15

AUXCommon Git Logs


commit 6426627967cbed6d97310d4fc7ed8a370121a18c
Author: unknown
Date: Tue Sep 29 14:05:43 2015 +0200

  bug fix in L1IDsynccheck


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.

2015-09-29 20:00:08 0:53:51 c878d24 4266279 2D 1E63 6177 864 0 112.02 MHz/100.0 MHz 157.23 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150929_205359 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 31,808 / 158,500 ( 20 % )
Total registers 64766
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,155,348 / 21,032,960 ( 29 % )
Total RAM Blocks 848 / 2,054 ( 41 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI PMA TX Serializers 17 / 24 ( 71 % )
Total PLLs 14 / 40 ( 35 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit c878d24337b558fab34fc6e7d0753f0e5d8acf58
Author: Karol Krizka
Date: Wed Sep 23 11:42:52 2015 +0200

  Updated to Q15. Added improves support for ROS dumping.


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15

AUXCommon Git Logs


commit 6426627967cbed6d97310d4fc7ed8a370121a18c
Author: unknown
Date: Tue Sep 29 14:05:43 2015 +0200

  bug fix in L1IDsynccheck


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.

2015-09-28 20:00:08 0:54:43 c878d24 d4193c3 2D 1E4B 6180 868 0 121.21 MHz/100.0 MHz 156.84 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150928_205451 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 31,813 / 158,500 ( 20 % )
Total registers 64796
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,155,348 / 21,032,960 ( 29 % )
Total RAM Blocks 848 / 2,054 ( 41 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI PMA TX Serializers 17 / 24 ( 71 % )
Total PLLs 14 / 40 ( 35 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit c878d24337b558fab34fc6e7d0753f0e5d8acf58
Author: Karol Krizka
Date: Wed Sep 23 11:42:52 2015 +0200

  Updated to Q15. Added improves support for ROS dumping.


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15

AUXCommon Git Logs


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.

2015-09-27 20:00:08 0:54:34 c878d24 d4193c3 2D 1E33 6180 868 0 119.72 MHz/100.0 MHz 153.0 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150927_205442 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 31,751 / 158,500 ( 20 % )
Total registers 64832
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,155,348 / 21,032,960 ( 29 % )
Total RAM Blocks 848 / 2,054 ( 41 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI PMA TX Serializers 17 / 24 ( 71 % )
Total PLLs 14 / 40 ( 35 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit c878d24337b558fab34fc6e7d0753f0e5d8acf58
Author: Karol Krizka
Date: Wed Sep 23 11:42:52 2015 +0200

  Updated to Q15. Added improves support for ROS dumping.


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15

AUXCommon Git Logs


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.

2015-09-26 20:00:08 0:51:50 c878d24 d4193c3 2D 1E1B 6180 868 0 113.75 MHz/100.0 MHz 164.55 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150926_205158 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 31,770 / 158,500 ( 20 % )
Total registers 64777
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,155,348 / 21,032,960 ( 29 % )
Total RAM Blocks 848 / 2,054 ( 41 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI PMA TX Serializers 17 / 24 ( 71 % )
Total PLLs 14 / 40 ( 35 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit c878d24337b558fab34fc6e7d0753f0e5d8acf58
Author: Karol Krizka
Date: Wed Sep 23 11:42:52 2015 +0200

  Updated to Q15. Added improves support for ROS dumping.


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15

AUXCommon Git Logs


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.

2015-09-25 20:00:08 0:53:40 c878d24 d4193c3 2D 1E03 6180 868 0 108.17 MHz/100.0 MHz 154.51 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150925_205348 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 31,829 / 158,500 ( 20 % )
Total registers 64639
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,155,348 / 21,032,960 ( 29 % )
Total RAM Blocks 848 / 2,054 ( 41 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI PMA TX Serializers 17 / 24 ( 71 % )
Total PLLs 14 / 40 ( 35 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit c878d24337b558fab34fc6e7d0753f0e5d8acf58
Author: Karol Krizka
Date: Wed Sep 23 11:42:52 2015 +0200

  Updated to Q15. Added improves support for ROS dumping.


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15

AUXCommon Git Logs


commit cd4193c366b21e13d8d8603fac8a8c7b60bb1e70
Author: Karol Krizka
Date: Fri Sep 25 16:18:14 2015 +0200

  Added amb_logic_fifo with rate controls for amb input.


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.

2015-09-24 20:00:08 0:49:10 c878d24 c30e857 2D 1DEB 6180 868 0 118.25 MHz/100.0 MHz 158.68 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150924_204918 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 31,825 / 158,500 ( 20 % )
Total registers 64791
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,155,348 / 21,032,960 ( 29 % )
Total RAM Blocks 848 / 2,054 ( 41 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI PMA TX Serializers 17 / 24 ( 71 % )
Total PLLs 14 / 40 ( 35 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit c878d24337b558fab34fc6e7d0753f0e5d8acf58
Author: Karol Krizka
Date: Wed Sep 23 11:42:52 2015 +0200

  Updated to Q15. Added improves support for ROS dumping.


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-23 20:00:12 0:50:20 c878d24 c30e857 2D 1DD3 6180 868 0 119.62 MHz/100.0 MHz 159.01 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150923_205032 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 31,777 / 158,500 ( 20 % )
Total registers 64734
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,155,348 / 21,032,960 ( 29 % )
Total RAM Blocks 848 / 2,054 ( 41 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI PMA TX Serializers 17 / 24 ( 71 % )
Total PLLs 14 / 40 ( 35 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit c878d24337b558fab34fc6e7d0753f0e5d8acf58
Author: Karol Krizka
Date: Wed Sep 23 11:42:52 2015 +0200

  Updated to Q15. Added improves support for ROS dumping.


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-23 07:45:46 1:15:43 c878d24 c30e857 2D 1DC6 6252 870 0 111.06 MHz/100.0 MHz 164.93 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150923_090129 .

Resource Usage Summary

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 31,811 / 158,500 ( 20 % )
Total registers 64858
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,155,348 / 21,032,960 ( 29 % )
Total RAM Blocks 848 / 2,054 ( 41 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI PMA TX Serializers 17 / 24 ( 71 % )
Total PLLs 14 / 40 ( 35 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit c878d24337b558fab34fc6e7d0753f0e5d8acf58
Author: Karol Krizka
Date: Wed Sep 23 11:42:52 2015 +0200

  Updated to Q15. Added improves support for ROS dumping.


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-22 20:00:08 0:01:07 db6f22d c30e857 N/A 15 6 74 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150922_200115 .

Leading Errors

Error (11871): Your design contains IP components that must be regenerated. To regenerate your IP, use the Upgrade IP Components dialog box, available on the Project menu in the Quartus II software
Error (281042): You must upgrade the IP component instantiated in file ../pll_main.vhd to the latest version of the IP component.
Error (12267): Release Notes
Error (281042): You must upgrade the IP component instantiated in file ../Gx/Gx1_2Gbps.vhd to the latest version of the IP component.
Error (12267): Release Notes
Error (281042): You must upgrade the IP component instantiated in file ../Gx/Gx4_2Gbps.vhd to the latest version of the IP component.
Error (12267): Release Notes
Error (281042): You must upgrade the IP component instantiated in file ../Gx/Gx4_6Gbps.vhd to the latest version of the IP component.
Error (12267): Release Notes
Error (281042): You must upgrade the IP component instantiated in file ../Gx/Tx4_6Gbps.vhd to the latest version of the IP component.
Error (12267): Release Notes
...

Processor Git Logs


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-21 20:00:08 0:01:04 db6f22d c30e857 N/A 9 6 74 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150921_200112 .

Leading Errors

Error (11871): Your design contains IP components that must be regenerated. To regenerate your IP, use the Upgrade IP Components dialog box, available on the Project menu in the Quartus II software
Error (281042): You must upgrade the IP component instantiated in file ../pll_main.vhd to the latest version of the IP component.
Error (12267): Release Notes
Error (281042): You must upgrade the IP component instantiated in file ../Gx/Gx1_2Gbps.vhd to the latest version of the IP component.
Error (12267): Release Notes
Error (281042): You must upgrade the IP component instantiated in file ../Gx/Gx4_2Gbps.vhd to the latest version of the IP component.
Error (12267): Release Notes
Error (281042): You must upgrade the IP component instantiated in file ../Gx/Gx4_6Gbps.vhd to the latest version of the IP component.
Error (12267): Release Notes
Error (281042): You must upgrade the IP component instantiated in file ../Gx/Tx4_6Gbps.vhd to the latest version of the IP component.
Error (12267): Release Notes
...

Processor Git Logs


commit db6f22daab3c3524542cf0da35e64fa18c4141de
Author: FTK User
Date: Mon Sep 21 08:15:21 2015 -0700

  switch nightly compile ot 15


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-20 20:00:08 0:00:39 dc419cf c30e857 N/A 77 4 44 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150920_200047 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-19 20:00:08 0:00:39 dc419cf c30e857 N/A 77 4 44 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150919_200047 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-18 20:00:08 0:00:43 dc419cf c30e857 N/A 77 4 44 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150918_200051 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 8c30e857944811ae642fadf3ed94dd36d032f26d
Author: Karol Krizka
Date: Fri Sep 18 11:01:58 2015 +0200

  Added scripted compiles.


commit b8b544910526260bfdc217f17593ae0bd947069f
Author: Karol Krizka
Date: Mon Sep 14 16:23:03 2015 +0200

  Updated SLINK16 megafunctions to quartus 15.0. Converted SLINK16 LSC to use aux_dcfifo, removing unused AFIFOLSC16 megafunction.

2015-09-17 20:00:08 0:00:58 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150917_200106 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-16 20:00:08 0:00:59 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150916_200107 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-15 20:00:08 0:00:59 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150915_200107 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-14 20:00:07 0:01:03 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150914_200110 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-13 20:00:08 0:00:58 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150913_200106 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-12 20:00:08 0:01:01 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150912_200109 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-11 20:00:10 0:01:30 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150911_200140 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-10 20:00:08 0:01:14 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150910_200122 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-09 20:00:08 0:01:01 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150909_200109 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-08 20:00:08 0:01:03 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150908_200111 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-07 20:00:08 0:01:04 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150907_200112 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-06 20:00:09 0:01:01 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150906_200110 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-05 20:00:08 0:01:06 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150905_200114 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-04 20:00:08 0:01:06 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150904_200114 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-03 20:00:08 0:01:10 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150903_200118 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-02 20:00:10 0:01:02 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150902_200112 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-09-01 20:00:09 0:01:16 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150901_200125 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-08-31 20:00:09 0:01:27 dc419cf 3f2b3d7 N/A 12 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150831_200136 .

Leading Errors

Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_TARGETED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal assignment name.
...

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit 03f2b3d7b8d7c31ddb3d77969ba151f9df012ea2
Author: unknown
Date: Sun Aug 30 12:21:40 2015 +0200

  updating for q15


commit 31dc9426f425128b99e9389506a46d87c1d90ad4
Author: unknown
Date: Fri Aug 21 14:48:34 2015 +0200

  Git thinks there are changes to files that have no changes WTF

2015-08-17 20:00:08 0:49:06 dc419cf 309e0b2 2D 1A5B 6192 786 0 121.98 MHz/100.0 MHz 164.45 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150817_204914 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,269 / 158,500 ( 21 % )
Total registers 62756
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-16 20:00:08 0:47:14 dc419cf 309e0b2 2D 1A43 6192 786 0 115.74 MHz/100.0 MHz 169.98 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150816_204722 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,266 / 158,500 ( 21 % )
Total registers 62784
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-15 20:00:08 0:47:20 dc419cf 309e0b2 2D 1A2B 6192 786 0 111.71 MHz/100.0 MHz 168.95 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150815_204728 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,311 / 158,500 ( 21 % )
Total registers 62833
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-14 20:00:10 0:46:58 dc419cf 309e0b2 2D 1A13 6192 786 0 120.21 MHz/100.0 MHz 165.51 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150814_204708 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,261 / 158,500 ( 21 % )
Total registers 62812
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-13 20:00:08 0:58:06 dc419cf 309e0b2 2D 19FB 6192 786 0 117.01 MHz/100.0 MHz 161.92 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150813_205814 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,233 / 158,500 ( 21 % )
Total registers 62787
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-12 20:00:08 1:02:38 dc419cf 309e0b2 2D 19E3 6192 786 0 120.09 MHz/100.0 MHz 165.4 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150812_210246 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,261 / 158,500 ( 21 % )
Total registers 62945
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-11 20:00:08 1:06:32 dc419cf 309e0b2 2D 19CB 6192 786 0 115.7 MHz/100.0 MHz 164.69 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150811_210640 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,249 / 158,500 ( 21 % )
Total registers 62865
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-10 20:00:08 1:05:42 dc419cf 309e0b2 2D 19B3 6192 786 0 117.55 MHz/100.0 MHz 170.07 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150810_210550 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,244 / 158,500 ( 21 % )
Total registers 62804
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-09 20:00:08 1:06:50 dc419cf 309e0b2 2D 199B 6192 786 0 119.53 MHz/100.0 MHz 163.03 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150809_210658 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,274 / 158,500 ( 21 % )
Total registers 62872
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-08 20:00:07 0:58:38 dc419cf 309e0b2 2D 1983 6192 786 0 118.12 MHz/100.0 MHz 165.92 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150808_205845 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,281 / 158,500 ( 21 % )
Total registers 62769
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-07 20:00:08 1:03:06 dc419cf 309e0b2 2D 196B 6192 786 0 118.48 MHz/100.0 MHz 170.74 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150807_210314 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,288 / 158,500 ( 21 % )
Total registers 62826
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-06 20:00:07 0:48:49 dc419cf 309e0b2 2D 1953 6192 786 0 121.2 MHz/100.0 MHz 156.57 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150806_204856 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,225 / 158,500 ( 21 % )
Total registers 62807
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-05 20:00:08 1:08:11 dc419cf 309e0b2 2D 193B 6192 786 0 117.33 MHz/100.0 MHz 160.38 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150805_210819 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,280 / 158,500 ( 21 % )
Total registers 62951
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-04 20:00:08 1:06:14 dc419cf 309e0b2 2D 1923 6192 786 0 117.63 MHz/100.0 MHz 167.31 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150804_210622 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,280 / 158,500 ( 21 % )
Total registers 62901
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-03 20:00:08 0:51:04 dc419cf 309e0b2 2D 190B 6192 789 0 117.74 MHz/100.0 MHz 154.92 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150803_205112 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,272 / 158,500 ( 21 % )
Total registers 62722
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-02 20:00:08 1:04:25 dc419cf 309e0b2 2D 18F3 6192 786 0 116.56 MHz/100.0 MHz 166.64 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150802_210433 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,257 / 158,500 ( 21 % )
Total registers 62827
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-08-01 20:00:12 1:05:25 dc419cf 309e0b2 2D 18DB 6192 786 0 119.65 MHz/100.0 MHz 170.56 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150801_210537 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,293 / 158,500 ( 21 % )
Total registers 62861
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-07-31 20:00:07 1:04:39 dc419cf 309e0b2 2D 18C3 6192 786 0 118.09 MHz/100.0 MHz 157.95 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150731_210446 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,297 / 158,500 ( 21 % )
Total registers 62876
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit dc419cf90e6667074510a02115785a2d2c4d1cf9
Author: Karol Krizka
Date: Fri Jul 31 12:37:44 2015 +0200

  Added RxROS project.


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-07-30 20:00:07 1:02:00 04f4bd7 309e0b2 2D 18AB 6192 786 0 119.26 MHz/100.0 MHz 165.21 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150730_210207 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,316 / 158,500 ( 21 % )
Total registers 62831
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.


commit 2edb9cc5cd67944403a8500503b3925222b20056
Author: Karol Krizka
Date: Sun Jul 26 15:32:47 2015 +0200

  Added missing files to the AMB l1id sync work.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-07-29 20:00:14 1:03:06 04f4bd7 309e0b2 2D 1893 6192 786 0 110.51 MHz/100.0 MHz 169.75 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150729_210320 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,282 / 158,500 ( 21 % )
Total registers 62867
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.


commit 2edb9cc5cd67944403a8500503b3925222b20056
Author: Karol Krizka
Date: Sun Jul 26 15:32:47 2015 +0200

  Added missing files to the AMB l1id sync work.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-07-28 20:00:07 1:03:35 04f4bd7 309e0b2 2D 187B 6192 786 0 107.28 MHz/100.0 MHz 161.52 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150728_210342 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,255 / 158,500 ( 21 % )
Total registers 62823
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.


commit 2edb9cc5cd67944403a8500503b3925222b20056
Author: Karol Krizka
Date: Sun Jul 26 15:32:47 2015 +0200

  Added missing files to the AMB l1id sync work.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-07-27 20:00:07 1:02:58 04f4bd7 309e0b2 2D 1863 6192 789 0 116.85 MHz/100.0 MHz 167.76 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150727_210305 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 33,305 / 158,500 ( 21 % )
Total registers 62854
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,124,872 / 21,032,960 ( 29 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 04f4bd7534d48f8b69bd56aee7518c7c89be240d
Author: Karol Krizka
Date: Mon Jul 27 15:49:58 2015 +0200

  Added missing hw_stripchi2 entity.


commit 2edb9cc5cd67944403a8500503b3925222b20056
Author: Karol Krizka
Date: Sun Jul 26 15:32:47 2015 +0200

  Added missing files to the AMB l1id sync work.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-07-26 20:00:09 0:02:32 2edb9cc 309e0b2 N/A 1287 1 4 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150726_200241 .

Leading Errors

Error (10481): VHDL Use Clause error at hit_warrior_multi.vhd(290): design library "work" does not contain primary unit "hw_stripchi2" File: D:/Projects/ftk/Nightlies/Input2/RxLDC/hit_warrior/hit_warrior_multi.vhd Line: 290
Error (293001): Quartus II Full Compilation was unsuccessful. 3 errors, 1 warning
Error (213009): File name "Rx.sof" does not exist
Error (213009): File name "I2_RxLDC.pof" does not exist

Processor Git Logs


commit 2edb9cc5cd67944403a8500503b3925222b20056
Author: Karol Krizka
Date: Sun Jul 26 15:32:47 2015 +0200

  Added missing files to the AMB l1id sync work.


commit 51e646b87ceebd13d59b997504e1ab57451b1fae
Author: Karol Krizka
Date: Sun Jul 26 15:29:26 2015 +0200

  Remove compilation reports from RxLDC.

AUXCommon Git Logs


commit c309e0b22d9a4f40876dfd8aeab5f4055561ffb6
Author: Karol Krizka
Date: Sun Jul 26 15:37:46 2015 +0200

  whitespace


commit e4b557a167e04edbc8a5fb3c15432e195e2f021a
Author: Karol Krizka
Date: Sun Jul 26 15:37:33 2015 +0200

  Link goes down on error in SimpleSimplexLDC.

2015-07-25 20:00:08 1:01:36 b9658e2 ac61546 2D 1833 6239 643 0 117.1 MHz/100.0 MHz 169.32 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150725_210144 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 38,808 / 158,500 ( 24 % )
Total registers 78907
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,816,340 / 21,032,960 ( 32 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit b9658e21948fc8e2bf6f8bd465d0a93a495e94de
Author: U-ELECSHOP\ftk
Date: Fri Jul 24 09:57:13 2015 -0700

  remove finished compiles


commit a3e09f1b315414b00d18dcfd20c72907deb0630c
Author: Jamie Saxon
Date: Fri Jul 24 14:39:30 2015 +0200

  updating the version script

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-24 20:00:08 1:02:48 b9658e2 ac61546 2D 181B 6239 643 0 118.18 MHz/100.0 MHz 158.63 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150724_210256 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 38,811 / 158,500 ( 24 % )
Total registers 78838
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,816,340 / 21,032,960 ( 32 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit b9658e21948fc8e2bf6f8bd465d0a93a495e94de
Author: U-ELECSHOP\ftk
Date: Fri Jul 24 09:57:13 2015 -0700

  remove finished compiles


commit a3e09f1b315414b00d18dcfd20c72907deb0630c
Author: Jamie Saxon
Date: Fri Jul 24 14:39:30 2015 +0200

  updating the version script

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-23 20:00:09 1:10:53 5672eac ac61546 2D 01 10 6238 643 0 120.15 MHz/100.0 MHz 160.26 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150723_211102 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 38,871 / 158,500 ( 25 % )
Total registers 78870
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,816,340 / 21,032,960 ( 32 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 5672eac6821c269b2742c71581c6f0bb40053502
Author: U-ELECSHOP\ftk
Date: Thu Jul 23 05:33:02 2015 -0700

  struggle to get the copies to work


commit f7904c190fa21afdf732cc9338ad8f2e842a3375
Author: U-ELECSHOP\ftk
Date: Wed Jul 22 12:40:03 2015 -0700

  changing how we copy the compiles

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-23 05:34:37 1:15:27 5672eac ac61546 2D 01 10 6238 643 0 120.15 MHz/100.0 MHz 160.26 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150723_065004 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 38,871 / 158,500 ( 25 % )
Total registers 78870
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,816,340 / 21,032,960 ( 32 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 5672eac6821c269b2742c71581c6f0bb40053502
Author: U-ELECSHOP\ftk
Date: Thu Jul 23 05:33:02 2015 -0700

  struggle to get the copies to work


commit f7904c190fa21afdf732cc9338ad8f2e842a3375
Author: U-ELECSHOP\ftk
Date: Wed Jul 22 12:40:03 2015 -0700

  changing how we copy the compiles

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-22 12:40:30 0:01:43 f7904c1 ac61546 N/A 1261 29 1 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150722_124213 .

Leading Errors

Error (213009): File name "I2_RxLDC.pof" does not exist

Processor Git Logs


commit f7904c190fa21afdf732cc9338ad8f2e842a3375
Author: U-ELECSHOP\ftk
Date: Wed Jul 22 12:40:03 2015 -0700

  changing how we copy the compiles


commit 03632bc46e76a6f6437b20cd9230ecd3aa82dfbb
Author: U-ELECSHOP\ftk
Date: Wed Jul 22 07:33:05 2015 -0700

  compile.sh to use y:

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-15 20:00:10 1:19:55 06ecf47 ac61546 2D 01 10 6238 643 0 120.15 MHz/100.0 MHz 160.26 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150715_212005 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 38,871 / 158,500 ( 25 % )
Total registers 78870
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,816,340 / 21,032,960 ( 32 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 06ecf47ca8dda351d505589db3f143e2c4d28248
Author: U-ELECSHOP\ftk
Date: Tue Jul 14 14:51:25 2015 -0700

  fixing for ftk account


commit e0ef02e5445be7e3491114292e50be83fa516f4f
Author: U-ELECSHOP\ftk
Date: Tue Jul 14 14:32:15 2015 -0700

  fixing compile scripts for new account

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-15 01:44:01 1:20:24 06ecf47 ac61546 2D 01 10 6238 643 0 120.15 MHz/100.0 MHz 160.26 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150715_030425 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 38,871 / 158,500 ( 25 % )
Total registers 78870
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,816,340 / 21,032,960 ( 32 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 06ecf47ca8dda351d505589db3f143e2c4d28248
Author: U-ELECSHOP\ftk
Date: Tue Jul 14 14:51:25 2015 -0700

  fixing for ftk account


commit e0ef02e5445be7e3491114292e50be83fa516f4f
Author: U-ELECSHOP\ftk
Date: Tue Jul 14 14:32:15 2015 -0700

  fixing compile scripts for new account

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-14 20:00:07 1:16:39 06ecf47 ac61546 2D 01 10 6238 643 0 120.15 MHz/100.0 MHz 160.26 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150714_211646 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 38,871 / 158,500 ( 25 % )
Total registers 78870
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,816,340 / 21,032,960 ( 32 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 06ecf47ca8dda351d505589db3f143e2c4d28248
Author: U-ELECSHOP\ftk
Date: Tue Jul 14 14:51:25 2015 -0700

  fixing for ftk account


commit e0ef02e5445be7e3491114292e50be83fa516f4f
Author: U-ELECSHOP\ftk
Date: Tue Jul 14 14:32:15 2015 -0700

  fixing compile scripts for new account

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-14 15:06:20 1:18:13 06ecf47 ac61546 2D 01 10 6238 643 0 120.15 MHz/100.0 MHz 160.26 MHz/160.0 MHz -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150714_162433 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB5H4F35C4
Timing Models Final
Logic utilization (in ALMs) 38,871 / 158,500 ( 25 % )
Total registers 78870
Total pins 182 / 656 ( 28 % )
Total virtual pins 0
Total block memory bits 6,816,340 / 21,032,960 ( 32 % )
Total DSP Blocks 0 / 1,092 ( 0 % )
Total HSSI RX PCSs 9 / 24 ( 38 % )
Total HSSI PMA RX Deserializers 9 / 24 ( 38 % )
Total HSSI TX PCSs 17 / 24 ( 71 % )
Total HSSI TX Channels 17 / 24 ( 71 % )
Total PLLs 1 / 40 ( 3 % )
Total DLLs 0 / 4 ( 0 % )

Processor Git Logs


commit 06ecf47ca8dda351d505589db3f143e2c4d28248
Author: U-ELECSHOP\ftk
Date: Tue Jul 14 14:51:25 2015 -0700

  fixing for ftk account


commit e0ef02e5445be7e3491114292e50be83fa516f4f
Author: U-ELECSHOP\ftk
Date: Tue Jul 14 14:32:15 2015 -0700

  fixing compile scripts for new account

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-14 14:51:38 0:05:04 06ecf47 ac61546 N/A 3019 89 4 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_I2_RxLDC_20150714_145642 .

Leading Errors

Error (12006): Node instance "mgl_prim2" instantiates undefined entity "sld_reserved_Rx_LatencyCalc_2_8be" File: D:/Projects/ftk/Nightlies/Input2/RxLDC/db/sld_ela_trigger_3do.tdf Line: 48
Error (293001): Quartus II Full Compilation was unsuccessful. 3 errors, 89 warnings
Error (213009): File name "Rx.sof" does not exist
Error (213009): File name "I2_RxLDC.pof" does not exist

Processor Git Logs


commit 06ecf47ca8dda351d505589db3f143e2c4d28248
Author: U-ELECSHOP\ftk
Date: Tue Jul 14 14:51:25 2015 -0700

  fixing for ftk account


commit e0ef02e5445be7e3491114292e50be83fa516f4f
Author: U-ELECSHOP\ftk
Date: Tue Jul 14 14:32:15 2015 -0700

  fixing compile scripts for new account

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.



RxDebug_EMIF_master

Compile Started Compile Time Processor AUXCommon Version nInfo nWarnings nErrors fMax[0] fMax[1] Fitter Effort
2015-07-12 16:00:37 1:22:52 393e4d0 ac61546 FE 01 0E 27910 323 0 135.89 MHz/100.0 MHz 147.71 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150712_172329 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,993 / 190,240 ( 29 % )
Total registers 87490
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.210 DOEMIF:gen_singl...afi_address_r[9]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_addr_cmd_datapath:uaddr_cmd_datapath|afi_address_r[9] DOEMIF:gen_singl...io_outa[9]~DFFLODOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_new_io_pads:uio_pads|EMIFRLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|altddio_out:uaddress_pad|ddio_out_r3f:auto_generated|ddio_outa[9]~DFFLO
2 -0.206 DOEMIF:gen_singl...afi_address_r[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_addr_cmd_datapath:uaddr_cmd_datapath|afi_address_r[3] DOEMIF:gen_singl...io_outa[3]~DFFLODOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_new_io_pads:uio_pads|EMIFRLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|altddio_out:uaddress_pad|ddio_out_r3f:auto_generated|ddio_outa[3]~DFFLO
3 -0.146 DOEMIF:gen_singl...ess|datain_r[37]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_addr_cmd_datapath:uaddr_cmd_datapath|EMIFRLDRAMII_p0_fr_cycle_shifter:uaddr_cmd_shift_address|datain_r[37] DOEMIF:gen_singl..._outa[18]~DFFHI0DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_new_io_pads:uio_pads|EMIFRLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|altddio_out:uaddress_pad|ddio_out_r3f:auto_generated|ddio_outa[18]~DFFHI0
4 -0.124 DOEMIF:gen_singl...ess|datain_r[28]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_addr_cmd_datapath:uaddr_cmd_datapath|EMIFRLDRAMII_p0_fr_cycle_shifter:uaddr_cmd_shift_address|datain_r[28] DOEMIF:gen_singl...o_outa[9]~DFFHI0DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_new_io_pads:uio_pads|EMIFRLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|altddio_out:uaddress_pad|ddio_out_r3f:auto_generated|ddio_outa[9]~DFFHI0
5 -0.121 DOEMIF:gen_singl...afi_address_r[8]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_addr_cmd_datapath:uaddr_cmd_datapath|afi_address_r[8] DOEMIF:gen_singl...io_outa[8]~DFFLODOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_new_io_pads:uio_pads|EMIFRLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|altddio_out:uaddress_pad|ddio_out_r3f:auto_generated|ddio_outa[8]~DFFLO

Processor Git Logs


commit 393e4d0ad77aa7ef1b5c0035b765afb97c185582
Author: Karol Krizka
Date: Thu Jul 9 22:04:12 2015 +0200

  Hold control registers consolidation.


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-11 16:00:25 1:23:11 393e4d0 ac61546 FE 01 0E 27910 323 0 135.89 MHz/100.0 MHz 147.71 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150711_172336 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,993 / 190,240 ( 29 % )
Total registers 87490
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.210 DOEMIF:gen_singl...afi_address_r[9]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_addr_cmd_datapath:uaddr_cmd_datapath|afi_address_r[9] DOEMIF:gen_singl...io_outa[9]~DFFLODOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_new_io_pads:uio_pads|EMIFRLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|altddio_out:uaddress_pad|ddio_out_r3f:auto_generated|ddio_outa[9]~DFFLO
2 -0.206 DOEMIF:gen_singl...afi_address_r[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_addr_cmd_datapath:uaddr_cmd_datapath|afi_address_r[3] DOEMIF:gen_singl...io_outa[3]~DFFLODOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_new_io_pads:uio_pads|EMIFRLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|altddio_out:uaddress_pad|ddio_out_r3f:auto_generated|ddio_outa[3]~DFFLO
3 -0.146 DOEMIF:gen_singl...ess|datain_r[37]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_addr_cmd_datapath:uaddr_cmd_datapath|EMIFRLDRAMII_p0_fr_cycle_shifter:uaddr_cmd_shift_address|datain_r[37] DOEMIF:gen_singl..._outa[18]~DFFHI0DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_new_io_pads:uio_pads|EMIFRLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|altddio_out:uaddress_pad|ddio_out_r3f:auto_generated|ddio_outa[18]~DFFHI0
4 -0.124 DOEMIF:gen_singl...ess|datain_r[28]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_addr_cmd_datapath:uaddr_cmd_datapath|EMIFRLDRAMII_p0_fr_cycle_shifter:uaddr_cmd_shift_address|datain_r[28] DOEMIF:gen_singl...o_outa[9]~DFFHI0DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_new_io_pads:uio_pads|EMIFRLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|altddio_out:uaddress_pad|ddio_out_r3f:auto_generated|ddio_outa[9]~DFFHI0
5 -0.121 DOEMIF:gen_singl...afi_address_r[8]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_addr_cmd_datapath:uaddr_cmd_datapath|afi_address_r[8] DOEMIF:gen_singl...io_outa[8]~DFFLODOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_new_io_pads:uio_pads|EMIFRLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|altddio_out:uaddress_pad|ddio_out_r3f:auto_generated|ddio_outa[8]~DFFLO

Processor Git Logs


commit 393e4d0ad77aa7ef1b5c0035b765afb97c185582
Author: Karol Krizka
Date: Thu Jul 9 22:04:12 2015 +0200

  Hold control registers consolidation.


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-10 16:03:36 1:26:04 393e4d0 ac61546 FE 01 0E 27910 323 0 135.89 MHz/100.0 MHz 147.71 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150710_172940 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,993 / 190,240 ( 29 % )
Total registers 87490
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.210 DOEMIF:gen_singl...afi_address_r[9]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_addr_cmd_datapath:uaddr_cmd_datapath|afi_address_r[9] DOEMIF:gen_singl...io_outa[9]~DFFLODOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_new_io_pads:uio_pads|EMIFRLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|altddio_out:uaddress_pad|ddio_out_r3f:auto_generated|ddio_outa[9]~DFFLO
2 -0.206 DOEMIF:gen_singl...afi_address_r[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_addr_cmd_datapath:uaddr_cmd_datapath|afi_address_r[3] DOEMIF:gen_singl...io_outa[3]~DFFLODOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_new_io_pads:uio_pads|EMIFRLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|altddio_out:uaddress_pad|ddio_out_r3f:auto_generated|ddio_outa[3]~DFFLO
3 -0.146 DOEMIF:gen_singl...ess|datain_r[37]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_addr_cmd_datapath:uaddr_cmd_datapath|EMIFRLDRAMII_p0_fr_cycle_shifter:uaddr_cmd_shift_address|datain_r[37] DOEMIF:gen_singl..._outa[18]~DFFHI0DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_new_io_pads:uio_pads|EMIFRLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|altddio_out:uaddress_pad|ddio_out_r3f:auto_generated|ddio_outa[18]~DFFHI0
4 -0.124 DOEMIF:gen_singl...ess|datain_r[28]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_addr_cmd_datapath:uaddr_cmd_datapath|EMIFRLDRAMII_p0_fr_cycle_shifter:uaddr_cmd_shift_address|datain_r[28] DOEMIF:gen_singl...o_outa[9]~DFFHI0DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_new_io_pads:uio_pads|EMIFRLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|altddio_out:uaddress_pad|ddio_out_r3f:auto_generated|ddio_outa[9]~DFFHI0
5 -0.121 DOEMIF:gen_singl...afi_address_r[8]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_addr_cmd_datapath:uaddr_cmd_datapath|afi_address_r[8] DOEMIF:gen_singl...io_outa[8]~DFFLODOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_p0:p0|EMIFRLDRAMII_p0_memphy:umemphy|EMIFRLDRAMII_p0_new_io_pads:uio_pads|EMIFRLDRAMII_p0_addr_cmd_pads:uaddr_cmd_pads|altddio_out:uaddress_pad|ddio_out_r3f:auto_generated|ddio_outa[8]~DFFLO

Processor Git Logs


commit 393e4d0ad77aa7ef1b5c0035b765afb97c185582
Author: Karol Krizka
Date: Thu Jul 9 22:04:12 2015 +0200

  Hold control registers consolidation.


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-08 16:00:31 1:23:37 393826d ac61546 FE 01 0E 27908 317 0 142.39 MHz/100.0 MHz 147.28 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150708_172408 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,846 / 190,240 ( 29 % )
Total registers 87440
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.379 DOEMIF:gen_singl...clk|reset_reg[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[3] DOEMIF:gen_singl...if|cmd1_addr[11]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[11]
2 -0.379 DOEMIF:gen_singl...clk|reset_reg[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[3] DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
3 -0.379 DOEMIF:gen_singl...clk|reset_reg[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[3] DOEMIF:gen_singl...if|cmd1_addr[17]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[17]
4 -0.379 DOEMIF:gen_singl...clk|reset_reg[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[3] DOEMIF:gen_singl...if|cmd1_addr[19]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[19]
5 -0.379 DOEMIF:gen_singl...clk|reset_reg[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[3] DOEMIF:gen_singl...if|cmd1_addr[21]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[21]

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-07 16:03:23 1:28:23 393826d ac61546 FE 01 0E 27908 317 0 142.39 MHz/100.0 MHz 147.28 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150707_173146 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,846 / 190,240 ( 29 % )
Total registers 87440
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.379 DOEMIF:gen_singl...clk|reset_reg[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[3] DOEMIF:gen_singl...if|cmd1_addr[11]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[11]
2 -0.379 DOEMIF:gen_singl...clk|reset_reg[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[3] DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
3 -0.379 DOEMIF:gen_singl...clk|reset_reg[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[3] DOEMIF:gen_singl...if|cmd1_addr[17]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[17]
4 -0.379 DOEMIF:gen_singl...clk|reset_reg[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[3] DOEMIF:gen_singl...if|cmd1_addr[19]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[19]
5 -0.379 DOEMIF:gen_singl...clk|reset_reg[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[3] DOEMIF:gen_singl...if|cmd1_addr[21]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[21]

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-06 16:00:21 1:24:11 393826d ac61546 FE 01 0E 27908 317 0 142.39 MHz/100.0 MHz 147.28 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150706_172432 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,846 / 190,240 ( 29 % )
Total registers 87440
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.379 DOEMIF:gen_singl...clk|reset_reg[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[3] DOEMIF:gen_singl...if|cmd1_addr[11]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[11]
2 -0.379 DOEMIF:gen_singl...clk|reset_reg[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[3] DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
3 -0.379 DOEMIF:gen_singl...clk|reset_reg[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[3] DOEMIF:gen_singl...if|cmd1_addr[17]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[17]
4 -0.379 DOEMIF:gen_singl...clk|reset_reg[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[3] DOEMIF:gen_singl...if|cmd1_addr[19]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[19]
5 -0.379 DOEMIF:gen_singl...clk|reset_reg[3]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_reset_sync:ureset_afi_clk|reset_reg[3] DOEMIF:gen_singl...if|cmd1_addr[21]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[21]

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-05 16:00:23 1:20:41 393826d 5e26926 FE 01 0E 27908 317 0 139.1 MHz/100.0 MHz 150.94 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150705_172104 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,946 / 190,240 ( 29 % )
Total registers 87592
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.199 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
2 -0.192 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
3 -0.181 DOEMIF:gen_singl...|phy_cal_successDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_success DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
4 -0.139 DOEMIF:gen_singl..._one:fsm|do_readDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|alt_rld_fsm_ctl_bl_is_one:fsm|do_read DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
5 -0.138 DOEMIF:gen_singl...nst|phy_cal_failDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_fail DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-07-04 16:00:40 1:20:34 393826d 5e26926 FE 01 0E 27908 317 0 139.1 MHz/100.0 MHz 150.94 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150704_172114 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,946 / 190,240 ( 29 % )
Total registers 87592
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.199 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
2 -0.192 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
3 -0.181 DOEMIF:gen_singl...|phy_cal_successDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_success DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
4 -0.139 DOEMIF:gen_singl..._one:fsm|do_readDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|alt_rld_fsm_ctl_bl_is_one:fsm|do_read DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
5 -0.138 DOEMIF:gen_singl...nst|phy_cal_failDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_fail DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-07-03 16:00:48 1:20:51 393826d 5e26926 FE 01 0E 27908 317 0 139.1 MHz/100.0 MHz 150.94 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150703_172139 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,946 / 190,240 ( 29 % )
Total registers 87592
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.199 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
2 -0.192 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
3 -0.181 DOEMIF:gen_singl...|phy_cal_successDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_success DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
4 -0.139 DOEMIF:gen_singl..._one:fsm|do_readDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|alt_rld_fsm_ctl_bl_is_one:fsm|do_read DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
5 -0.138 DOEMIF:gen_singl...nst|phy_cal_failDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_fail DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-07-02 16:00:23 1:20:44 393826d 5e26926 FE 01 0E 27908 317 0 139.1 MHz/100.0 MHz 150.94 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150702_172107 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,946 / 190,240 ( 29 % )
Total registers 87592
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.199 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
2 -0.192 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
3 -0.181 DOEMIF:gen_singl...|phy_cal_successDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_success DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
4 -0.139 DOEMIF:gen_singl..._one:fsm|do_readDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|alt_rld_fsm_ctl_bl_is_one:fsm|do_read DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
5 -0.138 DOEMIF:gen_singl...nst|phy_cal_failDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_fail DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-07-01 16:00:27 1:20:09 393826d 5e26926 FE 01 0E 27908 317 0 139.1 MHz/100.0 MHz 150.94 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150701_172036 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,946 / 190,240 ( 29 % )
Total registers 87592
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.199 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
2 -0.192 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
3 -0.181 DOEMIF:gen_singl...|phy_cal_successDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_success DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
4 -0.139 DOEMIF:gen_singl..._one:fsm|do_readDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|alt_rld_fsm_ctl_bl_is_one:fsm|do_read DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
5 -0.138 DOEMIF:gen_singl...nst|phy_cal_failDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_fail DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-30 16:00:57 1:20:09 393826d 5e26926 FE 01 0E 27908 317 0 139.1 MHz/100.0 MHz 150.94 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150630_172106 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,946 / 190,240 ( 29 % )
Total registers 87592
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.199 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
2 -0.192 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
3 -0.181 DOEMIF:gen_singl...|phy_cal_successDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_success DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
4 -0.139 DOEMIF:gen_singl..._one:fsm|do_readDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|alt_rld_fsm_ctl_bl_is_one:fsm|do_read DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
5 -0.138 DOEMIF:gen_singl...nst|phy_cal_failDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_fail DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-29 16:00:21 1:20:13 393826d 5e26926 FE 01 0E 27908 317 0 139.1 MHz/100.0 MHz 150.94 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150629_172034 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,946 / 190,240 ( 29 % )
Total registers 87592
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.199 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
2 -0.192 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
3 -0.181 DOEMIF:gen_singl...|phy_cal_successDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_success DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
4 -0.139 DOEMIF:gen_singl..._one:fsm|do_readDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|alt_rld_fsm_ctl_bl_is_one:fsm|do_read DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
5 -0.138 DOEMIF:gen_singl...nst|phy_cal_failDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_fail DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-28 16:00:35 1:19:55 393826d 5e26926 FE 01 0E 27908 317 0 139.1 MHz/100.0 MHz 150.94 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150628_172030 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,946 / 190,240 ( 29 % )
Total registers 87592
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.199 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
2 -0.192 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
3 -0.181 DOEMIF:gen_singl...|phy_cal_successDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_success DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
4 -0.139 DOEMIF:gen_singl..._one:fsm|do_readDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|alt_rld_fsm_ctl_bl_is_one:fsm|do_read DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
5 -0.138 DOEMIF:gen_singl...nst|phy_cal_failDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_fail DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-27 16:00:36 1:20:42 393826d 5e26926 FE 01 0E 27908 317 0 139.1 MHz/100.0 MHz 150.94 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150627_172118 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,946 / 190,240 ( 29 % )
Total registers 87592
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.199 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
2 -0.192 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
3 -0.181 DOEMIF:gen_singl...|phy_cal_successDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_success DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
4 -0.139 DOEMIF:gen_singl..._one:fsm|do_readDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|alt_rld_fsm_ctl_bl_is_one:fsm|do_read DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
5 -0.138 DOEMIF:gen_singl...nst|phy_cal_failDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_fail DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-26 16:00:23 1:19:28 393826d 5e26926 FE 01 0E 27908 317 0 139.1 MHz/100.0 MHz 150.94 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150626_171951 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,946 / 190,240 ( 29 % )
Total registers 87592
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.199 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
2 -0.192 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
3 -0.181 DOEMIF:gen_singl...|phy_cal_successDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_success DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
4 -0.139 DOEMIF:gen_singl..._one:fsm|do_readDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|alt_rld_fsm_ctl_bl_is_one:fsm|do_read DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
5 -0.138 DOEMIF:gen_singl...nst|phy_cal_failDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_fail DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-25 16:00:21 1:21:17 393826d 5e26926 FE 01 0E 27908 317 0 139.1 MHz/100.0 MHz 150.94 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150625_172138 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,946 / 190,240 ( 29 % )
Total registers 87592
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.199 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
2 -0.192 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
3 -0.181 DOEMIF:gen_singl...|phy_cal_successDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_success DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
4 -0.139 DOEMIF:gen_singl..._one:fsm|do_readDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|alt_rld_fsm_ctl_bl_is_one:fsm|do_read DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
5 -0.138 DOEMIF:gen_singl...nst|phy_cal_failDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_fail DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-24 16:00:25 1:20:17 a2c66eb 5e26926 FE 01 0E 27908 317 0 139.1 MHz/100.0 MHz 150.94 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150624_172042 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,946 / 190,240 ( 29 % )
Total registers 87592
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.199 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
2 -0.192 DOEMIF:gen_singl...f|cmd0_write_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_write_req DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
3 -0.181 DOEMIF:gen_singl...|phy_cal_successDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_success DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL
4 -0.139 DOEMIF:gen_singl..._one:fsm|do_readDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|alt_rld_fsm_ctl_bl_is_one:fsm|do_read DOEMIF:gen_singl...if|cmd1_addr[15]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[15]
5 -0.138 DOEMIF:gen_singl...nst|phy_cal_failDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|sequencer_phy_mgr:sequencer_phy_mgr_inst|phy_cal_fail DOEMIF:gen_singl..._B_ADDRESS_STALLDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|ExtMemClockInterface:ExternalMemInterface|dcfifo:dcfifo_input_amc_inst|dcfifo_lgm1:auto_generated|altsyncram_bf71:fifo_ram|ram_block5a120~PORT_B_ADDRESS_STALL

Processor Git Logs


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout


commit a374e80c2a4f22206946de3087c873c5f52f4215
Author: Jordan Webster
Date: Wed Jun 24 10:49:45 2015 -0700

  trying to fix compile fails from disconnected line in DOSpyBuffers

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-23 16:00:27 1:20:48 b0ea31e 5e26926 FE 01 0E 27906 318 0 134.35 MHz/100.0 MHz 149.57 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150623_172115 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,925 / 190,240 ( 29 % )
Total registers 87451
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit b0ea31e40c33a115b76a45fe9793180ed1cffda7
Merge: 2126c76 424e6cc
Author: John Alison
Date: Sun Jun 21 07:36:10 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030


commit 424e6cc647c622cad3a3cc80bea550fbc95cb159
Author: John Alison
Date: Sun Jun 21 13:36:16 2015 +0200

  Duplicating more TF registers

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-22 16:00:21 1:21:00 b0ea31e 5e26926 FE 01 0E 27906 318 0 134.35 MHz/100.0 MHz 149.57 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150622_172121 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,925 / 190,240 ( 29 % )
Total registers 87451
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit b0ea31e40c33a115b76a45fe9793180ed1cffda7
Merge: 2126c76 424e6cc
Author: John Alison
Date: Sun Jun 21 07:36:10 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030


commit 424e6cc647c622cad3a3cc80bea550fbc95cb159
Author: John Alison
Date: Sun Jun 21 13:36:16 2015 +0200

  Duplicating more TF registers

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-21 16:00:36 1:20:08 b0ea31e 5e26926 FE 01 0E 27906 318 0 134.35 MHz/100.0 MHz 149.57 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150621_172044 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,925 / 190,240 ( 29 % )
Total registers 87451
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit b0ea31e40c33a115b76a45fe9793180ed1cffda7
Merge: 2126c76 424e6cc
Author: John Alison
Date: Sun Jun 21 07:36:10 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030


commit 424e6cc647c622cad3a3cc80bea550fbc95cb159
Author: John Alison
Date: Sun Jun 21 13:36:16 2015 +0200

  Duplicating more TF registers

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-20 16:00:24 1:19:19 5975ae1 5e26926 FE 01 0E 27906 318 0 134.35 MHz/100.0 MHz 149.57 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150620_171943 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,925 / 190,240 ( 29 % )
Total registers 87451
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 5975ae14e045d34856d22389db903b59bd074f49
Author: John Alison
Date: Sat Jun 20 22:19:59 2015 +0200

  More Duplications


commit 74f9648de8673baa0048564d2c4ec9cb692e53e4
Author: jwebste2
Date: Fri Jun 19 16:05:55 2015 -0500

  updated nightly compile script

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-19 16:00:43 1:19:34 d77dd03 5e26926 FE 01 0E 27906 318 0 134.35 MHz/100.0 MHz 149.57 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150619_172017 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,925 / 190,240 ( 29 % )
Total registers 87451
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit d77dd035e78d6ac25c3284a702c96cc9af48c4b3
Author: jwebste2
Date: Fri Jun 19 11:33:48 2015 -0500

  updated nightly scripts


commit da78928e3fda69bf54b073a456a9c6e772b73042
Author: jwebste2
Date: Fri Jun 19 10:58:59 2015 -0500

  new nightly script

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-18 16:00:31 1:19:20 771ba18 5e26926 FE 01 0E 27906 318 0 134.35 MHz/100.0 MHz 149.57 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150618_171951 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,925 / 190,240 ( 29 % )
Total registers 87451
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 771ba18f6632802ff5785640080c93d1940f0952
Author: jwebster
Date: Thu Jun 18 12:23:08 2015 -0500

  nightly compile scripts


commit ae7993cf22664900fc7bdd42478db9eae038b315
Author: jwebster
Date: Thu Jun 18 12:19:20 2015 -0500

  typo in nightly script

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-17 16:00:11 1:18:38 251ae51 5e26926 FE 01 0E 27906 318 0 134.35 MHz/100.0 MHz 149.57 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150617_171849 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,925 / 190,240 ( 29 % )
Total registers 87451
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 251ae51b9e8c16cca3383d84ca59aa952127bbff
Merge: 137fa0b c6a09d2
Author: Jordan Webster
Date: Tue Jun 16 16:34:31 2015 -0700

  Merge branch 'Jordan'


commit c6a09d24a35da4fbb37382514d5ba57cf7b94777
Author: Jordan Webster
Date: Tue Jun 16 16:17:45 2015 -0700

  updated waves for TF road record types

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-16 16:01:01 1:24:17 b46aad1 5e26926 FE 01 0E 27906 318 0 136.78 MHz/100.0 MHz 152.53 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150616_172518 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,945 / 190,240 ( 29 % )
Total registers 87454
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,772,452 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit b46aad18d007b14c924aa2e781755471092c48a5
Merge: 81e9937 09d66c1
Author: unknown
Date: Tue Jun 16 15:20:32 2015 -0700

  Merge remote-tracking branch 'origin/master'

  Conflicts:
  combined_testbench/run_MergedDOLoop.do


commit 81e9937305472905c90ddce4df66b9877fcb4272
Author: unknown
Date: Tue Jun 16 15:19:36 2015 -0700

  adding DCIndexROM.vhd to rx emif qsf

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-15 16:00:45 1:23:33 b14f0e8 8a74633 FE 01 0C 27849 313 0 133.64 MHz/100.0 MHz 151.03 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150615_172418 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 55,493 / 190,240 ( 29 % )
Total registers 88019
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,636 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[10]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[10]
2 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[12]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[12]
3 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[13]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[13]
4 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[14]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[14]
5 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[16]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[16]

Processor Git Logs


commit b14f0e8d7ffe11a233bc97fea5a5954a39d99ee5
Author: John Alison
Date: Sun Jun 14 15:11:22 2015 +0200

  Updates to the latency to match the chi2


commit 0313f9ef396c612f0e88d34aa4ca66b4439812a7
Author: John Alison
Date: Sun Jun 14 14:40:46 2015 +0200

  Add fanout

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-14 16:00:41 1:23:35 b14f0e8 8a74633 FE 01 0C 27849 313 0 133.64 MHz/100.0 MHz 151.03 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150614_172416 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 55,493 / 190,240 ( 29 % )
Total registers 88019
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,636 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[10]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[10]
2 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[12]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[12]
3 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[13]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[13]
4 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[14]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[14]
5 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[16]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[16]

Processor Git Logs


commit b14f0e8d7ffe11a233bc97fea5a5954a39d99ee5
Author: John Alison
Date: Sun Jun 14 15:11:22 2015 +0200

  Updates to the latency to match the chi2


commit 0313f9ef396c612f0e88d34aa4ca66b4439812a7
Author: John Alison
Date: Sun Jun 14 14:40:46 2015 +0200

  Add fanout

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-13 16:00:23 1:23:31 c5178a2 8a74633 FE 01 0C 27849 313 0 133.64 MHz/100.0 MHz 151.03 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150613_172354 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 55,493 / 190,240 ( 29 % )
Total registers 88019
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,636 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[10]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[10]
2 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[12]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[12]
3 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[13]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[13]
4 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[14]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[14]
5 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[16]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[16]

Processor Git Logs


commit c5178a29264f669246ec94237617d390f4fb7534
Author: John Alison
Date: Sat Jun 13 04:25:56 2015 -0400

  Bring in changes from pushing timing


commit f5a890edb8cb9e307dfe5d05ecbc6ce981296420
Author: John Alison
Date: Sat Jun 13 04:18:13 2015 -0400

  Valdated Sim

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-12 16:00:12 1:23:44 3451fb6 8a74633 FE 01 0C 27849 313 0 133.64 MHz/100.0 MHz 151.03 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150612_172356 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 55,493 / 190,240 ( 29 % )
Total registers 88019
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,636 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[10]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[10]
2 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[12]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[12]
3 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[13]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[13]
4 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[14]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[14]
5 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[16]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[16]

Processor Git Logs


commit 3451fb662aa8738c2d9d1117509eaf7cc017d3a0
Merge: bbb0304 210641e
Author: John Alison
Date: Fri Jun 12 08:04:58 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030


commit 210641e0744c83d23ae9b78dca223dfe75bc6cc3
Author: Karol Krizka
Date: Fri Jun 12 14:03:16 2015 +0200

  Adjusted TFNomFitter delays to componstate for registering everything.

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-11 16:02:21 1:30:01 94e6851 8a74633 FE 01 0C 27849 313 0 133.64 MHz/100.0 MHz 151.03 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150611_173222 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 55,493 / 190,240 ( 29 % )
Total registers 88019
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,636 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[10]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[10]
2 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[12]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[12]
3 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[13]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[13]
4 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[14]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[14]
5 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[16]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[16]

Processor Git Logs


commit 94e68519ec9e7986d2bf0a608cff6f74f9afa2db
Merge: 93f3ae2 414f714
Author: jwebster
Date: Thu Jun 11 11:49:52 2015 -0500

  Merge branch 'master' of Y:\FTK\Processor_1_20141030


commit 414f714ab9f30dc915a4320b681432b779f4b101
Author: Karol Krizka
Date: Thu Jun 11 11:14:02 2015 +0200

  Delay output layermaps in TFNomFitter to make them synchronous with chi2 output.

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-10 16:03:05 1:25:47 52f1a1c 8a74633 FE 01 0C 27846 313 0 133.64 MHz/100.0 MHz 151.03 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150610_172852 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 55,493 / 190,240 ( 29 % )
Total registers 88019
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,636 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[10]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[10]
2 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[12]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[12]
3 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[13]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[13]
4 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[14]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[14]
5 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[16]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[16]

Processor Git Logs


commit 52f1a1c793f4f258dd78d7cc3264fa90c97805f4
Author: Karol Krizka
Date: Wed Jun 10 11:20:47 2015 +0200

  Updates to TF loading in run_MergedDOLoop.


commit 5f6a79c03471b4d0b9935dd999d66c8536141369
Author: Karol Krizka
Date: Wed Jun 10 11:18:20 2015 +0200

  Updates to TF waves files in combined_testbench.

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-09 16:00:33 1:24:19 983c302 8a74633 FE 01 0C 27846 313 0 133.64 MHz/100.0 MHz 151.03 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150609_172452 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 55,493 / 190,240 ( 29 % )
Total registers 88019
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,636 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[10]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[10]
2 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[12]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[12]
3 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[13]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[13]
4 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[14]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[14]
5 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[16]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[16]

Processor Git Logs


commit 983c302a638342a01a7c8891b1920ce4fcea1149
Author: Karol Krizka
Date: Tue Jun 9 11:43:25 2015 +0200

  Fixed typo in TFRoadSynchronizer to get it to compile.


commit c80b123e480c7e57594429e23530bee0addae55e
Author: Karol Krizka
Date: Tue Jun 9 11:33:08 2015 +0200

  Fixed roads with ID 0 comming out of buffer logic.

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-08 16:00:31 1:24:52 955880d 8a74633 FE 01 0C 27846 313 0 133.64 MHz/100.0 MHz 151.03 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150608_172523 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 55,493 / 190,240 ( 29 % )
Total registers 88019
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,636 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[10]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[10]
2 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[12]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[12]
3 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[13]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[13]
4 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[14]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[14]
5 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[16]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[16]

Processor Git Logs


commit 955880d2146344ecd2554d90e65b39d4ebd13d65
Author: jwebster
Date: Thu Jun 4 11:50:42 2015 -0500

  updated nightly run script for generating html


commit ad804a530f4fd3f89e897e2622b6978fe11277bd
Author: jwebster
Date: Thu Jun 4 11:48:27 2015 -0500

  updated compile script to checkout before pulling

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-07 16:00:38 1:24:21 955880d 8a74633 FE 01 0C 27846 313 0 133.64 MHz/100.0 MHz 151.03 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150607_172459 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 55,493 / 190,240 ( 29 % )
Total registers 88019
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,636 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[10]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[10]
2 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[12]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[12]
3 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[13]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[13]
4 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[14]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[14]
5 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[16]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[16]

Processor Git Logs


commit 955880d2146344ecd2554d90e65b39d4ebd13d65
Author: jwebster
Date: Thu Jun 4 11:50:42 2015 -0500

  updated nightly run script for generating html


commit ad804a530f4fd3f89e897e2622b6978fe11277bd
Author: jwebster
Date: Thu Jun 4 11:48:27 2015 -0500

  updated compile script to checkout before pulling

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-06 16:00:33 1:24:48 955880d 8a74633 FE 01 0C 27846 313 0 133.64 MHz/100.0 MHz 151.03 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150606_172521 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 55,493 / 190,240 ( 29 % )
Total registers 88019
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,636 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[10]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[10]
2 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[12]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[12]
3 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[13]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[13]
4 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[14]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[14]
5 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[16]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[16]

Processor Git Logs


commit 955880d2146344ecd2554d90e65b39d4ebd13d65
Author: jwebster
Date: Thu Jun 4 11:50:42 2015 -0500

  updated nightly run script for generating html


commit ad804a530f4fd3f89e897e2622b6978fe11277bd
Author: jwebster
Date: Thu Jun 4 11:48:27 2015 -0500

  updated compile script to checkout before pulling

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-05 16:00:37 1:24:49 955880d 8a74633 FE 01 0C 27846 313 0 133.64 MHz/100.0 MHz 151.03 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150605_172526 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 55,493 / 190,240 ( 29 % )
Total registers 88019
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,636 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[10]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[10]
2 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[12]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[12]
3 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[13]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[13]
4 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[14]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[14]
5 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[16]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[16]

Processor Git Logs


commit 955880d2146344ecd2554d90e65b39d4ebd13d65
Author: jwebster
Date: Thu Jun 4 11:50:42 2015 -0500

  updated nightly run script for generating html


commit ad804a530f4fd3f89e897e2622b6978fe11277bd
Author: jwebster
Date: Thu Jun 4 11:48:27 2015 -0500

  updated compile script to checkout before pulling

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-04 16:00:09 1:28:11 955880d 8a74633 FE 01 0C 27846 313 0 133.64 MHz/100.0 MHz 151.03 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150604_172820 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 55,493 / 190,240 ( 29 % )
Total registers 88019
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,636 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[10]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[10]
2 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[12]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[12]
3 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[13]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[13]
4 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[14]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[14]
5 -0.233 DOEMIF:gen_singl...if|cmd0_read_reqDOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd0_read_req DOEMIF:gen_singl...if|cmd1_addr[16]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|alt_rld_controller_top_ctl_bl_is_one_urfsh:c0|alt_rld_controller_ctl_bl_is_one_urfsh:controller_inst|memctl_data_if_ctl_bl_is_one_rldramii:data_if|cmd1_addr[16]

Processor Git Logs


commit 955880d2146344ecd2554d90e65b39d4ebd13d65
Author: jwebster
Date: Thu Jun 4 11:50:42 2015 -0500

  updated nightly run script for generating html


commit ad804a530f4fd3f89e897e2622b6978fe11277bd
Author: jwebster
Date: Thu Jun 4 11:48:27 2015 -0500

  updated compile script to checkout before pulling

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-03 16:00:20 1:11:47 e899ea5 8a74633 FE 01 0C 27192 209 0 131.25 MHz/100.0 MHz 155.45 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150603_171207 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,216 / 190,240 ( 28 % )
Total registers 82066
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit e899ea59c83f690d4c1cd7d70c303a824840b432
Author: John Alison
Date: Tue May 26 17:48:00 2015 -0400

  Quick bug fixes


commit e45eb723ec14f5268fa6512c97bd77199a1b5270
Merge: 13648d4 f0bca2d
Author: John Alison
Date: Tue May 26 17:41:19 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-02 16:00:52 1:11:43 e899ea5 8a74633 FE 01 0C 27192 209 0 131.25 MHz/100.0 MHz 155.45 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150602_171235 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,216 / 190,240 ( 28 % )
Total registers 82066
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit e899ea59c83f690d4c1cd7d70c303a824840b432
Author: John Alison
Date: Tue May 26 17:48:00 2015 -0400

  Quick bug fixes


commit e45eb723ec14f5268fa6512c97bd77199a1b5270
Merge: 13648d4 f0bca2d
Author: John Alison
Date: Tue May 26 17:41:19 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-01 16:00:09 1:11:42 e899ea5 8a74633 FE 01 0C 27192 209 0 131.25 MHz/100.0 MHz 155.45 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150601_171151 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,216 / 190,240 ( 28 % )
Total registers 82066
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit e899ea59c83f690d4c1cd7d70c303a824840b432
Author: John Alison
Date: Tue May 26 17:48:00 2015 -0400

  Quick bug fixes


commit e45eb723ec14f5268fa6512c97bd77199a1b5270
Merge: 13648d4 f0bca2d
Author: John Alison
Date: Tue May 26 17:41:19 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-05-31 16:00:21 1:11:46 e899ea5 8a74633 FE 01 0C 27192 209 0 131.25 MHz/100.0 MHz 155.45 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150531_171207 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,216 / 190,240 ( 28 % )
Total registers 82066
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit e899ea59c83f690d4c1cd7d70c303a824840b432
Author: John Alison
Date: Tue May 26 17:48:00 2015 -0400

  Quick bug fixes


commit e45eb723ec14f5268fa6512c97bd77199a1b5270
Merge: 13648d4 f0bca2d
Author: John Alison
Date: Tue May 26 17:41:19 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-05-30 16:00:20 1:12:10 e899ea5 8a74633 FE 01 0C 27192 209 0 131.25 MHz/100.0 MHz 155.45 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150530_171230 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,216 / 190,240 ( 28 % )
Total registers 82066
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit e899ea59c83f690d4c1cd7d70c303a824840b432
Author: John Alison
Date: Tue May 26 17:48:00 2015 -0400

  Quick bug fixes


commit e45eb723ec14f5268fa6512c97bd77199a1b5270
Merge: 13648d4 f0bca2d
Author: John Alison
Date: Tue May 26 17:41:19 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-05-28 16:00:41 1:12:09 e899ea5 8a74633 FE 01 0C 27192 209 0 131.25 MHz/100.0 MHz 155.45 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150528_171250 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,216 / 190,240 ( 28 % )
Total registers 82066
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit e899ea59c83f690d4c1cd7d70c303a824840b432
Author: John Alison
Date: Tue May 26 17:48:00 2015 -0400

  Quick bug fixes


commit e45eb723ec14f5268fa6512c97bd77199a1b5270
Merge: 13648d4 f0bca2d
Author: John Alison
Date: Tue May 26 17:41:19 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-05-27 16:00:09 1:12:39 e899ea5 8a74633 FE 01 0C 27192 209 0 131.25 MHz/100.0 MHz 155.45 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150527_171248 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,216 / 190,240 ( 28 % )
Total registers 82066
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit e899ea59c83f690d4c1cd7d70c303a824840b432
Author: John Alison
Date: Tue May 26 17:48:00 2015 -0400

  Quick bug fixes


commit e45eb723ec14f5268fa6512c97bd77199a1b5270
Merge: 13648d4 f0bca2d
Author: John Alison
Date: Tue May 26 17:41:19 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-05-26 16:00:48 1:12:25 f0bca2d 8a74633 FE 01 0C 27192 209 0 131.25 MHz/100.0 MHz 155.45 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150526_171313 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,216 / 190,240 ( 28 % )
Total registers 82066
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit f0bca2ddc048fa28dc073b02af1252fb60bc3b25
Author: unknown
Date: Tue May 26 15:38:23 2015 -0700

  fixed debug projects to pull header and trailer from DF scynch so it doesnt exert back pressure


commit f7fb5f7588540d28912ba2c3150f18f0bab8bd85
Author: John Alison
Date: Tue May 26 10:52:16 2015 -0400

  pipe_lining read_ready to TF

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-05-25 16:00:09 1:10:48 2cc96cd caea3fb FE 01 0A 27192 196 0 140.94 MHz/100.0 MHz 152.28 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150525_171057 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 53,848 / 190,240 ( 28 % )
Total registers 80449
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 2cc96cde8a5f922073369b789173663351425956
Merge: 098d4ed 1dd5d2c
Author: unknown
Date: Mon May 25 13:17:30 2015 -0700

  Merge remote-tracking branch 'origin/master'


commit 098d4edd67819277b12e3f2a37cb29b1e00ffc96
Author: unknown
Date: Mon May 25 13:17:08 2015 -0700

  adding monitoring of emif calibration success flag. DO_Status[22]

AUXCommon Git Logs


commit dcaea3fbed25b7af853bdc0af598b8623aa2b100
Author: John Alison
Date: Mon May 18 10:54:00 2015 -0400

  Adding duplicated registers


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.

2015-05-24 16:00:26 1:10:05 df20913 caea3fb FE 01 07 27186 190 0 139.84 MHz/100.0 MHz 148.7 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150524_171031 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 53,855 / 190,240 ( 28 % )
Total registers 80388
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit df209137fc23835ad7980541ad18539681003c2f
Author: John Alison
Date: Sat May 23 15:32:14 2015 -0400

  Bug fixing'


commit b837d788aaec7dd2e830ef853da8799dd8bad9d8
Author: John Alison
Date: Sat May 23 14:28:23 2015 -0400

  Updating types for reg duplication

AUXCommon Git Logs


commit dcaea3fbed25b7af853bdc0af598b8623aa2b100
Author: John Alison
Date: Mon May 18 10:54:00 2015 -0400

  Adding duplicated registers


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.

2015-05-23 16:00:19 1:10:27 df20913 caea3fb FE 01 07 27186 190 0 139.84 MHz/100.0 MHz 148.7 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150523_171046 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 53,855 / 190,240 ( 28 % )
Total registers 80388
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit df209137fc23835ad7980541ad18539681003c2f
Author: John Alison
Date: Sat May 23 15:32:14 2015 -0400

  Bug fixing'


commit b837d788aaec7dd2e830ef853da8799dd8bad9d8
Author: John Alison
Date: Sat May 23 14:28:23 2015 -0400

  Updating types for reg duplication

AUXCommon Git Logs


commit dcaea3fbed25b7af853bdc0af598b8623aa2b100
Author: John Alison
Date: Mon May 18 10:54:00 2015 -0400

  Adding duplicated registers


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.

2015-05-22 16:00:03 1:11:27 eef1e2e caea3fb FE 01 07 27186 190 0 134.12 MHz/100.0 MHz 145.12 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150522_171130 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 53,876 / 190,240 ( 28 % )
Total registers 80338
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit eef1e2e278e696145fe58e20947561d926805088
Author: John Alison
Date: Fri May 22 15:32:10 2015 -0400

  Adding pipelinning to TFRoadSynchron


commit 98445b4ec88ff8e83de28eacc8b8a9705c0fc399
Author: John Alison
Date: Fri May 22 15:29:58 2015 -0400

  Adding pipelining before the TFInputFIFO

AUXCommon Git Logs


commit dcaea3fbed25b7af853bdc0af598b8623aa2b100
Author: John Alison
Date: Mon May 18 10:54:00 2015 -0400

  Adding duplicated registers


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.

2015-05-21 16:00:03 0:01:03 b5e1460 caea3fb N/A 1734 0 4 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150521_160106 .

Leading Errors

Error (10482): VHDL error at TFNomCombiner.vhdl(458): object "sr_consts" is used but not declared File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/TF/project/TFNomCombiner.vhdl Line: 458
Error (293001): Quartus II Full Compilation was unsuccessful. 3 errors, 24 warnings
Error (213009): File name "Rx.sof" does not exist
Error (213009): File name "RxDebug_EMIF.pof" does not exist

Processor Git Logs


commit b5e14609780d9ff662addc8355d98a50dc5aec91
Author: John Alison
Date: Thu May 21 16:33:54 2015 -0400

  Adding more duplicate registers


commit 4356afec629904b4a81d953600c1abf054aa1444
Author: John Alison
Date: Thu May 21 12:03:55 2015 -0400

  Duplicating the const req

AUXCommon Git Logs


commit dcaea3fbed25b7af853bdc0af598b8623aa2b100
Author: John Alison
Date: Mon May 18 10:54:00 2015 -0400

  Adding duplicated registers


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.

2015-05-20 16:00:02 0:01:04 151d62e caea3fb N/A 1734 0 14 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150520_160106 .

Leading Errors

Error (10482): VHDL error at Rx.vhd(1122): object "do_send_input_event" is used but not declared File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1122
Error (10482): VHDL error at Rx.vhd(1128): object "do_send_input_event" is used but not declared File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1128
Error (10482): VHDL error at Rx.vhd(1134): object "do_send_input_event" is used but not declared File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1134
Error (10482): VHDL error at Rx.vhd(1140): object "do_send_input_event" is used but not declared File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1140
Error (10482): VHDL error at Rx.vhd(1146): object "do_send_input_event" is used but not declared File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1146
Error (10482): VHDL error at Rx.vhd(1152): object "do_send_input_event" is used but not declared File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1152
Error (10482): VHDL error at Rx.vhd(1158): object "do_send_input_event" is used but not declared File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1158
Error (10482): VHDL error at Rx.vhd(1163): object "do_send_input_event" is used but not declared File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1163
Error (10482): VHDL error at Rx.vhd(1168): object "do_send_input_event" is used but not declared File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1168
Error (10482): VHDL error at Rx.vhd(1173): object "do_send_input_event" is used but not declared File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1173
Error (10482): VHDL error at Rx.vhd(1178): object "do_send_input_event" is used but not declared File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1178
...

Processor Git Logs


commit 151d62e815d48241e8e54ad9cd62973678c9defc
Merge: 55fd268 89a43d0
Author: jwebster
Date: Wed May 20 14:27:29 2015 -0500

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030


commit 89a43d0ad108663b1ef72847857a26bd714c277e
Merge: 0896203 0f8b1c6
Author: John Alison
Date: Wed May 20 12:41:56 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit dcaea3fbed25b7af853bdc0af598b8623aa2b100
Author: John Alison
Date: Mon May 18 10:54:00 2015 -0400

  Adding duplicated registers


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.

2015-05-19 16:00:34 0:01:12 1e2affd caea3fb N/A 1734 0 16 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150519_160146 .

Leading Errors

Error (10349): VHDL Association List error at Rx.vhd(1334): formal "pix_stream_req" does not exist File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1334
Error (10346): VHDL error at Rx.vhd(1301): formal port or parameter "soft_reset_n" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1301
Error (10784): HDL error at DOEMIF.vhd(86): see declaration for object "soft_reset_n" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 86
Error (10346): VHDL error at Rx.vhd(1301): formal port or parameter "global_reset_n" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1301
Error (10784): HDL error at DOEMIF.vhd(87): see declaration for object "global_reset_n" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 87
Error (10346): VHDL error at Rx.vhd(1301): formal port or parameter "oct_rzqin" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1301
Error (10784): HDL error at DOEMIF.vhd(88): see declaration for object "oct_rzqin" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 88
Error (10346): VHDL error at Rx.vhd(1301): formal port or parameter "extmem_pll_refclk" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1301
Error (10784): HDL error at DOEMIF.vhd(89): see declaration for object "extmem_pll_refclk" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 89
Error (10346): VHDL error at Rx.vhd(1301): formal port or parameter "mem_qk" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1301
Error (10784): HDL error at DOEMIF.vhd(114): see declaration for object "mem_qk" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 114
...

Processor Git Logs


commit 1e2affdf03163ff5e4f1809728b67b13764cc432
Merge: 5cc631f f323f6e
Author: jwebster
Date: Tue May 19 16:00:44 2015 -0500

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030


commit f323f6e3ed788536e9d97fd85e24d888972de7b8
Merge: 5785233 2a14d00
Author: John Alison
Date: Tue May 19 15:33:56 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit dcaea3fbed25b7af853bdc0af598b8623aa2b100
Author: John Alison
Date: Mon May 18 10:54:00 2015 -0400

  Adding duplicated registers


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.

2015-05-18 16:00:58 1:11:03 b9448c9 caea3fb FE 01 07 27188 190 0 136.44 MHz/100.0 MHz 146.33 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150518_171201 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 53,877 / 190,240 ( 28 % )
Total registers 79497
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit b9448c98fea67d886aa335c384ecfaf02d00634b
Merge: 50a748d 90bedca
Author: jwebster
Date: Mon May 18 16:01:01 2015 -0500

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030


commit 90bedcacae2e982eedae73f1b99934f9b6985ccf
Merge: 971d123 77a1150
Author: John Alison
Date: Mon May 18 15:56:29 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit dcaea3fbed25b7af853bdc0af598b8623aa2b100
Author: John Alison
Date: Mon May 18 10:54:00 2015 -0400

  Adding duplicated registers


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.

2015-05-17 16:00:30 1:14:13 3311423 f4adf4e FE 01 07 27171 180 0 145.24 MHz/100.0 MHz 151.91 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150517_171443 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,342 / 190,240 ( 31 % )
Total registers 93611
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.077 DOEMIF:gen_singl...ed|rdaddr_reg[1]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_inst_ROM_no_ifdef_params:inst_ROM_i|altsyncram:altsyncram_component|altsyncram_qls1:auto_generated|rdaddr_reg[1] DOEMIF:gen_singl...t|PC[4]_OTERM299DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|PC[4]_OTERM299
2 -0.034 DOEMIF:gen_singl...ed|rdaddr_reg[2]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_inst_ROM_no_ifdef_params:inst_ROM_i|altsyncram:altsyncram_component|altsyncram_qls1:auto_generated|rdaddr_reg[2] DOEMIF:gen_singl...t|PC[4]_OTERM299DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|PC[4]_OTERM299

Processor Git Logs


commit 331142308b5f30d4b1805d5c9175e721e54c9ba8
Author: John Alison
Date: Sat May 16 09:55:18 2015 -0400

  Compiled Rx_EMIF Black as coal at 120


commit e7c8727193004f06e3dcc5216de1a46fc9ca9444
Merge: bca9923 76d1fe7
Author: John Alison
Date: Fri May 15 15:13:56 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.

2015-05-16 16:00:10 1:18:06 3311423 f4adf4e FE 01 07 27188 180 0 145.24 MHz/100.0 MHz 151.91 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150516_171816 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,342 / 190,240 ( 31 % )
Total registers 93611
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -0.077 DOEMIF:gen_singl...ed|rdaddr_reg[1]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_inst_ROM_no_ifdef_params:inst_ROM_i|altsyncram:altsyncram_component|altsyncram_qls1:auto_generated|rdaddr_reg[1] DOEMIF:gen_singl...t|PC[4]_OTERM299DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|PC[4]_OTERM299
2 -0.034 DOEMIF:gen_singl...ed|rdaddr_reg[2]DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_inst_ROM_no_ifdef_params:inst_ROM_i|altsyncram:altsyncram_component|altsyncram_qls1:auto_generated|rdaddr_reg[2] DOEMIF:gen_singl...t|PC[4]_OTERM299DOEMIF:gen_singledo:inst39|RoadProcessorEMIF:RoadProcessor_inst|EMIFRLDRAMII:EMIF_RLDRAMII_inst|EMIFRLDRAMII_0002:emifrldramii_inst|EMIFRLDRAMII_s0:s0|rw_manager_rldram:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|PC[4]_OTERM299

Processor Git Logs


commit 331142308b5f30d4b1805d5c9175e721e54c9ba8
Author: John Alison
Date: Sat May 16 09:55:18 2015 -0400

  Compiled Rx_EMIF Black as coal at 120


commit e7c8727193004f06e3dcc5216de1a46fc9ca9444
Merge: bca9923 76d1fe7
Author: John Alison
Date: Fri May 15 15:13:56 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.

2015-05-15 16:00:28 1:13:51 76d1fe7 f4adf4e FE 01 07 27182 181 0 138.58 MHz/100.0 MHz 150.53 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150515_171419 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,318 / 190,240 ( 31 % )
Total registers 93618
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 76d1fe734c5fb5231d137dfe1516c3a0bb2da10e
Author: Karol Krizka
Date: Fri May 15 09:37:26 2015 +0200

  Constants checksum now uses 10MHz clock.


commit a720bb129061bd6cd0f55e5a7bbf17760c48d84a
Author: John Alison
Date: Thu May 14 15:10:21 2015 -0400

  Duplicating more registers

AUXCommon Git Logs


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.

2015-05-14 16:02:05 1:15:16 a720bb1 f4adf4e FE 01 07 27190 181 0 138.58 MHz/100.0 MHz 150.53 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150514_171721 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,318 / 190,240 ( 31 % )
Total registers 93618
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit a720bb129061bd6cd0f55e5a7bbf17760c48d84a
Author: John Alison
Date: Thu May 14 15:10:21 2015 -0400

  Duplicating more registers


commit 1027fdec436f5f1d57ba7de6ee464b9eb8135ba5
Author: Jamie Saxon
Date: Wed May 13 17:38:55 2015 -0700

  fixing the bug patrick found

AUXCommon Git Logs


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.

2015-05-13 16:00:11 1:35:38 c356062 f4adf4e FE 01 07 27173 181 0 139.63 MHz/100.0 MHz 154.42 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150513_173549 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,343 / 190,240 ( 31 % )
Total registers 93539
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit c356062c101441cec5d9989e9fbd57537693837c
Author: Jamie Saxon
Date: Wed May 13 12:26:31 2015 -0700

  write spybuffers in test bench by default


commit 776ad7ecde9f7046cad17f72ca552f60d503dd27
Author: Jamie Saxon
Date: Tue May 5 13:01:08 2015 -0700

  write spybuffers in test bench by default

AUXCommon Git Logs


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.

2015-05-12 16:00:35 1:14:40 add87a4 f4adf4e FE 01 07 27202 181 0 139.63 MHz/100.0 MHz 154.42 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150512_171515 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,343 / 190,240 ( 31 % )
Total registers 93539
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit add87a4cc843c5672377a97b6863cd9d61dddb52
Author: Karol Krizka
Date: Tue May 12 19:43:42 2015 +0200

  Write constants to memory on 10MHz clock. Tested only with Rx_ROM.


commit e45c5e79441ebb93b035c88df19876fe17a77e26
Author: John Alison
Date: Tue May 12 13:33:36 2015 -0400

  Remove unused read logic in TF

AUXCommon Git Logs


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.

2015-05-11 16:00:07 1:14:11 461d03b 4490937 FE 01 07 27170 181 0 132.03 MHz/100.0 MHz 157.36 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150511_171418 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,187 / 190,240 ( 31 % )
Total registers 93600
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 461d03b0fb1b6fbac286f3689e3bbf45cf99cfc9
Author: John Alison
Date: Tue May 5 08:12:46 2015 -0500

  Move RxBasic to use standard emif


commit ecfe82af620a0fe10d35e13232dab23f1db6314f
Author: Karol Krizka
Date: Tue May 5 10:43:42 2015 +0200

  Ported the single clock DOOutputCatcher to RxDebug and made sure both pass synthesis.

AUXCommon Git Logs


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.


commit b8d6433973485fe3f248e55bdf30d4a6fe5b4289
Author: Karol Krizka
Date: Fri May 1 17:37:25 2015 +0200

  Added temperature sensor block.

2015-05-10 16:00:27 1:14:44 461d03b 4490937 FE 01 07 27170 181 0 132.03 MHz/100.0 MHz 157.36 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150510_171511 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,187 / 190,240 ( 31 % )
Total registers 93600
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 461d03b0fb1b6fbac286f3689e3bbf45cf99cfc9
Author: John Alison
Date: Tue May 5 08:12:46 2015 -0500

  Move RxBasic to use standard emif


commit ecfe82af620a0fe10d35e13232dab23f1db6314f
Author: Karol Krizka
Date: Tue May 5 10:43:42 2015 +0200

  Ported the single clock DOOutputCatcher to RxDebug and made sure both pass synthesis.

AUXCommon Git Logs


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.


commit b8d6433973485fe3f248e55bdf30d4a6fe5b4289
Author: Karol Krizka
Date: Fri May 1 17:37:25 2015 +0200

  Added temperature sensor block.

2015-05-09 16:00:08 1:14:36 461d03b 4490937 FE 01 07 27170 181 0 132.03 MHz/100.0 MHz 157.36 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150509_171444 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,187 / 190,240 ( 31 % )
Total registers 93600
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 461d03b0fb1b6fbac286f3689e3bbf45cf99cfc9
Author: John Alison
Date: Tue May 5 08:12:46 2015 -0500

  Move RxBasic to use standard emif


commit ecfe82af620a0fe10d35e13232dab23f1db6314f
Author: Karol Krizka
Date: Tue May 5 10:43:42 2015 +0200

  Ported the single clock DOOutputCatcher to RxDebug and made sure both pass synthesis.

AUXCommon Git Logs


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.


commit b8d6433973485fe3f248e55bdf30d4a6fe5b4289
Author: Karol Krizka
Date: Fri May 1 17:37:25 2015 +0200

  Added temperature sensor block.

2015-05-08 16:00:18 1:14:54 461d03b 4490937 FE 01 07 27170 181 0 132.03 MHz/100.0 MHz 157.36 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150508_171512 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,187 / 190,240 ( 31 % )
Total registers 93600
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 461d03b0fb1b6fbac286f3689e3bbf45cf99cfc9
Author: John Alison
Date: Tue May 5 08:12:46 2015 -0500

  Move RxBasic to use standard emif


commit ecfe82af620a0fe10d35e13232dab23f1db6314f
Author: Karol Krizka
Date: Tue May 5 10:43:42 2015 +0200

  Ported the single clock DOOutputCatcher to RxDebug and made sure both pass synthesis.

AUXCommon Git Logs


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.


commit b8d6433973485fe3f248e55bdf30d4a6fe5b4289
Author: Karol Krizka
Date: Fri May 1 17:37:25 2015 +0200

  Added temperature sensor block.

2015-05-07 16:00:07 1:14:21 461d03b 4490937 FE 01 07 27170 181 0 132.03 MHz/100.0 MHz 157.36 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150507_171428 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,187 / 190,240 ( 31 % )
Total registers 93600
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 461d03b0fb1b6fbac286f3689e3bbf45cf99cfc9
Author: John Alison
Date: Tue May 5 08:12:46 2015 -0500

  Move RxBasic to use standard emif


commit ecfe82af620a0fe10d35e13232dab23f1db6314f
Author: Karol Krizka
Date: Tue May 5 10:43:42 2015 +0200

  Ported the single clock DOOutputCatcher to RxDebug and made sure both pass synthesis.

AUXCommon Git Logs


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.


commit b8d6433973485fe3f248e55bdf30d4a6fe5b4289
Author: Karol Krizka
Date: Fri May 1 17:37:25 2015 +0200

  Added temperature sensor block.

2015-05-06 16:00:13 1:14:55 461d03b 4490937 FE 01 07 27170 181 0 132.03 MHz/100.0 MHz 157.36 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150506_171508 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,187 / 190,240 ( 31 % )
Total registers 93600
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 461d03b0fb1b6fbac286f3689e3bbf45cf99cfc9
Author: John Alison
Date: Tue May 5 08:12:46 2015 -0500

  Move RxBasic to use standard emif


commit ecfe82af620a0fe10d35e13232dab23f1db6314f
Author: Karol Krizka
Date: Tue May 5 10:43:42 2015 +0200

  Ported the single clock DOOutputCatcher to RxDebug and made sure both pass synthesis.

AUXCommon Git Logs


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.


commit b8d6433973485fe3f248e55bdf30d4a6fe5b4289
Author: Karol Krizka
Date: Fri May 1 17:37:25 2015 +0200

  Added temperature sensor block.

2015-05-05 16:00:02 1:14:18 461d03b 4490937 FE 01 07 27181 181 0 132.03 MHz/100.0 MHz 157.36 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150505_171420 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,187 / 190,240 ( 31 % )
Total registers 93600
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,802 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 461d03b0fb1b6fbac286f3689e3bbf45cf99cfc9
Author: John Alison
Date: Tue May 5 08:12:46 2015 -0500

  Move RxBasic to use standard emif


commit ecfe82af620a0fe10d35e13232dab23f1db6314f
Author: Karol Krizka
Date: Tue May 5 10:43:42 2015 +0200

  Ported the single clock DOOutputCatcher to RxDebug and made sure both pass synthesis.

AUXCommon Git Logs


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.


commit b8d6433973485fe3f248e55bdf30d4a6fe5b4289
Author: Karol Krizka
Date: Fri May 1 17:37:25 2015 +0200

  Added temperature sensor block.

2015-05-04 16:00:02 0:01:27 bb693c9 4490937 N/A 1740 6 22 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150504_160129 .

Leading Errors

Error (10349): VHDL Association List error at Rx.vhd(1426): formal "do_clk" does not exist File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1426
Error (10346): VHDL error at Rx.vhd(1425): formal port or parameter "clk" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1425
Error (10784): HDL error at TFInputBufferLogic.vhdl(23): see declaration for object "clk" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/TF/project/TFInputBufferLogic.vhdl Line: 23
Error (10346): VHDL error at Rx.vhd(1425): formal port or parameter "reset" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1425
Error (10784): HDL error at TFInputBufferLogic.vhdl(24): see declaration for object "reset" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/TF/project/TFInputBufferLogic.vhdl Line: 24
Error (10346): VHDL error at Rx.vhd(1425): formal port or parameter "read_enable" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1425
Error (10784): HDL error at TFInputBufferLogic.vhdl(25): see declaration for object "read_enable" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/TF/project/TFInputBufferLogic.vhdl Line: 25
Error (10346): VHDL error at Rx.vhd(1425): formal port or parameter "eoe_in" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1425
Error (10784): HDL error at TFInputBufferLogic.vhdl(27): see declaration for object "eoe_in" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/TF/project/TFInputBufferLogic.vhdl Line: 27
Error (10346): VHDL error at Rx.vhd(1425): formal port or parameter "sector_ready" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1425
Error (10784): HDL error at TFInputBufferLogic.vhdl(28): see declaration for object "sector_ready" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/TF/project/TFInputBufferLogic.vhdl Line: 28
...

Processor Git Logs


commit bb693c9f1b7d044f43df9b06991a2171be0c8ba6
Merge: 86583c3 9431515
Author: Jamie Saxon
Date: Mon May 4 09:12:21 2015 -0700

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030


commit 86583c31f785913ca2d563916366290b6fda2604
Author: Jamie Saxon
Date: Mon May 4 09:10:43 2015 -0700

  spy buffer to vme format

AUXCommon Git Logs


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.


commit b8d6433973485fe3f248e55bdf30d4a6fe5b4289
Author: Karol Krizka
Date: Fri May 1 17:37:25 2015 +0200

  Added temperature sensor block.

2015-05-03 16:00:02 0:01:45 2fd92df 4490937 N/A 1740 6 22 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150503_160147 .

Leading Errors

Error (10349): VHDL Association List error at Rx.vhd(1028): formal "nextevent" does not exist File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1028
Error (10346): VHDL error at Rx.vhd(1024): formal port or parameter "LD0" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1024
Error (10784): HDL error at DFSynchronization.vhd(45): see declaration for object "LD0" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/synchronization/DFSynchronization.vhd Line: 45
Error (10346): VHDL error at Rx.vhd(1024): formal port or parameter "LCTRL_N0" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1024
Error (10784): HDL error at DFSynchronization.vhd(46): see declaration for object "LCTRL_N0" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/synchronization/DFSynchronization.vhd Line: 46
Error (10346): VHDL error at Rx.vhd(1024): formal port or parameter "LWEN_N0" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1024
Error (10784): HDL error at DFSynchronization.vhd(47): see declaration for object "LWEN_N0" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/synchronization/DFSynchronization.vhd Line: 47
Error (10346): VHDL error at Rx.vhd(1024): formal port or parameter "LDOWN_N0" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1024
Error (10784): HDL error at DFSynchronization.vhd(48): see declaration for object "LDOWN_N0" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/synchronization/DFSynchronization.vhd Line: 48
Error (10346): VHDL error at Rx.vhd(1024): formal port or parameter "LD1" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1024
Error (10784): HDL error at DFSynchronization.vhd(51): see declaration for object "LD1" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/synchronization/DFSynchronization.vhd Line: 51
...

Processor Git Logs


commit 2fd92df4eac3d95eda21449ef333470ec6f22970
Author: Karol Krizka
Date: Sat May 2 01:25:47 2015 +0200

  Shit really compiles now.


commit fd3b1e85199ff9f2b141196f4e7b9cec9544cb64
Author: Karol Krizka
Date: Sat May 2 01:01:54 2015 +0200

  Things compile a bit better.c

AUXCommon Git Logs


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.


commit b8d6433973485fe3f248e55bdf30d4a6fe5b4289
Author: Karol Krizka
Date: Fri May 1 17:37:25 2015 +0200

  Added temperature sensor block.

2015-05-02 16:00:02 0:01:44 2fd92df 4490937 N/A 1740 6 22 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150502_160146 .

Leading Errors

Error (10349): VHDL Association List error at Rx.vhd(1028): formal "nextevent" does not exist File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1028
Error (10346): VHDL error at Rx.vhd(1024): formal port or parameter "LD0" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1024
Error (10784): HDL error at DFSynchronization.vhd(45): see declaration for object "LD0" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/synchronization/DFSynchronization.vhd Line: 45
Error (10346): VHDL error at Rx.vhd(1024): formal port or parameter "LCTRL_N0" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1024
Error (10784): HDL error at DFSynchronization.vhd(46): see declaration for object "LCTRL_N0" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/synchronization/DFSynchronization.vhd Line: 46
Error (10346): VHDL error at Rx.vhd(1024): formal port or parameter "LWEN_N0" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1024
Error (10784): HDL error at DFSynchronization.vhd(47): see declaration for object "LWEN_N0" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/synchronization/DFSynchronization.vhd Line: 47
Error (10346): VHDL error at Rx.vhd(1024): formal port or parameter "LDOWN_N0" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1024
Error (10784): HDL error at DFSynchronization.vhd(48): see declaration for object "LDOWN_N0" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/synchronization/DFSynchronization.vhd Line: 48
Error (10346): VHDL error at Rx.vhd(1024): formal port or parameter "LD1" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1024
Error (10784): HDL error at DFSynchronization.vhd(51): see declaration for object "LD1" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/synchronization/DFSynchronization.vhd Line: 51
...

Processor Git Logs


commit 2fd92df4eac3d95eda21449ef333470ec6f22970
Author: Karol Krizka
Date: Sat May 2 01:25:47 2015 +0200

  Shit really compiles now.


commit fd3b1e85199ff9f2b141196f4e7b9cec9544cb64
Author: Karol Krizka
Date: Sat May 2 01:01:54 2015 +0200

  Things compile a bit better.c

AUXCommon Git Logs


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.


commit b8d6433973485fe3f248e55bdf30d4a6fe5b4289
Author: Karol Krizka
Date: Fri May 1 17:37:25 2015 +0200

  Added temperature sensor block.

2015-05-01 16:00:02 0:01:31 ba9bf5c 4490937 N/A 1752 6 22 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150501_160133 .

Leading Errors

Error (10349): VHDL Association List error at Rx.vhd(1028): formal "nextevent" does not exist File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1028
Error (10346): VHDL error at Rx.vhd(1024): formal port or parameter "LD0" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1024
Error (10784): HDL error at DFSynchronization.vhd(45): see declaration for object "LD0" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/synchronization/DFSynchronization.vhd Line: 45
Error (10346): VHDL error at Rx.vhd(1024): formal port or parameter "LCTRL_N0" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1024
Error (10784): HDL error at DFSynchronization.vhd(46): see declaration for object "LCTRL_N0" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/synchronization/DFSynchronization.vhd Line: 46
Error (10346): VHDL error at Rx.vhd(1024): formal port or parameter "LWEN_N0" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1024
Error (10784): HDL error at DFSynchronization.vhd(47): see declaration for object "LWEN_N0" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/synchronization/DFSynchronization.vhd Line: 47
Error (10346): VHDL error at Rx.vhd(1024): formal port or parameter "LDOWN_N0" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1024
Error (10784): HDL error at DFSynchronization.vhd(48): see declaration for object "LDOWN_N0" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/synchronization/DFSynchronization.vhd Line: 48
Error (10346): VHDL error at Rx.vhd(1024): formal port or parameter "LD1" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 1024
Error (10784): HDL error at DFSynchronization.vhd(51): see declaration for object "LD1" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/synchronization/DFSynchronization.vhd Line: 51
...

Processor Git Logs


commit ba9bf5c9ebbcdfb5eb2fa55d3ce251d85ca4f94c
Author: Karol Krizka
Date: Fri May 1 18:20:27 2015 +0200

  Rx_EMIF compiles again in vsim.


commit 505feddade8954621eb81f99fc9ba78c0fb70bee
Author: Karol Krizka
Date: Fri May 1 18:14:17 2015 +0200

  Added temperature sensor.

AUXCommon Git Logs


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.


commit b8d6433973485fe3f248e55bdf30d4a6fe5b4289
Author: Karol Krizka
Date: Fri May 1 17:37:25 2015 +0200

  Added temperature sensor block.

2015-04-30 16:00:30 0:01:34 30fee5c 9937988 N/A 1777 24 4 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150430_160204 .

Leading Errors

Error (10481): VHDL Use Clause error at AMBConverter.vhd(100): design library "work" does not contain primary unit "aux_scfifo" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/synchronization/AMBConverter.vhd Line: 100
Error (293001): Quartus II Full Compilation was unsuccessful. 3 errors, 149 warnings
Error (213009): File name "Rx.sof" does not exist
Error (213009): File name "RxDebug_EMIF.pof" does not exist

Processor Git Logs


commit 30fee5cede29e3080dd6c7bc5470ea6edd724539
Merge: a19f412 9bfcd94
Author: John Alison
Date: Thu Apr 30 14:17:57 2015 -0500

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030


commit a19f4122cbec9c58197638babe2fd2717773853c
Author: John Alison
Date: Thu Apr 30 14:17:15 2015 -0500

  Fixing compile errors for Rx_ROM and EMIF

AUXCommon Git Logs


commit e9937988b0410a903a309ecf9d5e3682a85119da
Author: Karol Krizka
Date: Thu Apr 30 08:41:36 2015 +0200

  whitespace


commit 43719b025a0f79f2cb1043ed3dae62cf1eb2654c
Author: Karol Krizka
Date: Fri Apr 24 13:56:08 2015 +0200

  Add overflow and freeze to VMEBuffBlock.

2015-04-29 16:00:08 1:14:38 b3b49ce 3e565fd FE 01 07 27197 176 0 134.97 MHz/100.0 MHz 147.23 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150429_171446 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,273 / 190,240 ( 31 % )
Total registers 93535
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,817 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit b3b49ce685cabac13f1d017d082d5806072ae5ad
Merge: d17a9d0 f5f9058
Author: jwebster
Date: Tue Apr 28 10:58:57 2015 -0500

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030


commit d17a9d0977445c39b31e62a72d553d88cf7d6a58
Author: jwebster
Date: Tue Apr 28 10:58:52 2015 -0500

  Rx_EMIF nightly

AUXCommon Git Logs


commit 13e565fdd8a064917b8402ac3a4c56c4746337d9
Author: John Alison
Date: Sat Apr 25 17:59:05 2015 -0500

  Reset init state in prbs checker


commit 2bd250385141f8f6f531d23bbbf4795d0b4d92b4
Author: John Alison
Date: Sat Apr 25 12:14:32 2015 -0500

  Fixes for comiler warnings

2015-04-28 16:00:07 1:13:35 b3b49ce 3e565fd FE 01 07 27208 176 0 134.97 MHz/100.0 MHz 147.23 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150428_171342 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,273 / 190,240 ( 31 % )
Total registers 93535
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,769,817 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit b3b49ce685cabac13f1d017d082d5806072ae5ad
Merge: d17a9d0 f5f9058
Author: jwebster
Date: Tue Apr 28 10:58:57 2015 -0500

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030


commit d17a9d0977445c39b31e62a72d553d88cf7d6a58
Author: jwebster
Date: Tue Apr 28 10:58:52 2015 -0500

  Rx_EMIF nightly

AUXCommon Git Logs


commit 13e565fdd8a064917b8402ac3a4c56c4746337d9
Author: John Alison
Date: Sat Apr 25 17:59:05 2015 -0500

  Reset init state in prbs checker


commit 2bd250385141f8f6f531d23bbbf4795d0b4d92b4
Author: John Alison
Date: Sat Apr 25 12:14:32 2015 -0500

  Fixes for comiler warnings

2015-04-27 16:00:23 0:04:24 d60df24 3e565fd N/A 4528 39 12 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150427_160447 .

Leading Errors

Error (12014): Net "do_status[28]", which fans out to "vme_latches:vme_latches_inst|words_in[11][28]", cannot be assigned more than one value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 252
Error (12015): Net is fed by "DOEMIF:\gen_singledo:inst39|do_status[28]" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 24
Error (12015): Net is fed by "DOEMIF:\gen_singledo:inst39|local_cal_fail" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 96
Error (12014): Net "do_status[27]", which fans out to "vme_latches:vme_latches_inst|words_in[11][27]", cannot be assigned more than one value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 252
Error (12015): Net is fed by "DOEMIF:\gen_singledo:inst39|do_status[27]" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 24
Error (12015): Net is fed by "DOEMIF:\gen_singledo:inst39|local_cal_success" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 95
Error (12014): Net "do_status[26]", which fans out to "vme_latches:vme_latches_inst|words_in[11][26]", cannot be assigned more than one value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 252
Error (12015): Net is fed by "DOEMIF:\gen_singledo:inst39|do_status[26]" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 24
Error (12015): Net is fed by "DOEMIF:\gen_singledo:inst39|local_init_done" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 94
Error (293001): Quartus II Full Compilation was unsuccessful. 11 errors, 109 warnings
Error (213009): File name "Rx.sof" does not exist
...

Processor Git Logs


commit d60df2455464e45d7b924c43526b55eeaaf40106
Author: John Alison
Date: Mon Apr 27 15:35:07 2015 -0500

  Creatign logiclocks


commit cd947c118dc5cca801ca4a5ee2d4ddaba6ee0c4f
Merge: 32ab7fc a48a8ef
Author: jwebster
Date: Mon Apr 27 11:49:01 2015 -0500

  nightly merge

AUXCommon Git Logs


commit 13e565fdd8a064917b8402ac3a4c56c4746337d9
Author: John Alison
Date: Sat Apr 25 17:59:05 2015 -0500

  Reset init state in prbs checker


commit 2bd250385141f8f6f531d23bbbf4795d0b4d92b4
Author: John Alison
Date: Sat Apr 25 12:14:32 2015 -0500

  Fixes for comiler warnings

2015-04-26 16:00:02 0:04:03 98ee7ab 3e565fd N/A 4537 39 12 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150426_160405 .

Leading Errors

Error (12014): Net "do_status[28]", which fans out to "vme_latches:vme_latches_inst|words_in[11][28]", cannot be assigned more than one value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 252
Error (12015): Net is fed by "DOEMIF:\gen_singledo:inst39|do_status[28]" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 24
Error (12015): Net is fed by "DOEMIF:\gen_singledo:inst39|local_cal_fail" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 96
Error (12014): Net "do_status[27]", which fans out to "vme_latches:vme_latches_inst|words_in[11][27]", cannot be assigned more than one value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 252
Error (12015): Net is fed by "DOEMIF:\gen_singledo:inst39|do_status[27]" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 24
Error (12015): Net is fed by "DOEMIF:\gen_singledo:inst39|local_cal_success" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 95
Error (12014): Net "do_status[26]", which fans out to "vme_latches:vme_latches_inst|words_in[11][26]", cannot be assigned more than one value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 252
Error (12015): Net is fed by "DOEMIF:\gen_singledo:inst39|do_status[26]" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 24
Error (12015): Net is fed by "DOEMIF:\gen_singledo:inst39|local_init_done" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/DOEMIF.vhd Line: 94
Error (293001): Quartus II Full Compilation was unsuccessful. 11 errors, 109 warnings
Error (213009): File name "Rx.sof" does not exist
...

Processor Git Logs


commit 98ee7abb8737cdb3ec033957eca8d51e830bc682
Author: jwebster
Date: Sun Apr 26 11:22:31 2015 -0500

  Rx_EMIF nightly


commit 6b2bb26690a6b7c4ff4b5e5e09a18da025fe5cc4
Author: jwebster
Date: Sun Apr 26 01:22:27 2015 -0500

  Rx_ROM nightly

AUXCommon Git Logs


commit 13e565fdd8a064917b8402ac3a4c56c4746337d9
Author: John Alison
Date: Sat Apr 25 17:59:05 2015 -0500

  Reset init state in prbs checker


commit 2bd250385141f8f6f531d23bbbf4795d0b4d92b4
Author: John Alison
Date: Sat Apr 25 12:14:32 2015 -0500

  Fixes for comiler warnings

2015-04-25 16:00:27 0:01:41 6f7079e bd25038 N/A 1775 8 5 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150425_160208 .

Leading Errors

Error (10324): VHDL Expression error at Rx.vhd(38): expression ""11111110000000000001"" has 20 elements ; expected 24 elements. File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_EMIF/Rx.vhd Line: 38
Error (12153): Can't elaborate top-level user hierarchy
Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 78 warnings
Error (213009): File name "Rx.sof" does not exist
Error (213009): File name "RxDebug_EMIF.pof" does not exist

Processor Git Logs


commit 6f7079e0ab911909c11385943bea519ec10b5bd9
Author: John Alison
Date: Sat Apr 25 12:52:55 2015 -0500

  Compiling Rxdebug_ROM


commit bf649f78d0fbdb428c58ddd3f290dc5401c85822
Merge: 0c667fe 5ea643c
Author: John Alison
Date: Sat Apr 25 12:45:36 2015 -0500

  Merge branch 'master' of y:/FTK/Processor_1_20141030

AUXCommon Git Logs


commit 2bd250385141f8f6f531d23bbbf4795d0b4d92b4
Author: John Alison
Date: Sat Apr 25 12:14:32 2015 -0500

  Fixes for comiler warnings


commit b6fa94d726a6d2df6f2fdc0d4f579bd8127b8718
Author: Jamie Saxon
Date: Thu Apr 23 15:16:24 2015 -0700

  fix for hw merging

2015-04-24 16:00:01 1:16:00 8242973 6fa94d7 FE 0 110 27207 313 0 142.49 MHz/100.0 MHz 145.65 MHz/130.01 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_EMIF_master_20150424_171601 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 58,751 / 190,240 ( 31 % )
Total registers 90306
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,765,724 / 24,719,360 ( 31 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 824297398072a1841e8f72e0ecfe83541120d67d
Author: jwebster
Date: Fri Apr 24 15:26:40 2015 -0500

  edited all qsfs so fitters use specific seeds


commit 32cd19b77803f9c79d23e53b416c221006fbffd6
Merge: 3668b10 65bf963
Author: Patrick Bryant
Date: Fri Apr 24 13:21:22 2015 -0500

  Merge remote-tracking branch 'origin/master'

AUXCommon Git Logs


commit b6fa94d726a6d2df6f2fdc0d4f579bd8127b8718
Author: Jamie Saxon
Date: Thu Apr 23 15:16:24 2015 -0700

  fix for hw merging


commit aa785972151c03e3724b0ce8f063ce75239c6607
Author: Karol Krizka
Date: Wed Apr 22 11:04:09 2015 +0200

  Clean up of port order in aux_scfifo_lookahead.



RxDebug_ROM_master

Compile Started Compile Time Processor AUXCommon Version nInfo nWarnings nErrors fMax[0] fMax[1] Fitter Effort
2015-07-12 18:30:26 1:12:28 393e4d0 ac61546 FD 01 2F 28082 416 0 129.94 MHz/100.0 MHz 142.63 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150712_194254 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,829 / 190,240 ( 29 % )
Total registers 86546
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -5.555 RxBlock:RxBlock_i...dc_inst|halffullRxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:gen_slink:3:ldc_inst|halffull vme_latches:vme_l...nst|word_reg[15]vme_latches:vme_latches_inst|freeze_latch:gen_latches:3:latch_inst|word_reg[15]
2 -3.380 RxBlock:RxBlock_i...dc_inst|halffullRxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:gen_slink:1:ldc_inst|halffull vme_latches:vme_l...nst|word_reg[13]vme_latches:vme_latches_inst|freeze_latch:gen_latches:3:latch_inst|word_reg[13]
3 -3.267 RxBlock:RxBlock_i...dc_inst|halffullRxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:gen_slink:0:ldc_inst|halffull vme_latches:vme_l...nst|word_reg[12]vme_latches:vme_latches_inst|freeze_latch:gen_latches:3:latch_inst|word_reg[12]
4 -3.097 RxBlock:RxBlock_i...dc_inst|halffullRxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:gen_slink:2:ldc_inst|halffull vme_latches:vme_l...nst|word_reg[14]vme_latches:vme_latches_inst|freeze_latch:gen_latches:3:latch_inst|word_reg[14]

Processor Git Logs


commit 393e4d0ad77aa7ef1b5c0035b765afb97c185582
Author: Karol Krizka
Date: Thu Jul 9 22:04:12 2015 +0200

  Hold control registers consolidation.


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-11 18:30:35 1:11:43 393e4d0 ac61546 FD 01 2F 28082 416 0 129.94 MHz/100.0 MHz 142.63 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150711_194218 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,829 / 190,240 ( 29 % )
Total registers 86546
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -5.555 RxBlock:RxBlock_i...dc_inst|halffullRxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:gen_slink:3:ldc_inst|halffull vme_latches:vme_l...nst|word_reg[15]vme_latches:vme_latches_inst|freeze_latch:gen_latches:3:latch_inst|word_reg[15]
2 -3.380 RxBlock:RxBlock_i...dc_inst|halffullRxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:gen_slink:1:ldc_inst|halffull vme_latches:vme_l...nst|word_reg[13]vme_latches:vme_latches_inst|freeze_latch:gen_latches:3:latch_inst|word_reg[13]
3 -3.267 RxBlock:RxBlock_i...dc_inst|halffullRxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:gen_slink:0:ldc_inst|halffull vme_latches:vme_l...nst|word_reg[12]vme_latches:vme_latches_inst|freeze_latch:gen_latches:3:latch_inst|word_reg[12]
4 -3.097 RxBlock:RxBlock_i...dc_inst|halffullRxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:gen_slink:2:ldc_inst|halffull vme_latches:vme_l...nst|word_reg[14]vme_latches:vme_latches_inst|freeze_latch:gen_latches:3:latch_inst|word_reg[14]

Processor Git Logs


commit 393e4d0ad77aa7ef1b5c0035b765afb97c185582
Author: Karol Krizka
Date: Thu Jul 9 22:04:12 2015 +0200

  Hold control registers consolidation.


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-10 18:32:40 1:11:59 393e4d0 ac61546 FD 01 2F 28082 416 0 129.94 MHz/100.0 MHz 142.63 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150710_194439 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,829 / 190,240 ( 29 % )
Total registers 86546
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Top Failing Paths

Slack From To
1 -5.555 RxBlock:RxBlock_i...dc_inst|halffullRxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:gen_slink:3:ldc_inst|halffull vme_latches:vme_l...nst|word_reg[15]vme_latches:vme_latches_inst|freeze_latch:gen_latches:3:latch_inst|word_reg[15]
2 -3.380 RxBlock:RxBlock_i...dc_inst|halffullRxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:gen_slink:1:ldc_inst|halffull vme_latches:vme_l...nst|word_reg[13]vme_latches:vme_latches_inst|freeze_latch:gen_latches:3:latch_inst|word_reg[13]
3 -3.267 RxBlock:RxBlock_i...dc_inst|halffullRxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:gen_slink:0:ldc_inst|halffull vme_latches:vme_l...nst|word_reg[12]vme_latches:vme_latches_inst|freeze_latch:gen_latches:3:latch_inst|word_reg[12]
4 -3.097 RxBlock:RxBlock_i...dc_inst|halffullRxBlock:RxBlock_inst|Xcvr_Road:road_inst|SimpleSimplexLDC:gen_slink:2:ldc_inst|halffull vme_latches:vme_l...nst|word_reg[14]vme_latches:vme_latches_inst|freeze_latch:gen_latches:3:latch_inst|word_reg[14]

Processor Git Logs


commit 393e4d0ad77aa7ef1b5c0035b765afb97c185582
Author: Karol Krizka
Date: Thu Jul 9 22:04:12 2015 +0200

  Hold control registers consolidation.


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-08 18:30:25 1:06:34 393826d ac61546 FD 01 2F 28074 406 0 133.98 MHz/100.0 MHz 142.76 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150708_193659 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,772 / 190,240 ( 29 % )
Total registers 86427
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-07 18:33:29 1:07:10 393826d ac61546 FD 01 2F 28074 406 0 133.98 MHz/100.0 MHz 142.76 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150707_194039 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,772 / 190,240 ( 29 % )
Total registers 86427
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-06 18:30:22 1:08:03 393826d ac61546 FD 01 2F 28074 406 0 133.98 MHz/100.0 MHz 142.76 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150706_193825 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,772 / 190,240 ( 29 % )
Total registers 86427
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit dac61546e3d985fe4086535724c5337931fbc926
Author: Karol Krizka
Date: Mon Jul 6 21:24:23 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.


commit 4402ccd2905084aec3b09dacfadd55e5b6f7e241
Author: Karol Krizka
Date: Mon Jul 6 21:22:29 2015 +0200

  Added HOLD ignore on SLINK, disable for SimpleSimplexL*C.

2015-07-05 18:30:10 1:07:41 393826d 5e26926 FD 01 2F 28074 406 0 133.98 MHz/100.0 MHz 142.76 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150705_193751 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,772 / 190,240 ( 29 % )
Total registers 86427
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-07-04 18:30:24 1:08:51 393826d 5e26926 FD 01 2F 28074 406 0 133.98 MHz/100.0 MHz 142.76 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150704_193915 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,772 / 190,240 ( 29 % )
Total registers 86427
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-07-03 18:30:39 1:07:57 393826d 5e26926 FD 01 2F 28074 406 0 133.98 MHz/100.0 MHz 142.76 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150703_193836 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,772 / 190,240 ( 29 % )
Total registers 86427
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-07-02 18:30:25 1:07:35 393826d 5e26926 FD 01 2F 28074 406 0 133.98 MHz/100.0 MHz 142.76 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150702_193800 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,772 / 190,240 ( 29 % )
Total registers 86427
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-07-01 18:30:09 1:07:46 393826d 5e26926 FD 01 2F 28074 406 0 133.98 MHz/100.0 MHz 142.76 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150701_193755 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,772 / 190,240 ( 29 % )
Total registers 86427
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-30 18:30:33 1:08:20 393826d 5e26926 FD 01 2F 28074 406 0 133.98 MHz/100.0 MHz 142.76 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150630_193853 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,772 / 190,240 ( 29 % )
Total registers 86427
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-29 18:30:09 1:07:26 393826d 5e26926 FD 01 2F 28074 406 0 133.98 MHz/100.0 MHz 142.76 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150629_193735 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,772 / 190,240 ( 29 % )
Total registers 86427
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-28 18:30:39 1:08:15 393826d 5e26926 FD 01 2F 28074 406 0 133.98 MHz/100.0 MHz 142.76 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150628_193854 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,772 / 190,240 ( 29 % )
Total registers 86427
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-27 18:30:20 1:07:11 393826d 5e26926 FD 01 2F 28074 406 0 133.98 MHz/100.0 MHz 142.76 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150627_193731 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,772 / 190,240 ( 29 % )
Total registers 86427
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-26 18:30:32 1:08:10 393826d 5e26926 FD 01 2F 28074 406 0 133.98 MHz/100.0 MHz 142.76 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150626_193842 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,772 / 190,240 ( 29 % )
Total registers 86427
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-25 18:30:09 1:08:28 393826d 5e26926 FD 01 2F 28074 406 0 133.98 MHz/100.0 MHz 142.76 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150625_193837 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,772 / 190,240 ( 29 % )
Total registers 86427
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 393826dcfe2ecb9fcbc78d8cfae366b39aaef8a5
Author: jwebste2
Date: Wed Jun 24 23:16:01 2015 -0500

  Updated Rx_EMIF/Rx.qsf so that removal of duplicate registers is not turned off for the entire TF - this boosted fMax by 35 MHz in the push150MHz branch


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-24 18:30:02 1:07:39 a2c66eb 5e26926 FD 01 2F 28074 406 0 133.98 MHz/100.0 MHz 142.76 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150624_193741 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,772 / 190,240 ( 29 % )
Total registers 86427
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit a2c66ebb6ffebb4c229c730ac29c47ccd6b24739
Author: jwebste2
Date: Wed Jun 24 14:48:54 2015 -0500

  updated forced duplicate registers in Rx_ROM/Rx.qsf : TFRoadOragnizer fanout


commit a374e80c2a4f22206946de3087c873c5f52f4215
Author: Jordan Webster
Date: Wed Jun 24 10:49:45 2015 -0700

  trying to fix compile fails from disconnected line in DOSpyBuffers

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-23 18:30:28 0:01:51 550cde7 5e26926 N/A 1717 0 5 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150623_183219 .

Leading Errors

Error (10346): VHDL error at Rx.vhd(1647): formal port or parameter "top_outLiveLayers" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_ROM/Rx.vhd Line: 1647
Error (10784): HDL error at DOSpyBuffers.vhdl(60): see declaration for object "top_outLiveLayers" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/spybuffers/DOSpyBuffers.vhdl Line: 60
Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 0 warnings
Error (213009): File name "Rx.sof" does not exist
Error (213009): File name "RxDebug_ROM.pof" does not exist

Processor Git Logs


commit 550cde79611c68c3c124677cce976e1c46ca5e49
Author: Jordan Webster
Date: Tue Jun 23 17:45:14 2015 -0700

  fixed the LiveLayers typo in DO


commit b4f07514a735cf710098899f3f86624d2f84e8ac
Author: jwebster
Date: Tue Jun 23 16:05:33 2015 -0500

  * updated DOSpyBuffers to include Live Layers
  * shortened sector ID in spy buffers from 16 bits to 13 bits and moved position of layermap
  * Updated TB run script to dump waveform output files, wlf & do

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-22 18:30:09 1:11:23 b0ea31e 5e26926 FD 01 2F 28074 407 0 127.23 MHz/100.0 MHz 135.78 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150622_194132 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,861 / 190,240 ( 29 % )
Total registers 86384
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit b0ea31e40c33a115b76a45fe9793180ed1cffda7
Merge: 2126c76 424e6cc
Author: John Alison
Date: Sun Jun 21 07:36:10 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030


commit 424e6cc647c622cad3a3cc80bea550fbc95cb159
Author: John Alison
Date: Sun Jun 21 13:36:16 2015 +0200

  Duplicating more TF registers

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-21 18:30:33 1:11:20 b0ea31e 5e26926 FD 01 2F 28074 407 0 127.23 MHz/100.0 MHz 135.78 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150621_194153 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,861 / 190,240 ( 29 % )
Total registers 86384
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit b0ea31e40c33a115b76a45fe9793180ed1cffda7
Merge: 2126c76 424e6cc
Author: John Alison
Date: Sun Jun 21 07:36:10 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030


commit 424e6cc647c622cad3a3cc80bea550fbc95cb159
Author: John Alison
Date: Sun Jun 21 13:36:16 2015 +0200

  Duplicating more TF registers

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-20 18:30:37 1:11:27 5975ae1 5e26926 FD 01 2F 28074 407 0 127.23 MHz/100.0 MHz 135.78 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150620_194204 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,861 / 190,240 ( 29 % )
Total registers 86384
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 5975ae14e045d34856d22389db903b59bd074f49
Author: John Alison
Date: Sat Jun 20 22:19:59 2015 +0200

  More Duplications


commit 74f9648de8673baa0048564d2c4ec9cb692e53e4
Author: jwebste2
Date: Fri Jun 19 16:05:55 2015 -0500

  updated nightly compile script

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-19 18:30:40 1:11:12 74f9648 5e26926 FD 01 2F 28074 407 0 127.23 MHz/100.0 MHz 135.78 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150619_194152 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,861 / 190,240 ( 29 % )
Total registers 86384
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 74f9648de8673baa0048564d2c4ec9cb692e53e4
Author: jwebste2
Date: Fri Jun 19 16:05:55 2015 -0500

  updated nightly compile script


commit d77dd035e78d6ac25c3284a702c96cc9af48c4b3
Author: jwebste2
Date: Fri Jun 19 11:33:48 2015 -0500

  updated nightly scripts

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-18 18:30:41 1:09:50 771ba18 5e26926 FD 01 2F 28074 407 0 127.23 MHz/100.0 MHz 135.78 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150618_194031 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,861 / 190,240 ( 29 % )
Total registers 86384
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 771ba18f6632802ff5785640080c93d1940f0952
Author: jwebster
Date: Thu Jun 18 12:23:08 2015 -0500

  nightly compile scripts


commit ae7993cf22664900fc7bdd42478db9eae038b315
Author: jwebster
Date: Thu Jun 18 12:19:20 2015 -0500

  typo in nightly script

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-17 18:30:09 1:10:43 251ae51 5e26926 FD 01 2F 28074 407 0 127.23 MHz/100.0 MHz 135.78 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150617_194052 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,861 / 190,240 ( 29 % )
Total registers 86384
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 251ae51b9e8c16cca3383d84ca59aa952127bbff
Merge: 137fa0b c6a09d2
Author: Jordan Webster
Date: Tue Jun 16 16:34:31 2015 -0700

  Merge branch 'Jordan'


commit c6a09d24a35da4fbb37382514d5ba57cf7b94777
Author: Jordan Webster
Date: Tue Jun 16 16:17:45 2015 -0700

  updated waves for TF road record types

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-16 18:30:50 1:11:18 251ae51 5e26926 FD 01 2F 28074 407 0 127.23 MHz/100.0 MHz 135.78 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150616_194208 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,861 / 190,240 ( 29 % )
Total registers 86384
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 251ae51b9e8c16cca3383d84ca59aa952127bbff
Merge: 137fa0b c6a09d2
Author: Jordan Webster
Date: Tue Jun 16 16:34:31 2015 -0700

  Merge branch 'Jordan'


commit c6a09d24a35da4fbb37382514d5ba57cf7b94777
Author: Jordan Webster
Date: Tue Jun 16 16:17:45 2015 -0700

  updated waves for TF road record types

AUXCommon Git Logs


commit 35e2692639b4311c9c8cd89f484da170d9c80e5b
Author: Karol Krizka
Date: Tue Jun 16 16:45:45 2015 +0200

  Updated ssmap compile.do to get ssmap testbench to work.


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor

2015-06-15 18:30:30 1:11:08 2468a04 8a74633 FD 01 2F 28074 407 0 127.23 MHz/100.0 MHz 135.78 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150615_194138 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,861 / 190,240 ( 29 % )
Total registers 86384
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,935,444 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 2468a04f311c98f181c37eb974c2d9df354789ab
Merge: 3930cca b14f0e8
Author: unknown
Date: Mon Jun 15 16:32:21 2015 -0700

  Merge remote-tracking branch 'origin/master' into NewDCFlagMap

  Conflicts:
  Rx_EMIF/Rx.qsf
  combined_testbench/compileTF.do


commit 3930cca9f6592df279ed403b6402fe5dfdf26965
Author: unknown
Date: Mon Jun 15 16:29:15 2015 -0700

  looping in EMIF as well and all projects comile. merging

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-14 18:30:40 1:09:23 b14f0e8 8a74633 FD 01 2D 28016 402 0 135.81 MHz/100.0 MHz 139.57 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150614_194003 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,380 / 190,240 ( 29 % )
Total registers 81528
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,703 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit b14f0e8d7ffe11a233bc97fea5a5954a39d99ee5
Author: John Alison
Date: Sun Jun 14 15:11:22 2015 +0200

  Updates to the latency to match the chi2


commit 0313f9ef396c612f0e88d34aa4ca66b4439812a7
Author: John Alison
Date: Sun Jun 14 14:40:46 2015 +0200

  Add fanout

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-13 18:30:22 1:09:12 c5178a2 8a74633 FD 01 2D 28016 402 0 135.81 MHz/100.0 MHz 139.57 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150613_193934 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,380 / 190,240 ( 29 % )
Total registers 81528
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,703 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit c5178a29264f669246ec94237617d390f4fb7534
Author: John Alison
Date: Sat Jun 13 04:25:56 2015 -0400

  Bring in changes from pushing timing


commit f5a890edb8cb9e307dfe5d05ecbc6ce981296420
Author: John Alison
Date: Sat Jun 13 04:18:13 2015 -0400

  Valdated Sim

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-12 18:30:22 1:09:11 3451fb6 8a74633 FD 01 2D 28016 402 0 135.81 MHz/100.0 MHz 139.57 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150612_193933 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,380 / 190,240 ( 29 % )
Total registers 81528
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,703 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 3451fb662aa8738c2d9d1117509eaf7cc017d3a0
Merge: bbb0304 210641e
Author: John Alison
Date: Fri Jun 12 08:04:58 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030


commit 210641e0744c83d23ae9b78dca223dfe75bc6cc3
Author: Karol Krizka
Date: Fri Jun 12 14:03:16 2015 +0200

  Adjusted TFNomFitter delays to componstate for registering everything.

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-11 18:30:08 1:09:36 94e6851 8a74633 FD 01 2D 28016 402 0 135.81 MHz/100.0 MHz 139.57 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150611_193944 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,380 / 190,240 ( 29 % )
Total registers 81528
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,703 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 94e68519ec9e7986d2bf0a608cff6f74f9afa2db
Merge: 93f3ae2 414f714
Author: jwebster
Date: Thu Jun 11 11:49:52 2015 -0500

  Merge branch 'master' of Y:\FTK\Processor_1_20141030


commit 414f714ab9f30dc915a4320b681432b779f4b101
Author: Karol Krizka
Date: Thu Jun 11 11:14:02 2015 +0200

  Delay output layermaps in TFNomFitter to make them synchronous with chi2 output.

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-10 18:33:15 0:00:32 e5f42e6 8a74633 N/A 1711 0 4 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150610_183347 .

Leading Errors

Error (10481): VHDL Use Clause error at TFSctFitterShiftRegister.vhdl(51): design library "work" does not contain primary unit "shiftreg_20x62" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/TF/project/TFSctFitterShiftRegister.vhdl Line: 51
Error (293001): Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings
Error (213009): File name "Rx.sof" does not exist
Error (213009): File name "RxDebug_ROM.pof" does not exist

Processor Git Logs


commit e5f42e64ca661618a3a0f640298be9ed3fc0c259
Author: Karol Krizka
Date: Wed Jun 10 23:26:49 2015 +0200

  Updated delays in fitters to account for added pipelining.


commit 52f1a1c793f4f258dd78d7cc3264fa90c97805f4
Author: Karol Krizka
Date: Wed Jun 10 11:20:47 2015 +0200

  Updates to TF loading in run_MergedDOLoop.

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-09 18:31:41 1:10:43 983c302 8a74633 FD 01 2D 28013 402 0 135.81 MHz/100.0 MHz 139.57 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150609_194224 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,380 / 190,240 ( 29 % )
Total registers 81528
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,703 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 983c302a638342a01a7c8891b1920ce4fcea1149
Author: Karol Krizka
Date: Tue Jun 9 11:43:25 2015 +0200

  Fixed typo in TFRoadSynchronizer to get it to compile.


commit c80b123e480c7e57594429e23530bee0addae55e
Author: Karol Krizka
Date: Tue Jun 9 11:33:08 2015 +0200

  Fixed roads with ID 0 comming out of buffer logic.

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-08 18:30:37 1:10:39 955880d 8a74633 FD 01 2D 28013 402 0 135.81 MHz/100.0 MHz 139.57 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150608_194116 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,380 / 190,240 ( 29 % )
Total registers 81528
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,703 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 955880d2146344ecd2554d90e65b39d4ebd13d65
Author: jwebster
Date: Thu Jun 4 11:50:42 2015 -0500

  updated nightly run script for generating html


commit ad804a530f4fd3f89e897e2622b6978fe11277bd
Author: jwebster
Date: Thu Jun 4 11:48:27 2015 -0500

  updated compile script to checkout before pulling

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-07 18:30:09 1:10:50 955880d 8a74633 FD 01 2D 28013 402 0 135.81 MHz/100.0 MHz 139.57 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150607_194059 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,380 / 190,240 ( 29 % )
Total registers 81528
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,703 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 955880d2146344ecd2554d90e65b39d4ebd13d65
Author: jwebster
Date: Thu Jun 4 11:50:42 2015 -0500

  updated nightly run script for generating html


commit ad804a530f4fd3f89e897e2622b6978fe11277bd
Author: jwebster
Date: Thu Jun 4 11:48:27 2015 -0500

  updated compile script to checkout before pulling

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-06 18:30:38 1:10:50 955880d 8a74633 FD 01 2D 28013 402 0 135.81 MHz/100.0 MHz 139.57 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150606_194128 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,380 / 190,240 ( 29 % )
Total registers 81528
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,703 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 955880d2146344ecd2554d90e65b39d4ebd13d65
Author: jwebster
Date: Thu Jun 4 11:50:42 2015 -0500

  updated nightly run script for generating html


commit ad804a530f4fd3f89e897e2622b6978fe11277bd
Author: jwebster
Date: Thu Jun 4 11:48:27 2015 -0500

  updated compile script to checkout before pulling

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-05 18:30:56 1:10:10 955880d 8a74633 FD 01 2D 28013 402 0 135.81 MHz/100.0 MHz 139.57 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150605_194106 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,380 / 190,240 ( 29 % )
Total registers 81528
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,703 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 955880d2146344ecd2554d90e65b39d4ebd13d65
Author: jwebster
Date: Thu Jun 4 11:50:42 2015 -0500

  updated nightly run script for generating html


commit ad804a530f4fd3f89e897e2622b6978fe11277bd
Author: jwebster
Date: Thu Jun 4 11:48:27 2015 -0500

  updated compile script to checkout before pulling

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-03 18:30:31 1:10:53 e899ea5 8a74633 FD 01 2D 27138 391 0 127.94 MHz/100.0 MHz 140.35 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150603_194124 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,239 / 190,240 ( 29 % )
Total registers 81425
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit e899ea59c83f690d4c1cd7d70c303a824840b432
Author: John Alison
Date: Tue May 26 17:48:00 2015 -0400

  Quick bug fixes


commit e45eb723ec14f5268fa6512c97bd77199a1b5270
Merge: 13648d4 f0bca2d
Author: John Alison
Date: Tue May 26 17:41:19 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-02 18:30:39 1:10:28 e899ea5 8a74633 FD 01 2D 27138 391 0 127.94 MHz/100.0 MHz 140.35 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150602_194107 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,239 / 190,240 ( 29 % )
Total registers 81425
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit e899ea59c83f690d4c1cd7d70c303a824840b432
Author: John Alison
Date: Tue May 26 17:48:00 2015 -0400

  Quick bug fixes


commit e45eb723ec14f5268fa6512c97bd77199a1b5270
Merge: 13648d4 f0bca2d
Author: John Alison
Date: Tue May 26 17:41:19 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-06-01 18:30:09 1:10:31 e899ea5 8a74633 FD 01 2D 27138 391 0 127.94 MHz/100.0 MHz 140.35 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150601_194040 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,239 / 190,240 ( 29 % )
Total registers 81425
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit e899ea59c83f690d4c1cd7d70c303a824840b432
Author: John Alison
Date: Tue May 26 17:48:00 2015 -0400

  Quick bug fixes


commit e45eb723ec14f5268fa6512c97bd77199a1b5270
Merge: 13648d4 f0bca2d
Author: John Alison
Date: Tue May 26 17:41:19 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-05-31 18:30:44 1:10:25 e899ea5 8a74633 FD 01 2D 27138 391 0 127.94 MHz/100.0 MHz 140.35 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150531_194109 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,239 / 190,240 ( 29 % )
Total registers 81425
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit e899ea59c83f690d4c1cd7d70c303a824840b432
Author: John Alison
Date: Tue May 26 17:48:00 2015 -0400

  Quick bug fixes


commit e45eb723ec14f5268fa6512c97bd77199a1b5270
Merge: 13648d4 f0bca2d
Author: John Alison
Date: Tue May 26 17:41:19 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-05-30 18:30:09 1:11:21 e899ea5 8a74633 FD 01 2D 27138 391 0 127.94 MHz/100.0 MHz 140.35 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150530_194130 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,239 / 190,240 ( 29 % )
Total registers 81425
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit e899ea59c83f690d4c1cd7d70c303a824840b432
Author: John Alison
Date: Tue May 26 17:48:00 2015 -0400

  Quick bug fixes


commit e45eb723ec14f5268fa6512c97bd77199a1b5270
Merge: 13648d4 f0bca2d
Author: John Alison
Date: Tue May 26 17:41:19 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-05-29 18:30:29 1:10:24 e899ea5 8a74633 FD 01 2D 27138 391 0 127.94 MHz/100.0 MHz 140.35 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150529_194053 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,239 / 190,240 ( 29 % )
Total registers 81425
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit e899ea59c83f690d4c1cd7d70c303a824840b432
Author: John Alison
Date: Tue May 26 17:48:00 2015 -0400

  Quick bug fixes


commit e45eb723ec14f5268fa6512c97bd77199a1b5270
Merge: 13648d4 f0bca2d
Author: John Alison
Date: Tue May 26 17:41:19 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-05-28 18:30:09 1:10:27 e899ea5 8a74633 FD 01 2D 27138 391 0 127.94 MHz/100.0 MHz 140.35 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150528_194036 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,239 / 190,240 ( 29 % )
Total registers 81425
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit e899ea59c83f690d4c1cd7d70c303a824840b432
Author: John Alison
Date: Tue May 26 17:48:00 2015 -0400

  Quick bug fixes


commit e45eb723ec14f5268fa6512c97bd77199a1b5270
Merge: 13648d4 f0bca2d
Author: John Alison
Date: Tue May 26 17:41:19 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-05-27 18:30:17 1:10:24 e899ea5 8a74633 FD 01 2D 27138 391 0 127.94 MHz/100.0 MHz 140.35 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150527_194041 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,239 / 190,240 ( 29 % )
Total registers 81425
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit e899ea59c83f690d4c1cd7d70c303a824840b432
Author: John Alison
Date: Tue May 26 17:48:00 2015 -0400

  Quick bug fixes


commit e45eb723ec14f5268fa6512c97bd77199a1b5270
Merge: 13648d4 f0bca2d
Author: John Alison
Date: Tue May 26 17:41:19 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-05-26 18:30:03 1:10:29 e899ea5 8a74633 FD 01 2D 27138 391 0 127.94 MHz/100.0 MHz 140.35 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150526_194032 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,239 / 190,240 ( 29 % )
Total registers 81425
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit e899ea59c83f690d4c1cd7d70c303a824840b432
Author: John Alison
Date: Tue May 26 17:48:00 2015 -0400

  Quick bug fixes


commit e45eb723ec14f5268fa6512c97bd77199a1b5270
Merge: 13648d4 f0bca2d
Author: John Alison
Date: Tue May 26 17:41:19 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit f8a7463380c301720effb2e514a58067a520adf5
Author: John Alison
Date: Tue May 26 11:26:52 2015 -0400

  Bug fix to FIFOWordMonitor


commit 3d6b8d092be673637e0bb3c227d702f1536d9f00
Author: John Alison
Date: Tue May 26 11:18:28 2015 -0400

  Registering input of FIFOWordMon

2015-05-25 18:30:14 0:01:01 2cc96cd caea3fb N/A 1711 0 5 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150525_183115 .

Leading Errors

Error (10346): VHDL error at RoadProcessor.vhd(209): formal port or parameter "extmem_emif_success" must have actual or default value File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/RoadProcessor.vhd Line: 209
Error (10784): HDL error at ExtMemClockInterface.vhd(71): see declaration for object "extmem_emif_success" File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/MergedDO/project/ExtMemClockInterface.vhd Line: 71
Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 22 warnings
Error (213009): File name "Rx.sof" does not exist
Error (213009): File name "RxDebug_ROM.pof" does not exist

Processor Git Logs


commit 2cc96cde8a5f922073369b789173663351425956
Merge: 098d4ed 1dd5d2c
Author: unknown
Date: Mon May 25 13:17:30 2015 -0700

  Merge remote-tracking branch 'origin/master'


commit 098d4edd67819277b12e3f2a37cb29b1e00ffc96
Author: unknown
Date: Mon May 25 13:17:08 2015 -0700

  adding monitoring of emif calibration success flag. DO_Status[22]

AUXCommon Git Logs


commit dcaea3fbed25b7af853bdc0af598b8623aa2b100
Author: John Alison
Date: Mon May 18 10:54:00 2015 -0400

  Adding duplicated registers


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.

2015-05-24 18:30:40 1:09:58 df20913 caea3fb FD 01 2C 27138 391 0 135.72 MHz/100.0 MHz 145.48 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150524_194038 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,231 / 190,240 ( 29 % )
Total registers 79421
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit df209137fc23835ad7980541ad18539681003c2f
Author: John Alison
Date: Sat May 23 15:32:14 2015 -0400

  Bug fixing'


commit b837d788aaec7dd2e830ef853da8799dd8bad9d8
Author: John Alison
Date: Sat May 23 14:28:23 2015 -0400

  Updating types for reg duplication

AUXCommon Git Logs


commit dcaea3fbed25b7af853bdc0af598b8623aa2b100
Author: John Alison
Date: Mon May 18 10:54:00 2015 -0400

  Adding duplicated registers


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.

2015-05-23 18:30:08 1:10:31 df20913 caea3fb FD 01 2C 27138 391 0 135.72 MHz/100.0 MHz 145.48 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150523_194039 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,231 / 190,240 ( 29 % )
Total registers 79421
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit df209137fc23835ad7980541ad18539681003c2f
Author: John Alison
Date: Sat May 23 15:32:14 2015 -0400

  Bug fixing'


commit b837d788aaec7dd2e830ef853da8799dd8bad9d8
Author: John Alison
Date: Sat May 23 14:28:23 2015 -0400

  Updating types for reg duplication

AUXCommon Git Logs


commit dcaea3fbed25b7af853bdc0af598b8623aa2b100
Author: John Alison
Date: Mon May 18 10:54:00 2015 -0400

  Adding duplicated registers


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.

2015-05-22 18:30:47 1:09:36 07726fa caea3fb FD 01 2C 27138 391 0 135.72 MHz/100.0 MHz 145.48 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150522_194023 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,231 / 190,240 ( 29 % )
Total registers 79421
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 07726fab89e1db23051bfa0ddc7dd06f32c20828
Author: John Alison
Date: Fri May 22 17:55:18 2015 -0400

  Updating assignment editor


commit eef1e2e278e696145fe58e20947561d926805088
Author: John Alison
Date: Fri May 22 15:32:10 2015 -0400

  Adding pipelinning to TFRoadSynchron

AUXCommon Git Logs


commit dcaea3fbed25b7af853bdc0af598b8623aa2b100
Author: John Alison
Date: Mon May 18 10:54:00 2015 -0400

  Adding duplicated registers


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.

2015-05-21 18:30:09 1:09:31 df7037b caea3fb FD 01 2C 27138 391 0 135.72 MHz/100.0 MHz 145.48 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150521_193940 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,231 / 190,240 ( 29 % )
Total registers 79421
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit df7037bcac3a8f382231a83d62e5d266f2462959
Author: John Alison
Date: Thu May 21 17:46:41 2015 -0400

  Bug fixes


commit 678aeda869940ddad456b623047485a0b411165a
Author: John Alison
Date: Thu May 21 17:37:42 2015 -0400

  Register and pipeline TF SpyBuffers

AUXCommon Git Logs


commit dcaea3fbed25b7af853bdc0af598b8623aa2b100
Author: John Alison
Date: Mon May 18 10:54:00 2015 -0400

  Adding duplicated registers


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.

2015-05-20 18:30:02 1:10:25 151d62e caea3fb FD 01 2C 27138 391 0 135.72 MHz/100.0 MHz 145.48 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150520_194027 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,231 / 190,240 ( 29 % )
Total registers 79421
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 151d62e815d48241e8e54ad9cd62973678c9defc
Merge: 55fd268 89a43d0
Author: jwebster
Date: Wed May 20 14:27:29 2015 -0500

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030


commit 89a43d0ad108663b1ef72847857a26bd714c277e
Merge: 0896203 0f8b1c6
Author: John Alison
Date: Wed May 20 12:41:56 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit dcaea3fbed25b7af853bdc0af598b8623aa2b100
Author: John Alison
Date: Mon May 18 10:54:00 2015 -0400

  Adding duplicated registers


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.

2015-05-19 18:30:38 0:00:59 1e2affd caea3fb N/A 1711 0 4 - - -
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150519_183137 .

Leading Errors

Error (10349): VHDL Association List error at Rx.vhd(1334): formal "pix_stream_req" does not exist File: C:/Users/jswebster/Desktop/stable/Processor_1_20141030/RxDebug_ROM/Rx.vhd Line: 1334
Error (293001): Quartus II Full Compilation was unsuccessful. 3 errors, 22 warnings
Error (213009): File name "Rx.sof" does not exist
Error (213009): File name "RxDebug_ROM.pof" does not exist

Processor Git Logs


commit 1e2affdf03163ff5e4f1809728b67b13764cc432
Merge: 5cc631f f323f6e
Author: jwebster
Date: Tue May 19 16:00:44 2015 -0500

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030


commit f323f6e3ed788536e9d97fd85e24d888972de7b8
Merge: 5785233 2a14d00
Author: John Alison
Date: Tue May 19 15:33:56 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit dcaea3fbed25b7af853bdc0af598b8623aa2b100
Author: John Alison
Date: Mon May 18 10:54:00 2015 -0400

  Adding duplicated registers


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.

2015-05-18 18:30:41 1:10:25 b9448c9 caea3fb FD 01 2C 27138 389 0 136.76 MHz/100.0 MHz 144.84 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150518_194106 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 54,031 / 190,240 ( 28 % )
Total registers 78922
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit b9448c98fea67d886aa335c384ecfaf02d00634b
Merge: 50a748d 90bedca
Author: jwebster
Date: Mon May 18 16:01:01 2015 -0500

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030


commit 90bedcacae2e982eedae73f1b99934f9b6985ccf
Merge: 971d123 77a1150
Author: John Alison
Date: Mon May 18 15:56:29 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit dcaea3fbed25b7af853bdc0af598b8623aa2b100
Author: John Alison
Date: Mon May 18 10:54:00 2015 -0400

  Adding duplicated registers


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.

2015-05-17 18:30:10 1:05:16 3311423 f4adf4e FD 01 2C 26925 367 0 134.63 MHz/100.0 MHz 129.62 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150517_193526 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,507 / 190,240 ( 31 % )
Total registers 92790
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 331142308b5f30d4b1805d5c9175e721e54c9ba8
Author: John Alison
Date: Sat May 16 09:55:18 2015 -0400

  Compiled Rx_EMIF Black as coal at 120


commit e7c8727193004f06e3dcc5216de1a46fc9ca9444
Merge: bca9923 76d1fe7
Author: John Alison
Date: Fri May 15 15:13:56 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.

2015-05-16 18:30:16 1:04:52 3311423 f4adf4e FD 01 2C 26931 367 0 134.63 MHz/100.0 MHz 129.62 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150516_193508 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,507 / 190,240 ( 31 % )
Total registers 92790
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 331142308b5f30d4b1805d5c9175e721e54c9ba8
Author: John Alison
Date: Sat May 16 09:55:18 2015 -0400

  Compiled Rx_EMIF Black as coal at 120


commit e7c8727193004f06e3dcc5216de1a46fc9ca9444
Merge: bca9923 76d1fe7
Author: John Alison
Date: Fri May 15 15:13:56 2015 -0400

  Merge branch 'master' of eshop1:/net/designs/FTK/Processor_1_20141030

AUXCommon Git Logs


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.

2015-05-15 18:30:22 1:04:58 76d1fe7 f4adf4e FD 01 2C 26937 368 0 134.63 MHz/100.0 MHz 129.62 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150515_193520 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,507 / 190,240 ( 31 % )
Total registers 92790
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 76d1fe734c5fb5231d137dfe1516c3a0bb2da10e
Author: Karol Krizka
Date: Fri May 15 09:37:26 2015 +0200

  Constants checksum now uses 10MHz clock.


commit a720bb129061bd6cd0f55e5a7bbf17760c48d84a
Author: John Alison
Date: Thu May 14 15:10:21 2015 -0400

  Duplicating more registers

AUXCommon Git Logs


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.

2015-05-14 18:32:02 1:05:09 a720bb1 f4adf4e FD 01 2C 26934 368 0 134.63 MHz/100.0 MHz 129.62 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150514_193711 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,507 / 190,240 ( 31 % )
Total registers 92790
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit a720bb129061bd6cd0f55e5a7bbf17760c48d84a
Author: John Alison
Date: Thu May 14 15:10:21 2015 -0400

  Duplicating more registers


commit 1027fdec436f5f1d57ba7de6ee464b9eb8135ba5
Author: Jamie Saxon
Date: Wed May 13 17:38:55 2015 -0700

  fixing the bug patrick found

AUXCommon Git Logs


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.

2015-05-13 18:30:18 1:06:29 1027fde f4adf4e FD 01 2C 26925 368 0 134.63 MHz/100.0 MHz 129.62 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150513_193647 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,507 / 190,240 ( 31 % )
Total registers 92790
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 1027fdec436f5f1d57ba7de6ee464b9eb8135ba5
Author: Jamie Saxon
Date: Wed May 13 17:38:55 2015 -0700

  fixing the bug patrick found


commit c356062c101441cec5d9989e9fbd57537693837c
Author: Jamie Saxon
Date: Wed May 13 12:26:31 2015 -0700

  write spybuffers in test bench by default

AUXCommon Git Logs


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.

2015-05-12 18:30:32 1:05:57 76bcfc7 f4adf4e FD 01 2C 26949 368 0 134.63 MHz/100.0 MHz 129.62 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150512_193629 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,507 / 190,240 ( 31 % )
Total registers 92790
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 76bcfc743a69ce5dc66ae3c16f0d9561d90a1b8c
Merge: a2195a4 add87a4
Author: John Alison
Date: Tue May 12 16:58:10 2015 -0400

  Merge branch 'master' of eshop1.uchicago.edu:/net/designs/FTK/Processor_1_20141030


commit a2195a4704b3e090df7410603896717eb43383dc
Author: John Alison
Date: Tue May 12 13:52:12 2015 -0400

  Duplicating the logic going to the checksum

AUXCommon Git Logs


commit 7f4adf4ed2a54d7d0ec86c9ffa78d845c054fc58
Author: Karol Krizka
Date: Tue May 12 09:27:17 2015 +0200

  Fix prbs_any by initializing first pattern to all 1.


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.

2015-05-11 18:30:12 1:10:39 461d03b 4490937 FD 01 2C 26925 368 0 139.43 MHz/100.0 MHz 143.16 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150511_194051 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,384 / 190,240 ( 31 % )
Total registers 92824
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 461d03b0fb1b6fbac286f3689e3bbf45cf99cfc9
Author: John Alison
Date: Tue May 5 08:12:46 2015 -0500

  Move RxBasic to use standard emif


commit ecfe82af620a0fe10d35e13232dab23f1db6314f
Author: Karol Krizka
Date: Tue May 5 10:43:42 2015 +0200

  Ported the single clock DOOutputCatcher to RxDebug and made sure both pass synthesis.

AUXCommon Git Logs


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.


commit b8d6433973485fe3f248e55bdf30d4a6fe5b4289
Author: Karol Krizka
Date: Fri May 1 17:37:25 2015 +0200

  Added temperature sensor block.

2015-05-10 18:30:20 1:10:32 461d03b 4490937 FD 01 2C 26925 368 0 139.43 MHz/100.0 MHz 143.16 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150510_194052 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,384 / 190,240 ( 31 % )
Total registers 92824
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 461d03b0fb1b6fbac286f3689e3bbf45cf99cfc9
Author: John Alison
Date: Tue May 5 08:12:46 2015 -0500

  Move RxBasic to use standard emif


commit ecfe82af620a0fe10d35e13232dab23f1db6314f
Author: Karol Krizka
Date: Tue May 5 10:43:42 2015 +0200

  Ported the single clock DOOutputCatcher to RxDebug and made sure both pass synthesis.

AUXCommon Git Logs


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.


commit b8d6433973485fe3f248e55bdf30d4a6fe5b4289
Author: Karol Krizka
Date: Fri May 1 17:37:25 2015 +0200

  Added temperature sensor block.

2015-05-09 18:30:15 1:10:34 461d03b 4490937 FD 01 2C 26925 368 0 139.43 MHz/100.0 MHz 143.16 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150509_194049 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,384 / 190,240 ( 31 % )
Total registers 92824
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 461d03b0fb1b6fbac286f3689e3bbf45cf99cfc9
Author: John Alison
Date: Tue May 5 08:12:46 2015 -0500

  Move RxBasic to use standard emif


commit ecfe82af620a0fe10d35e13232dab23f1db6314f
Author: Karol Krizka
Date: Tue May 5 10:43:42 2015 +0200

  Ported the single clock DOOutputCatcher to RxDebug and made sure both pass synthesis.

AUXCommon Git Logs


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.


commit b8d6433973485fe3f248e55bdf30d4a6fe5b4289
Author: Karol Krizka
Date: Fri May 1 17:37:25 2015 +0200

  Added temperature sensor block.

2015-05-08 18:30:21 1:10:26 461d03b 4490937 FD 01 2C 26925 368 0 139.43 MHz/100.0 MHz 143.16 MHz/120.0 MHz STANDARD
Get files:
  scp -r ${USER}@eshop1.uchicago.edu:/net/designs/FTK/Nightlies/compile_RxDebug_ROM_master_20150508_194047 .

Resource Usage Summary

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name Rx
Top-level Entity Name Rx
Family Arria V
Device 5AGXFB7H4F35C4
Timing Models Final
Logic utilization (in ALMs) 59,384 / 190,240 ( 31 % )
Total registers 92824
Total pins 247 / 656 ( 38 % )
Total virtual pins 0
Total block memory bits 7,932,758 / 24,719,360 ( 32 % )
Total DSP Blocks 0 / 1,156 ( 0 % )
Total HSSI RX PCSs 17 / 24 ( 71 % )
Total HSSI PMA RX Deserializers 17 / 24 ( 71 % )
Total HSSI TX PCSs 13 / 24 ( 54 % )
Total HSSI TX Channels 13 / 24 ( 54 % )
Total PLLs 2 / 40 ( 5 % )
Total DLLs 1 / 4 ( 25 % )

Processor Git Logs


commit 461d03b0fb1b6fbac286f3689e3bbf45cf99cfc9
Author: John Alison
Date: Tue May 5 08:12:46 2015 -0500

  Move RxBasic to use standard emif


commit ecfe82af620a0fe10d35e13232dab23f1db6314f
Author: Karol Krizka
Date: Tue May 5 10:43:42 2015 +0200

  Ported the single clock DOOutputCatcher to RxDebug and made sure both pass synthesis.

AUXCommon Git Logs


commit b449093711a4cfa247e81e195606b7c49c7f3981
Author: Karol Krizka
Date: Fri May 1 17:38:16 2015 +0200

  Fixed XcvrGroupMonitor's non-sync-checked signal connections.


commit b8d6433973485fe3f248e55bdf30d4a6fe5b4289
Author: Karol Krizka
Date: Fri May 1 17:37:25 2015 +0200

  Added temperature sensor block.