[Ftk_hardware] At this Thursday FTK meeting: talk by Yasu on Data Formatter study using real data

Tiehui Liu thliu at fnal.gov
Wed May 16 17:34:03 CDT 2012

Dear All,

Since his first talk at FTK meeting, Yasu has done a lot work to study the Data Formatter bandwidth requirements using real beam data, both at FPGA/board level as well as at system level. 
This is work in progress, but I think that the studies are advanced, complete and interesting enough to give a good status/summary report. The results also give us a pretty good idea
about the bandwidth requirements both upstream and downstream of Data Formatter layer, using real beam data...  scaling up to 14 TeV at high pile up.

To complete the picture, Jamieson will give a brief update on the layout status of the prototype Data Formatter board, and also initial firmware considerations for the core routing algorithm. 



On Apr 19, 2012, at 8:16 AM, Tiehui Liu wrote:

> Hi, everyone,
> Yasu is a new postdoc (joint UC-Fermilab) who arrived Fermilab early April from Japan and started working with us on Data Formatter. His first month is spent on
> learning about all the basics to better prepare him working on the DF hardware. He has learned a lot within past few weeks, and I encouraged him to
> give a talk at today's meeting to tell people what he has learned so far (and the SCT/Pixel detector models he built to understand the detector module-ROD-tower mapping).
> Please come to the meeting and meet Yasu today. 
> cheers,
> Ted
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