[Ftk_hardware] VME access for the AUX card
paola.giannetti at pi.infn.it
Sun Dec 26 04:12:27 CST 2010
Mel Shochet wrote:
> Dear Paola,
I agree that VME and "not serialized communication lines" between the
AUX board and the AMB is again something we have to discuss.
Since the P3 connector is used for serialized links (it is specialized
for that), I was thinking to use VME user defined pins for
board-to-board TTL connections. Can we use J2 pins? For example these
could be used for Hold and Freeze signals.
Regarding VME I suppose we have the possibility to use 2 VME slaves, one
in the AUX board and one in the AMboard, reducing to zero the extra
signals we have to pass between the 2 and decoupling the 2 designs.
The AMB VME is under discussion and 2 proposals are going to be tried in
the next prototype:
(1) try to use 64 bit VME transfers. This implies slave firmware will
(2) try to use flash rams for the patterns banks.
If we find an agreement about using the 64 or 32 bit transfer, we could
develop a single VME slave and use it every where, changing only the
VME internal addressing.
Again we should choose a single responsible that study and propose the
basic f9irmware for every body, like we should do it for functions that
are shared between the AUX board and the final board.
Coming to other details:
we have a 5 bit geographical address to which both the boards have to
answer (the slot number), however we can choose an extra bit that will
distinguish between the 2 boards belonging to the same slot. So we have
to decide how to share the board addresses.
Unfortunately from what Francesco is learning on the new VME CPU (Atlas
like), we don't have the possibility to use the entire field of VME
addresses (32 bits). This is a general problem that will affect also
Illinois and Fermilab.
It is not totally clear yet, but the use of a large number of address
bits is strongly discouraged. And more powerful is the VME CPU (more
memory it has) less VME space is available.
So let's consider the possibility that we have only roughly 20 bits for
internal addressing. We will need an internal register to choose
different memory location fields (Fifos, Spy buffers, AMchips, SS and AM
Maps, Fit Constant memories.....).
In conclusion we have to plan the VME addressing. I suggest to start
with a Francesco's description of what he is learning from the CPU use.
Than we really need to choose a responsible of VME logic if we want to
create a standard slave.
> We will need VME access for the AUX card to load the FPGAs, read
> out the Spy Buffers, etc. This will presumably come from the AM
> card. Have you assigned P3 pins for the VME signals going between the
> AM and AUX cards?
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