Features
- Single-width, 9Ux400VME standard module;
- 48 LVDS input channels per Chip (96 channels/board);
- Input resolution of 1.2ns;
- Minimum pulse width of 4.8ns between pulses;
- Max. 10 hits per collision for each wire;
- First trigger level latency adjustable to 10us;
- Four separate intermediate data buffers with adjustable depth;
- VME read-out with 32-bit or 64-bit CBLT capability;
- Power used: +5V/7A and -5V/0.5A from the backplane;
- Board generates: -3.3V/1.5A available on the front panel.
