General Design
The TDC Module has been built around two Altera Stratix FPGAs. The special capabilitie s of this device are the availability of 840MHz LVDS inputs, multiple phase locked clo ck modules, and abundant memory. The TDC system would operate with an input resolution of 1.2ns, a minimum input pulse width of 4.8ns and a minimum separation of 4.8ns between pulses.
Memory pipelines, with a depth equivalent to up to 10us, are included for each channel to allow deadtimeless operation. After a first-level trigger, data pass into one of four separate intermediate buffers for processing. After a second-level trigger, the data are passed through a processor implemented in the FPGA to encode the relative time-to-digital values for the input pulses. Each wire input can accept up to 10 hits per collision. This processing and moving of the data takes seven microseconds. The results are then loaded into the local VME buffer for readout.
As an additional feature, the TDC board also generates trigger flags for a tracking processor called the Extremely Fast Tracker (XFT). This separate path uses the same input data, but uses a different processor, also implemented in the FPGA. The results, along with a 22ns clock, are sent out via backplane connector P3. The features of the TDC board can be adapted and/or modified by loading new design firmware in the configuration memories on board.
TDC Single Channel Flow Chart
- LVDS pulse converted to a 10-bit data bus via SERDES Block;
- Any channel can be blocked out with a VME command;
- Data passes through a 512word RAM (The Pipeline);
- The chip is fitted with a 4-buffer DAQ system
- On first-level trigger pulse, up to 64 words are written into one of four buffers;
- On second-level trigger pulse, buffer content enters Edge Detector Block;
- Hits are calculated and stored into VME Event Memory for readout.