All trigger paths and trigger bits in Stream J


The trigger paths depend on what trigger table is used. The table below is based on the Physica table (Physics_0_01_v24) which contains the largest dataset by Sep. 10, 2001.

  1. Path Dimuon_CMUCMU1.5_v2
    	Level 1 trigger L1_TWO_CMU1.5_PT1.5_v2     	         bit # 49
    	 (TWO CMU muons: Pt>1.5, each matched to XTRP tracks Pt>1.5)
    	Level 2 trigger L2_AUTO_L1_TWO_CMU1.5_PT1.5_v1           bit # 21 
    	 (TWO CMU muons: Pt>1.5 : Auto accept)
    	Level 3 trigger: Pt> 1.5, |del(x)| < 30 (CMU)            bit # 4
    	                (auto accept)             
    
  2. Path Dimuon_CMUCMX1.5_v5
    	Level 1 trigger L1_CMU1.5_PT1.5_&_CMX1.5_PT2_PS10_v1     bit # 41 
    	 ( CMU Pt>1.5, matched XTRP Pt>1.5 
               &  CMX Pt>1.5, matched XTRP Pt>2.0,
    	   prescale 10 )	
    	Level 2 trigger L2_AUTO_L1_CMU1.5_PT1.5_&_CMX1.5_PT2_v1  bit # 5 
    	 ( same Pt cuts : Auto accept )
    	Level 3 trigger: Pt> 1.5, |del(x)| < 30 (CMU), 30 (CMX)  bit # 5
    			(auto accept)
    
  3. Path Dimuon_L3PS10_L1_CMU1.5_PT1.5_&_CMX1.5_PT2_v1
    	Level 1 trigger L1_CMU1.5_PT1.5_&_CMX1.5_PT2_PS10_v1     bit # 41
    	  ( same as the cut in Path 2)
    	Level 2 trigger L2_AUTO_L1_CMU1.5_PT1.5_&_CMX1.5_PT2_v1  bit # 5
    		(Auto accept)
    	Level 3 trigger: Pt> 1.5, |del(x)| < 30 (CMU), 30 (CMX)  bit # 6
    		(auto accept with prescale=10)
    
  4. Path Dimuon_L3PS10_L1_TWO_CMU1.5_PT1.5_v1
    	Level 1 trigger L1_TWO_CMU1.5_PT1.5_v2                    bit # 49 
    	  ( same as the cut in Path 1)
    	Level 2 trigger L2_AUTO_L1_TWO_CMU1.5_PT1.5_v1            bit # 21 
    		(Auto accept)
    	Level 3 trigger: Pt> 1.5, |del(x)| < 30 (CMU)             bit # 7
    	        (auto accept with prescale=10)
    
  5. Path Jpsi_CMUCMU1.5_v1
    	Level 1 trigger L1_TWO_CMU1.5_PT1.5_v2                    bit # 49 
    	 (TWO CMU muons: Pt>1.5, each matched to XTRP tracks Pt>1.5)
    	Level 2 trigger L2_AUTO_L1_TWO_CMU1.5_PT1.5_v1            bit # 21
    		(auto accept)
    	Level 3 trigger: Pt> 1.5, |del(x)| < 30 (CMU) for each muons
    			 2.7< Mass < 4.0, | del(Z1-Z2) | < 10, opp. charge
    			 (auto accept)			          bit # 22
    
  6. Path Jpsi_CMUCMX1.5_v3
    	Level 1 trigger L1_CMU1.5_PT1.5_&_CMX1.5_PT2_PS10_v1      bit # 41 
    	  ( same as the cut in Path 2)
    	Level 2 trigger L2_AUTO_L1_CMU1.5_PT1.5_&_CMX1.5_PT2_v1   bit # 5 
    		(Auto accept)
    	Level 3 trigger: Pt> 1.5, |del(x)| < 30 (CMU), 30 (CMX)
    			 2.7< Mass < 4.0, | del(Z1-Z2) | < 10, opp. charge
    			 (auto accept)				  bit # 23
    
  7. Path Muon_CMU1.5_v2
    	Level 1 trigger L1_CMU1.5_PT1.5_PS250_v1         bit # 43 
    	   ( CMU Pt>1.5, matched XTRP>1.5, prescale=250)
    	Level 2 trigger L2_AUTO_L1_CMU1.5_PT1.5_v1       bit # 4 
    		(Auto accept)
    	Level 3 tigger: Pt> 1.5,  |del(x)| < 30 (CMU)    bit # 27
    		(auto accept)
    
  8. Path Muon_CMUP8_v2
    	Level 1 trigger L1_CMU6_PT8_v1                   bit # 47 
    	   ( CMU Pt>6., matched XTRP>8. )
    	Level 2 trigger L2_AUTO_L1_CMU6_PT8_v1           bit # 6 
    		(Auto accept)
    	Level 3: Pt > 12,  |del(x)| < 10 (CMU), 10(CMP)  bit # 29
    		(auto accept) 
    
  9. Path Muon_CMX12_v5
    	Level 1 trigger L1_CMX6_PT8_PS10_v1            bit # 45 
    	   ( CMX Pt>6.0, matched XTRP>8., prescale=10)
    	Level 2 trigger L2_AUTO_L1_CMX6_PT8_v1         bit # 8
    		(Auto accept)
    	Level 3:  Pt > 12,  |del(x)| < 10 (CMX)        bit # 30
    		(auto accept)
    
  10. Path Muon_L3PS10_L1_CMU1.5_PT1.5_v1
    	Level 1 trigger L1_CMU1.5_PT1.5_PS250_v1       bit # 43 
    	   ( CMU Pt>1.5, matched XTRP>1.5, prescale=250)
    	Level 2 trigger L2_AUTO_L1_CMU1.5_PT1.5_v1     bit # 4 
    		(Auto accept)
    	Level 3 tigger: Pt> 1.5,  |del(x)| < 30 (CMU)  bit # 31
    		(auto accept with prescale 10)
    
  11. Path Muon_L3PS10_L1_CMU6_PT8_v1
    	Level 1 trigger L1_CMU6_PT8_v1                  bit # 47 
    	   ( CMU Pt>6.0, matched XTRP>8.0, prescale=250)	
    	Level 2 trigger L2_AUTO_L1_CMU6_PT8_v1          bit # 6
    		(Auto accept)
    	Level 3: Pt > 12,  |del(x)| < 10 (CMU)          bit # 32
    		(auto accept with prescale 10) 
    
  12. Path Muon_L3PS10_L1_CMX6_PT8_v1
    	Level 1 trigger L1_CMX6_PT8_PS10_v1             bit # 45 
    	   (CMX Pt>6.0, matched XTRP Pt>8.0, prescale=10)
    	Level 2 trigger L2_AUTO_L1_CMX6_PT8_v1          bit # 8
    		(Auto accept)
    	Level 3:  Pt > 12,  |del(x)| < 10 (CMX)         bit # 33
    		(auto accept with prescale 10)     
    
  13. Path Muon_L3tag_L1_CMUP6_PT8_v2
    	Level 1 trigger L1_CMUP6_PT8_PS0_v1             bit # 0 
    	   (CMU Pt>6.0, matched XTRP Pt>8.0
    	    CMP Pt>3.0, CMP_NUMBER_OF_LAYERS  > 2.0 ) 
    	Level 2 trigger L2_AUTO_L1_CMUP6_PT8_v1         bit # 7 
    		(Auto accept)
    	Level 3: Pt > 12,  |del(x)| < 10 (CMU), 10(CMP) bit # 34
    		(auto accept with prescale=10) 
    


24 Sep 2001, Un-ki Yang