ATLAS Tilecal Electronics Design Review

Design Review Issues

The following points arose from discussions at the design review for the 3-in-1 and Mother Board.

1. Effect on 7-pole shaper of capacitance of PMT anode and divider board, as well as component tolerances.
  These stray capacitances have been measured and documented. The effect of component tolerances has also been investigated and documented. The schematics have been updated with the necessary tolerances.

Report written .

Stray capacitances affecting the charge injection system  have also been measured.

Report written .

2. Temperature analysis of 3-in-1
  The operating temperature of all active components was measured in free air. Then the temperature of the hottest component was measured in the operating configuration with the shield cooled to its nominal operating temperature of 19° C. Its temperature during operation will be less than 30° C.

Report written.

3. Power supply rejection factor
  We have measured the power supply noise rejection as a function of frequency. Results are characterized as the maximum noise allowed for 0.5 ADC noise counts. A Vicor supply has been purchased. It is well within the allowed noise range.

Report written.

4. Capacitor type
  Decide on specification of dielectric. There are concerns of reliability.

Manufacturers were contacted and characteristics obtained.

Report written

5. Burn-in

Evaluate need to burn-in and the time and temperature program for burn-in.

A one week burn-in program is planned for all completed boards.

Report written.

6. Use of Californium source for neutron tests
  Check radiation dose from photons.

The dose from photons is less than the photon dose in the final application.

Report written

7. Single point of failure analysis
  Analayze for each part of the system the possible failure types and the implications.

Report written


8. Updates to schematics
  Add voltage rating of capacitors and power of resistors. A footnote might indicate the default values with non-default values called out explicitly.

Done for all schematics for Version 3.0 and later.

9. Updates to mechanical drawing of 3-in-1 card
  Modify tolerances on mechanical drawing to be realistic.


10. Look for coherent noise on LVL1 trigger sums.
  In progress.   11. Radiation tests of Mother Board before PRR.
  What can be done here? Evaluation of individual components? Preliminary tests with Version 2?

In progress.