May 25, 1999
Proposed Burn-in Procedures


This note describes the burn-in procedures planned for the TileCal 3-in-1 cards and Mother Boards at the University of Chicago. The proposal follows procedures outlined in Ref. 1.

1. Overview

It is proposed to conduct a burn-in of fully assembled PC board systems with the goal of eliminating infant mortality and freak failures. The former correspond to failures introduced by the PC board assembly process while the latter correspond to premature component failures of well manufactured parts. For the type of system involved here the typical infant mortality lifetime is estimated as 5-20 hours and the freak lifetime as 1000 hours. Statistics accumulated during the burn-in process will allow us to check the validity of this model and to confirm the suitability of the burn-in period. Since the failure rate varies logarithmically with test time, there will be only limited capability to increase the useful duration of the test beyond what is planned.

A burn-in period of 1 week is proposed, at an elevated ambient temperature of 65° C. This duration is typical of industrial procedures and should be achievable with the planned delivery schedule. The temperature is close to the maximum operating temperature for the components since die temperatures will significantly exceed the ambient temperature.

The temperature dependence of the failure rate is expected to follow an Arrhenius model, where the reaction rate varies as exp(-EA/kT). A reasonable estimate of the activation energy EA for the type of electronic components used here is 1 eV [Ref. 2]. This means that at a temperature of 65° C the aging is 100 times faster than at the normal operating temperature of 25° C. Hence the burn-in period will correspond to 1.9 years of normal operation. During normal ATLAS operating conditions the temperature of the hottest component on the 3-in-1 card has been measured to be ~ 25° C. The duration of the burn-in test corresponds to 17 times the estimated freak lifetime.

It is proposed to use a markovian burn-in for which any failure is repaired and the testing restarted at the beginning of the one-week period. The procedure is repeated until a board passes the test.

2. Operational Details for 3-in-1 Cards

For testing 3-in-1 cards we will use a group of 5 Mother Board assemblies produced in the pre-production process. Each Mother Board will be equipped with 48 3-in-1 cards to give a total of 240 cards under test at one time. The system will be powered and at least one of the Mother Board assemblies will be under continuous readout and testing. The time and location of failures will be logged. After one week of burn-in, an operator will remove faulty cards for repair and good cards for delivery to the sites for PMT block assembly. A fresh set of 3-in-1 cards will be installed and the process repeated. It is estimated that the weekly changeover can be done in less than a day. During the intervening week, faulty cards will be repaired.

It is estimated that this process should yield about 200 tested, burned-in 3-in-1 cards each week. The full production volume could be completed in ~60 weeks.

3. Operational Details for Mother Boards

Facilities are planned to burn-in 5 Mother Board sets per week. The four boards of each set will first be equipped with mezzanine cards. This includes 9 LVL1 adder cards, 1 integrator ADC card, and 1 interface control card. These assemblies will be mounted on a 3-m-long rigid support and interconnection cables will be installed. After completing preliminary tests the Mother Board assembly will be covered with a thermal enclosure and heated to 65° C. Low voltage power will be applied throughout the test, but it is impractical to run logic tests continuously on all systems during burn-in. At the conclusion of the one-week burn-in each assembly will be retested.

It is estimated that this process should yield about 4 Mother Board sets per week and that the full production volume could be completed in ~70 weeks.


  1. Burn-In: An Engineering approach to the design an analysis of burn-in procedures, F. Jensen and N. E. Petersen, ISBN 0-471-10215-6, Wiley, 1982.
  2. Test Methods and Procedures for Microelectronics, MIL-STD-883B.