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-- DRAW CONTROL_BOARD No.3 VHDL   version 3.1 boards  Aug 2000 --
-----------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
ENTITY ab3 IS
PORT (
      tube             : IN std_logic_vector(5 DOWNTO 0);
      multi_sel        : IN std_logic;
      drw_sel          : IN std_logic;
      data_in          : IN std_logic;
      rxw              : IN std_logic;
      enable           : IN std_logic;
      clock            : IN std_logic;
      dly_en           : OUT std_logic;
      sel              : OUT std_logic_vector(24 DOWNTO 13);
      p                : OUT std_logic_vector(7 DOWNTO 0);
      data_out_en      : OUT std_logic );
END ab3;

architecture logic_layout of ab3 is
      SIGNAL shft_q    : std_logic_vector(12 DOWNTO 0);
      SIGNAL shft_d    : std_logic_vector(12 DOWNTO 0);
      SIGNAL shft_clk  : std_logic;
      SIGNAL ltch_q    : std_logic_vector(7 DOWNTO 0);
      SIGNAL ltch_d    : std_logic_vector(7 DOWNTO 0);
      SIGNAL ltch_clk  : std_logic;
      SIGNAL shift_in  : std_logic;
      SIGNAL latch_ext : std_logic;

BEGIN
    sel(13) <= drw_sel when (tube = "001101") else '0';
    sel(14) <= drw_sel when (tube = "001110") else '0';
    sel(15) <= drw_sel when (tube = "001111") else '0';
    sel(16) <= drw_sel when (tube = "010000") else '0';
    sel(17) <= drw_sel when (tube = "010001") else '0';
    sel(18) <= drw_sel when (tube = "010010") else '0';
    sel(19) <= drw_sel when (tube = "010011") else '0';
    sel(20) <= drw_sel when (tube = "010100") else '0';
    sel(21) <= drw_sel when (tube = "010101") else '0';
    sel(22) <= drw_sel when (tube = "010110") else '0';
    sel(23) <= drw_sel when (tube = "010111") else '0';
    sel(24) <= drw_sel when (tube = "011000") else '0';
	shift_in <= (drw_sel or multi_sel) when (tube = "111100") else '0';
	latch_ext <= (drw_sel or multi_sel) when (tube = "111101") else '0';
     shft_clk <= '1' when ((shift_in = '1') and (clock = '1')) else '0';
     shft_d(0) <= shft_q(12) when (rxw = '1') else data_in;
     process(shft_clk) begin
       if(falling_edge(shft_clk) ) then
         shft_d(12 downto 1) <= shft_q(11 downto 0);
       end if;
     end process;
     process(shft_clk) begin
        if(rising_edge(shft_clk) ) then
          shft_q(12 downto 0) <= shft_d(12 downto 0);
        end if;
      end process;
     ltch_clk <= '1' when ((enable = '1') and (shift_in = '1')) else '0';
     process (ltch_clk) begin
        if(falling_edge(ltch_clk) ) then
           ltch_d(7 downto 0) <= shft_q(10 downto 3);
        end if;
     end process;
     process (ltch_clk) begin
        if(rising_edge(ltch_clk) ) then
          ltch_q(7 downto 0) <= ltch_d(7 downto 0);
        end if;
     end process;
     p(7 downto 0) <= ltch_q(7 downto 0);
        dly_en <= latch_ext;

     process(drw_sel,tube) begin
        if(drw_sel = '1') then
           if((tube(5 downto 4) = "00") or 
              (tube(5 downto 3) = "010") or 
              (tube(5 downto 0) = "011000")) then
               data_out_en <= '1';
           else 
               data_out_en <= '0';
           end if;
        else
           data_out_en <= '0';
        end if;
     end process;

end logic_layout;