Overview of VHDL Modules used in the Interface Card

This is the main module that collects data from the 8 digitizer boards, performs
a CRC check on this input data, transforms 2 bit serial data from each TileDMU
(2 TileDMU chips per digitizer board) into 32 bit parallel words, holds them in
a dual port memory before they are sent over the SLINK/G-link connection.  At
the end of each data frame it also appends a global CRC checksum that is used by
the destination card to check for transmission errors over the link.

This module makes a decision about the start of a data frame by comparing the
incoming control and data signals from the digitizers. Two out of six digitizers
are required to assert the start of a data frame.

This module takes the 2-line serial input from a TileDMU, unscrambles and then
arranges them in to a 32 bit words corresponding to header, data and CRC
checksum.  The main module glink_asic.vhdl, creates 16 instances of this to
process the 16 TileDMU inputs.

Takes 8 of the 32 bit words from the s2p module and sends them out one by one in
a specified order to a dual port memory instantiated in the glink_asic.vhdl.
There are two dual port memories to handle the full data frame.  The interface
card can hold upto 6 data frames in these dual port memories. (This is
calculated with 7 time samples in digitization process.)

Calculates the CRC checksum on the incoming digitizer data and compares it with
CRC checksum from the digitizer to detect transmission errors from digitizer to
the interface board.  It uses a table driven implementation with the same CRC
polynomial as used in the digitizers.

Calculates a global CRC checksum for the full data frame passing through the 
interface card.

Appends the global CRC checksum at the end of the data frame, which is used by
the link destination card to check for transmission errors.

Ambreesh Gupta 
University of Chicago