--345678901234567890123456789012345678901234567890123456789012345678901234567890 -------------------------------------------------------------------------------- -- -- -- File name : crcrx.vhd -- -- -- -- Author : Erik Brandin, CERN, EP-Division -- -- Erik van der Bij, CERN, EP-Division -- -- -- -- Description : 16 bit CRC 16 bit look-ahead calculator which used the -- -- polynomial implemented in the entity CRCGEN. -- -- -- -- Data on TX_D input is a part of the CRC stream if, and only -- -- if, the input bits RX_FLAG and RX_DATA are high. -- -- -- -- The result from CRCGEN has a two cycles latency. There -- -- is a built-in pipeline to delay the data so that the CRCC -- -- itself is available the same cycle as the result from the -- -- CRCGEN. -- -- -- -- Notes : If, for some reason, another CRC polynomial is to be used, -- -- only the entity CRCGEN has to be modified. -- -- -- -- Uses files : crcgen.vhd -- -- -- -------------------------------------------------------------------------------- -- Revision History -- -------------------------------------------------------------------------------- -- Version | Date |Author| Modifications -- -------------------------------------------------------------------------------- -- 0.1 | 22-07-99 | EB | Original version -- -- 1.0 | 27-07-99 | EB | Output mux removed -- -- 1.1 | 16-11-99 | EB | CRC command changed to odd bit inverted -- -- 2.0 | 26-May-2000 | EvdB | Removed CLK from sensitivity list -- -- 2.1 | 17-Oct-2000 | EvdB | Added HW_UP input so dump entity only regs -- -- 2.11 | 23-Oct-2000 | EvdB | Comments -- -- 2.12 | 27-Oct-2000 | EvdB | Comments -- -- | | | -- -------------------------------------------------------------------------------- library IEEE; use IEEE.Std_Logic_1164.all; -------------------------------------------------------------------------------- entity CRCRX is -------------------------------------------------------------------------------- port ( CLK : in std_logic; -- Input clock HW_UP : in std_logic; -- link up RX_D : in std_logic_vector (15 downto 0); -- G-LINK signals RX_DATA : in std_logic; -- RX_CNTL : in std_logic; -- RX_FLAG : in std_logic; -- CRC : out std_logic_vector(15 downto 0) ); end CRCRX; -------------------------------------------------------------------------------- architecture behaviour of CRCRX is -------------------------------------------------------------------------------- component CRCGEN port ( CLK : in std_logic; CLRCRC: in std_logic; CALC : in std_logic; D : in std_logic_vector (15 downto 0); Q : out std_logic_vector (15 downto 0)); end component; signal rst : std_logic; signal crc_q : std_logic_vector(15 downto 0); signal d_reg0 : std_logic_vector(15 downto 0); signal crc_stream : std_logic; signal clk_n : std_logic; -------------------------------------------------------------------------------- begin -------------------------------------------------------------------------------- clk_n <= not CLK; rxcrc : crcgen port map (clk_n, rst, crc_stream, d_reg0, crc_q); -------------------------------------------------------------------------------- -- Input registers inreg:process(CLK,clk_n) begin if (CLK'event and CLK = '1' ) then crc_stream <= RX_DATA and (not RX_FLAG) and (not RX_CNTL); rst <= RX_CNTL; d_reg0 <= RX_D; end if; if (clk_n'event and clk_n = '1' ) then CRC <= crc_q; end if; end process inreg; -------------------------------------------------------------------------------- end behaviour; -------------------------------------------------------------------------------- -- END OF FILE --------------------------------------------------------------------------------