library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -- 2 of 6 inputs are low result=0 otherwise result=1 entity vote is port ( poll: in std_logic_vector(5 downto 0); result: out std_logic); end vote; architecture a of vote is signal c0,c1,c2,c3,c4 : std_logic; signal c5,c6,c7,c8,c9 : std_logic; signal c10,c11,c12,c13,c14 : std_logic; signal d0,d1,d2 : std_logic; begin c0 <= poll(0) or poll(1); c1 <= poll(0) or poll(2); c2 <= poll(0) or poll(3); c3 <= poll(0) or poll(4); c4 <= poll(0) or poll(5); c5 <= poll(1) or poll(2); c6 <= poll(1) or poll(2); c7 <= poll(1) or poll(3); c8 <= poll(1) or poll(4); c9 <= poll(2) or poll(3); c10 <= poll(2) or poll(4); c11 <= poll(2) or poll(5); c12 <= poll(3) or poll(4); c13 <= poll(3) or poll(5); c14 <= poll(4) or poll(5); d0 <= c0 and c1 and c2 and c3 and c4; d1 <= c5 and c6 and c7 and c8 and c9; d2 <= c10 and c11 and c12 and c13 and c14; result <= d0 and d1 and d2; end a;