library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library lpm;
use lpm.lpm_components.all;

entity s2p_sort is 
	port(
		clki : in std_logic;
		di0 : in std_logic;
		di1 : in std_logic;
		weni : in std_logic;
		clr : in std_logic;
		data_now : in std_logic;
		dready	: out	std_logic;
		do : out std_logic_vector(31 downto 0));
end s2p_sort;

architecture a of s2p_sort is
	signal dffq: std_logic_vector(31 downto 0);
	signal counter_4: std_logic_vector(3 downto 0);
	signal data_av: std_logic;
	signal clk_n: std_logic;
	constant limit: std_logic_vector := "0001";
	signal num_ok: std_logic;
	signal delay0: std_logic;
	signal delay1: std_logic;
	signal delay2: std_logic;
	signal clkib: std_logic;
	signal dostep : std_logic_vector(31 downto 0);
	signal clrshft : std_logic;
	signal reset : std_logic;
	signal wenia : std_logic;
	signal wenib : std_logic;
	signal wenic : std_logic;
	signal wenid : std_logic;
begin
--***************************************************************************
-- use shift register here
--***************************************************************************

data_shift1: lpm_shiftreg  generic map (LPM_WIDTH => 16)
						   port map ( clock => clki,
									  shiftin => di0,
									  enable => weni,
								--	  aclr => clrshft,   
									  q => dffq( 15 downto 0));
data_shift2: lpm_shiftreg  generic map (LPM_WIDTH => 16)
						   port map ( clock => clki,
									  shiftin => di1,
									  enable => weni,
								--	  aclr => clrshft,   
									  q => dffq( 31 downto 16));									
data_count: lpm_counter generic map (LPM_WIDTH => 4)
						port map(clock => clki,
						         clk_en => weni, 
								 aclr => clrshft,
								 q => counter_4);
						
num_cmp: lpm_compare generic map (LPM_WIDTH => 4)
				     port map (dataa => counter_4,
								datab => limit,
								aeb => num_ok);
								
clrshft <= clr or reset;								
clkib <= not clki;
data_av <= num_ok and data_now;
process(clki,clkib,data_av,dffq,dostep)
    variable do_buff: std_logic_vector(31 downto 0);
	variable docrc : std_logic_vector(31 downto 0);
begin
	do_buff(31) := dffq(16);
	do_buff(30) := dffq(0);
 	do_buff(29) := dffq(17);
 	do_buff(28) := dffq(1);
 	do_buff(27) := dffq(18);
 	do_buff(26) := dffq(2);
 	do_buff(25) := dffq(19);
 	do_buff(24) := dffq(3);
 	do_buff(23) := dffq(20);
 	do_buff(22) := dffq(4);
 	do_buff(21) := dffq(21);
 	do_buff(20) := dffq(5);
 	do_buff(19) := dffq(22);
 	do_buff(18) := dffq(6);
 	do_buff(17) := dffq(23);
	do_buff(16) := dffq(7);
 	do_buff(15) := dffq(24);
 	do_buff(14) := dffq(8);
 	do_buff(13) := dffq(25);
 	do_buff(12) := dffq(9);
	do_buff(11) := dffq(26);
	do_buff(10) := dffq(10);
 	do_buff(9) := dffq(27);
	do_buff(8) := dffq(11);
 	do_buff(7) := dffq(28);
 	do_buff(6) := dffq(12);
 	do_buff(5) := dffq(29);
 	do_buff(4) := dffq(13);
 	do_buff(3) := dffq(30);
	do_buff(2) := dffq(14);
 	do_buff(1) := dffq(31);
	do_buff(0) := dffq(15);
		
	docrc(0) := dostep(1);   
    docrc(1) := dostep(3);
    docrc(2) := dostep(5);
    docrc(3) := dostep(7);
    docrc(4) := dostep(9);
    docrc(5) := dostep(11);
    docrc(6) := dostep(13);
    docrc(7) := dostep(15);
    docrc(8) := dostep(17);
    docrc(9) := dostep(19);
    docrc(10) := dostep(21);
    docrc(11) := dostep(23);
    docrc(12) := dostep(25);
    docrc(13) := dostep(27);
    docrc(14) := dostep(29);
    docrc(15) := dostep(31);
    docrc(16) := dostep(0);
    docrc(17) := dostep(2);
    docrc(18) := dostep(4);
    docrc(19) := dostep(6);
    docrc(20) := dostep(8);
    docrc(21) := dostep(10);
    docrc(22) := dostep(12);
    docrc(23) := dostep(14);
    docrc(24) := dostep(16);
    docrc(25) := dostep(18);
    docrc(26) := dostep(20);
    docrc(27) := dostep(22);
    docrc(28) := dostep(24);
    docrc(29) := dostep(26);
    docrc(30) := dostep(28);
    docrc(31) := dostep(30);
    if(clkib'event and clkib = '1') then
       if(data_av = '1') then
         dostep <= do_buff;
       end if;
    end if;
    if(clki'event and clki = '1') then
       if(delay2 = '1') then
          if(weni = '1') then
            do <= dostep;
          else
            do(31) <= '0';
            do(30 downto 0) <= docrc(30 downto 0);
          end if;
	   end if;
	end if;
	if (clkib'event and clkib = '1' ) then
		delay0 <= data_av;
		delay2 <= delay1;
	end if;
	if (clki'event and clki = '1' ) then
       delay1 <= delay0;
	   dready <= delay2;
	end if;
end process;
process(clki,clkib) begin
  if(clki'event and clki = '1') then
    wenia <= weni;
    wenic <= wenib;
  end if;
  if(clkib'event and clkib = '1') then
    wenib <= wenia;
    wenid <= wenic;
  end if;
end process;
  reset <= wenid and not wenic;
end a;