library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.lpm_components.all;
-- e2o collects 32 bit data words from one half of the drawer that have been
-- assembled by the s2p_sort modules and cues the words for storage
-- in the lpm_ram_dp dual port memory
-- en marks that data is ready
-- data_en is the enable for memory storage
entity e2o is
	port (
		reset: in std_logic;
		en: in std_logic;
		data1: in std_logic_vector(31 downto 0);
		data2: in std_logic_vector(31 downto 0);
		data3: in std_logic_vector(31 downto 0);
		data4: in std_logic_vector(31 downto 0);
		data5: in std_logic_vector(31 downto 0);
		data6: in std_logic_vector(31 downto 0);
		data7: in std_logic_vector(31 downto 0);
		data8: in std_logic_vector(31 downto 0);
		data_out: out std_logic_vector(31 downto 0);
		data_en: out std_logic;
		clk_op: in std_logic);
end e2o;

architecture a of e2o is
    type pipe_state is (d1,d2,d3,d4,d5,d6,d7,d8);
    signal current_state : pipe_state;
    signal next_state : pipe_state;
	signal sdata6: std_logic_vector(31 downto 0);
	signal sdata7: std_logic_vector(31 downto 0);
	signal sdata8: std_logic_vector(31 downto 0);
	signal strt : std_logic;
	signal ev5 : std_logic;
	signal ev8 : std_logic;
	signal wen0 : std_logic;
	signal clr_bar : std_logic;
	signal nextev : std_logic;
	
begin
 process(en,ev5,reset) begin
  if(en = '1') then    -- en goes high at the start of each block of 8 words
    strt <= '1';       -- strt stays high for the first 4 words readout
  elsif(ev5 = '1' or reset = '1') then  -- the next en comes in before word 8 is queued
    strt <= '0';
  end if;
 end process;

process(ev8,en,reset) begin
  if(reset='1') then
    nextev <= '0';
  else
    if(en = '1') then
       nextev <= '1';   -- nextev goes high at the start of each block and stays
    elsif(ev8'event and ev8 = '1') then   -- high till all words are read out
       nextev <= strt;                    -- checked at 8th word
    end if;
  end if;
end process;

process(strt,nextev) begin
  if(strt = '1') then
    wen0 <= '1';
  elsif(nextev = '0') then
    wen0 <= '0';
  end if;
end process;

process(clk_op) begin
  if(clk_op'event and clk_op = '1') then
    data_en <= wen0;
    clr_bar <= wen0;
  end if;
end process;

 process(reset,clk_op) begin
   if(reset='1') then
     current_state <= d1;
   elsif(clk_op'event and clk_op = '1') then
     current_state <= next_state;
   end if;
 end process;

 process(current_state) begin
  case current_state is
      when d1 =>
        ev5 <= '0';
        ev8 <= '0';
       data_out <= data1;
       if(clr_bar = '1') then
          next_state <= d2;
        else
          next_state <= d1;
        end if;
      when d2 =>
        data_out <= data2;
        next_state <= d3;
      when d3 =>
        data_out <= data3;
        next_state <= d4;
        sdata6 <= data6;
        sdata7 <= data7;
        sdata8 <= data8;
      when d4 =>
        data_out <= data4;
        next_state <= d5;
      when d5 =>
        ev5 <= '1';
        data_out <= data5;
        next_state <= d6;
      when d6 =>
        ev5 <= '0';
        data_out <= sdata6;
        next_state <= d7;
      when d7 =>
        data_out <= sdata7;
        next_state <= d8;
      when d8 =>
        ev8 <= '1';
        data_out <= sdata8;
        next_state <= d1;
   end case;
 end process;

end a;