--345678901234567890123456789012345678901234567890123456789012345678901234567890 -------------------------------------------------------------------------------- -- -- -- File name : crctx.vhd -- -- -- -- Author : Erik Brandin, CERN, EP-Division -- -- -- -- Description : 16 bit CRC 16 bit look-ahead calculator which used the -- -- polynomial implemented in the entity CRCGEN. -- -- -- -- The CRCTX monitors the input signals and calculates CRC -- -- only on valid data in TX_D_IN. -- -- -- -- The latency is one clock cycle, in which the a control word -- -- is sent (bit 0 and 1 asserted) to signal to the LDC that the -- -- the next cycles contains teh CRCC. -- -- -- -- The cycle where the CRCC is inserted cannot be used to send -- -- any data through TX_D_IN. -- -- -- -- Notes : If, for some reason, another CRC polynomial is to be used, -- -- only the entity CRCGEN has to be modified. -- -- -- -- Uses files : crcgen.vhd -- -- -- -- Max freq. : 106.38MHz -- -- -- -- Size 10K30 : 6% of LC (113) -- -- -- -------------------------------------------------------------------------------- -- Revision History -- -------------------------------------------------------------------------------- -- Version | Date |Author| Modifications -- -------------------------------------------------------------------------------- -- 0.1 | 22-07-99 | EB | Original version -- -- 1.0 | 27-07-99 | EB | Output mux added -- -- 1.1 | 14-09-99 | EB | Control signals removed -- -- 1.2 | 07-10-99 | EB | Reset changed to active high -- -- 1.3 | 16-11-99 | EB | CRC command changed to odd bit inverted -- -------------------------------------------------------------------------------- library IEEE; use IEEE.Std_Logic_1164.all; -------------------------------------------------------------------------------- -- Entity declaration -------------------------------------------------------------------------------- entity CRCTX is port ( CLK : in std_logic; -- Input clock TX_D_IN : in std_logic_vector (15 downto 0); -- G-LINK signals TX_D : out std_logic_vector (15 downto 0); TX_DATA_IN : in std_logic; TX_DATA : out std_logic; TX_CNTL_IN : in std_logic; TX_CNTL : out std_logic; TX_FLAG_IN : in std_logic; TX_FLAG : out std_logic ); end CRCTX; architecture behaviour of CRCTX is -------------------------------------------------------------------------------- -- Component declarations -------------------------------------------------------------------------------- component CRCGEN port ( CLK : in std_logic; CLRCRC: in std_logic; CALC : in std_logic; D : in std_logic_vector (15 downto 0); Q : out std_logic_vector (15 downto 0)); end component; -------------------------------------------------------------------------------- -- Signal declarations -------------------------------------------------------------------------------- signal rst : std_logic; -- Reset signal to crcgen signal crc_f : std_logic_vector(15 downto 0); -- Output from crcgen signal txd0 : std_logic_vector(15 downto 0); signal txd1 : std_logic_vector(15 downto 0); signal txd2 : std_logic_vector(15 downto 0); signal txd3 : std_logic_vector(15 downto 0); signal txdata0,txdata1,txdata2,txdata3 : std_logic; signal txflag0,txflag1,txflag2,txflag3 : std_logic; signal txcntl0,txcntl1,txcntl2,txcntl3 : std_logic; signal clk_n : std_logic; signal idle : std_logic; signal crc_stream: std_logic; signal xmit : std_logic; -------------------------------------------------------------------------------- -- Entity -------------------------------------------------------------------------------- begin -------------------------------------------------------------------------------- -- Component instantiation -------------------------------------------------------------------------------- txcrc : crcgen port map (CLK, rst, crc_stream, TX_D_IN, crc_f); clk_n <= not CLK; pipeline: process(CLK,clk_n) begin if(CLK'event and CLK = '1') then txd0 <= TX_D_IN; txdata0 <= TX_DATA_IN; txflag0 <= TX_FLAG_IN; txcntl0 <= TX_CNTL_IN; end if; if(clk_n'event and clk_n = '1') then txd1 <= txd0; txdata1 <= txdata0; txflag1 <= txflag0; txcntl1 <= txcntl0; end if; if(CLK'event and CLK = '1') then txd2 <= txd1; txdata2 <= txdata1; txflag2 <= txflag1; txcntl2 <= txcntl1; end if; if(clk_n'event and clk_n = '1') then txd3 <= txd2; txdata3 <= txdata2; txflag3 <= txflag2; txcntl3 <= txcntl2; end if; end process pipeline; rst <= txcntl3 and txd3(7) and txd3(6) and txd3(5) and txd3(4); crc_stream <= TX_DATA_IN and (not TX_FLAG_IN) and (not TX_CNTL_IN); -- just pass data idle <= TX_FLAG_IN and (not TX_DATA_IN); -- let crc calc finish xmit <= txflag3 and txdata3; -- latch and send the CRC -------------------------------------------------------------------------------- -- Entity processes -------------------------------------------------------------------------------- -- Output multiplexer -- if TR_CRC was asserted previous cycle the CRC should be sent with MSB first -- to DOUT which can be sent directly to CRCRX. Otherwise DIN is sent to DOUT outmux:process(CLK) begin if (CLK'event and CLK = '1') then if(xmit = '1') then TX_D(15) <= crc_f(0); TX_D(14) <= crc_f(1); TX_D(13) <= crc_f(2); TX_D(12) <= crc_f(3); TX_D(11) <= crc_f(4); TX_D(10) <= crc_f(5); TX_D(9) <= crc_f(6); TX_D(8) <= crc_f(7); TX_D(7) <= crc_f(8); TX_D(6) <= crc_f(9); TX_D(5) <= crc_f(10); TX_D(4) <= crc_f(11); TX_D(3) <= crc_f(12); TX_D(2) <= crc_f(13); TX_D(1) <= crc_f(14); TX_D(0) <= crc_f(15); else TX_D <= txd3; end if; TX_CNTL <= txcntl3; TX_DATA <= txdata3; TX_FLAG <= txflag3; end if; end process outmux; end behaviour; -------------------------------------------------------------------------------- -- END OF FILE --------------------------------------------------------------------------------