% ***************************************************************** * * * * 3in1_V12.tdf for V3.2 3in1 cards July 1999 * * * * * ***************************************************************** % TITLE "3in1_v12"; subdesign 3in1_v12 ( data_in : input; clock : input; card_sel : input; multi_sel : input; rxw : input; enable : input; back_load : input; por : input; % low till power fully on 1 ms % tp : input; s1 : output; s2 : output; s3 : output; s4 : output; itr : output; data_out : output; db0 : output; db1 : output; db2 : output; db3 : output; db4 : output; db5 : output; db6 : output; db7 : output; db8 : output; db9 : output; intg_rd : output; tp_lo : output; tp_hi : output; data_out_ena : output; trig_disable : output; multi : output; selected : output; ) VARIABLE f[7..0], selected, ire, tpelo, tpehi, mse, abit : node; shft[12..0],ashft[12..0] :dff; itrf, iref, msef, trigf :dff; dac[9..0],sf[4..1] :dff; tpel, tpeh :dff; BEGIN % input shift register % shft[12..0].clk = clock & selected; IF rxw THEN shft[0].d = ashft[12].q; ELSE shft[0].d = data_in; END IF; shft[12..1].d = ashft[11..0].q; ashft[12..0].clk = !(clock # back_load) & selected; ashft[12..0].d = shft[12..0].q; % make data_out tristate externally so just send shft[12].q % data_out_ena = card_sel; data_out = shft[12].q; % function codes % f[0] = !shft[2].q & !shft[1].q & !shft[0].q & selected & enable; f[1] = !shft[2].q & !shft[1].q & shft[0].q & selected & enable; f[2] = !shft[2].q & shft[1].q & !shft[0].q & selected & enable; f[3] = !shft[2].q & shft[1].q & shft[0].q & selected & enable; f[4] = shft[2].q & !shft[1].q & !shft[0].q & selected & enable; f[5] = shft[2].q & !shft[1].q & shft[0].q & selected & enable; f[6] = shft[2].q & shft[1].q & !shft[0].q & selected & enable; f[7] = shft[2].q & shft[1].q & shft[0].q & selected & enable; abit = shft[3].q; % integrator read control % iref.d = abit; iref.clk = f[0]; iref.prn = por; ire = iref.q; IF (card_sel) THEN intg_rd = ire; ELSE intg_rd = vcc; END IF; % integrator test/run mode control% itrf.d = abit; itrf.clk = f[1]; itrf.prn = por; itr = itrf.q; % handle s1-s4 latch bits -integrator gain control % sf[4..1].d = shft[6..3].q; sf[4..1].clk = f[2]; sf[1].clrn = por; sf[2].prn = por; sf[3].prn = por; sf[4].prn = por; s[4..1] = sf[4..1].q; % multi_sel control % msef.d = abit; msef.clk = f[3]; msef.clrn = por; mse = msef.q; % card selected % multi = mse & multi_sel; selected = card_sel # multi; % tp_lo control % tpel.d = abit; tpel.clk = f[4]; tpel.clrn = por; tpelo = tpel.q; tp_lo = tpel.q & tp; % tp_hi control % tpeh.d = abit; tpeh.clk = f[5]; tpeh.clrn = por; tpehi = tpeh.q; tp_hi = tpeh.q & tp; % data to dac's output bits % dac[9..0].clk = f[6]; dac[9..0].d = shft[12..3].q; db[9] = dac[0].q; db[8] = dac[1].q; db[7] = dac[2].q; db[6] = dac[3].q; db[5] = dac[4].q; db[4] = dac[5].q; db[3] = dac[6].q; db[2] = dac[7].q; db[1] = dac[8].q; db[0] = dac[9].q; % trigger control % trigf.d = shft[3].q; trigf.clk = f[7]; trigf.prn = por; trig_disable = trigf.q; % set shft[12..0] to internal register value to if back_load goes high % % using preset or clear flip-flop inputs % shft[3].prn = !(back_load & selected & trig_disable); shft[3].clrn = !(back_load & selected & !trig_disable); shft[4].prn = !(back_load & selected & s1); shft[4].clrn = !(back_load & selected & !s1); shft[5].prn = !(back_load & selected & s2); shft[5].clrn = !(back_load & selected & !s2); shft[6].prn = !(back_load & selected & s3); shft[6].clrn = !(back_load & selected & !s3); shft[7].prn = !(back_load & selected & s4); shft[7].clrn = !(back_load & selected & !s4); shft[8].prn = !(back_load & selected & itr); shft[8].clrn = !(back_load & selected & !itr); shft[9].prn = !(back_load & selected & ire); shft[9].clrn = !(back_load & selected & !ire); shft[10].prn = !(back_load & selected & mse); shft[10].clrn = !(back_load & selected & !mse); shft[11].prn = !(back_load & selected & tpelo); shft[11].clrn = !(back_load & selected & !tpelo); shft[12].prn = !(back_load & selected & tpehi); shft[12].clrn = !(back_load & selected & !tpehi); END;