PULSAR (as "PULSer And Recorder") is a general purpose 9U VME interface board for HEP applications. Although it is designed primarily as an upgrade path (original proposal CDF note 6259) for the CDF Level 2 trigger system (see IEEE paper for L2 upgrade , SVT upgrade as well as most recent L2CAL upgrade proposal or see L2CAL upgrade web page), the design is general enough that it can be potentially used in many other applications, within CDF or outside CDF. It can be used as a general purpose interface board, as a standalone DAQ system (such as test beam enviornment) or software based trigger system when combined with modern CPUs, or even as a general purpose diagnostic test tool. Pulsar design is powerful, modular, universal and self-testable. The general design philosophy of Pulsar is to use one type of motherboard (with a few powerful modern FPGAs and SRAMs) to interface any user data with any industrial standard link (for example, CERN S-LINK or Gigabit Ethernet) through the use of custom mezzanine cards. The design is such that users can choose which standard link to interface with via simple custom transition module or mezzanine card. The board is designed to be fully self-testable, at board level as well as at system level. This important feature makes it suitable to develop and tune an upgrade system in stand-alone mode, therefore reduces impact on running experiment during commissioning phase. A summary of all Pulsar applications, within and outside CDF/HEP, can be found at a recent IEEE talk at the IEEE Real Time 2009.
The mezzanine card connections are all bi-directional (i.e. one can plug either transimitter or receiver cards). The implementation is similar to the CMC standard (Common Mezzanine Card) and the actual design followed S-LINK64 spec. There are four mezzanine card slots at the front of the board, each has up to 83 user defined signals directly visible to motherboard FPGAs. Pulsar has user defined interface to P3 connector and this interface has up to 117 signals directly interfacing with one of the main FPGAs on board. This allows users to re-define which standard (or custom) link to interface with on the transition module on the back of the crate. It also has user defined interface to P2 connector with up to 50 signals visible to all three main FPGAs on board via buffer chips. The user defined interfaces to both P3 and P2 are all bi-directional. There are also four different types of LVDS connections at the front of the board and they are the only connections which are specific to CDF application.
For CDF Level 2 trigger application, CERN S-LINK (stands for "Simple LINK") is currently chosen to be the standard link to allow Pulsar to communicate with commodity processors via commercially available, high bandwidth, S-LINK to PCI/PMC interface cards . This is done by using a simple transition module to interface with SLINK mezzanine cards. The mezzanine card interface is compatible with S-LINK interface mezzanine card standard (see S-LINK interface mezzanine card example ). In this application, Pulsar is used as an universal interface board to convert and merge many different trigger data paths into S-LINK standard. In addition, both the Level 1 trigger and track trigger information are made available to each Pulsar, allowing Pulsar to act as pre-processors to pass only Region-of-Interest trigger data downstream. This design feature is driven by physics requirements, providing flexibility in performance. Knowledge to be gained by using S-LINK at CDF will be transferable to and from LHC community.
Due to the use of modern FPGAs on the board with many interfaces, a major fraction of the design effort was dedicated to extensive design verifications by using state-of-the-art Computer Aided Design tools. The tools used include Leonardo Spectrum for VHDL synthesis, Quartus II for place and routing for logic arrays and FPGA gate level simulation, Mentor Graphics QuickSimII using Smart Models together with netlist files created by QuartusII for board and multi-board level simulation, Interconnect Synthesis tool for trace and cross talk analysis to check signal integrity, and IS MultiBoard tool for signal integrity checks between the motherboard and mezzanine cards. The sophisticated tools significantly helped streamline the design process. This design methodology allowed us to build flawless prototype board. The self-test capability of the board design made it possible for us to fully test the prototype boards within 6 weeks after receiving the prototype boards. The prototype boards were also tested with on board clock speed up to 100 MHz and no problems were found. No layout or fabrication errors were found on the prototype boards, allowing them to serve as the production version.
|Nov 2001||Initial design work for Pulsar and hotlink mezzanine cards started|
|Jan 2002||Initial overall firmware design and VHDL code writing for Pulsar started, decided to use LeonardoSpectrum for synthesis, and use QuartusII for place&route.|
|Feb 2002||Core firmware VHDL code in S-LINK merger case working, used for compiler to assign IO pins for all three FPGAs. Optimizing Pulsar design based on the firmware work.|
|March 2002||Pulsar firmware in CVS. Hotlink Mezzanine cards (Tx and Rx) design and board level simulation finished, ordered PCBs. will arrive in April.|
|April 2002||Finalizing schematics for Pulsar board, initial board level simulation in S-LINK merger case successful. Initial layout started (see Pulsar components placement and Pulsar layout) . Hotlink mezzanine cards (Tx/Rx) prototype fully loaded ready for testing. see Hotlink Rx picture and Hotlink Tx picture.|
|May 2002||Pulsar schematics finalized. removed buffers between P3 and control FPGA. More intensive board level simulation successfully done on most part of the board. This includes VME interface with all three FPGAs (internal registers, RAMs, spy FIFOs, as well as external SRAMs), "boundary scan" to check every single connector pin (connectivity) to and from each FPGAs (as input or output) with board level simulation. Initial tests on hotlink mezzanine card prototypes are successful.|
|June 2002||Changed and Optimized Pulsar component placement. Actual routing started (see new layout: Pulsar all layers ). Documenting board level simulation details . Inital Multi-board simulation is successful: Pulsar now can receive data from 4 hotlink Rx mezzanine cards driven by 4 hotlink Tx mezzanine cards, and send out the data in S-LINK format to P3. This was done with 9 boards in the simulation (one Pulsar, 4 Rx mezzanine cards and 4 Tx mezzanine cards). See multi-board simulation setup: Pulsar and his eight daughters ). Initial routing finished, trace analysis starts.|
|July 2002||Trace analysis in progress.Pulsar self test-mode firmware (without mezzanine cards) ready and simulated at board level. Trace analysis results indicate that there are quite a few signals (integrity) need to be improved...done. Pulsar Mini-review as L2 teststand tool. Initial S-LINK to PCI software for testing Pulsar prototype is ready, using SSPCI and SPCIS. See S-LINK teststand setup, another view.|
|Aug 2002||Aug. 1st: L2 review committee asked us to discuss the possibility of using Pulsar for L2 trigger upgrade for Run2b at L2 Review. Finished crosstalk analysis (as suggested by Mini-review committe), Pulsar PCB (X 4) ordered on Aug. 9th. Work on documentation on going... prepare firmware and VME software for initial prototype testing. More trace analysis on going, now using IS MultiBoard tool from Mentor Graphics. 2 PCBs (see Pulsar PCB top view and bottom view) and parts were sent out on Aug. 29th, expect the boards back by Sept.19th.|
|Sept. 2002||Work on L2 upgrade proposal (see upgrade proposal draft, work in progress) and board and device level description of Pulsar (see content of the documentation ). Taxi version mezzanine card work started. Prepare for initial prototype testing work, firmware and VME software for Pulsar initial testing ready (see Simple firmware and vme software for initial Pulsar VME access testing, and Firmware and VME software to test SLINK merger case ). Two fully loaded Pulsar boards received on Sept.19th (see Pulsar front view , Pulsar rear view , Pulsar rear view with two SLINK mezzanine cards , Pulsar with AUX card ). Sept. 21: initial VME access tests to all three FPGAs (registers, LEDs and internal RAMs) are successful. Sept. 24-26th: DOE review. Sept.25th: very first SLINK data formatted inside DataIO FPGA on Pulsar prototype (see description, Firmware block diagram, first SLINK data from DataIO FPGA SLINK spy buffer , Quartus II simulation result: begin of the data package, and Quartus II simulation result: end of the data package.) Sept. 27th: both DataIO FPGAs SLINK output data merged by the Control FPGA and read out via VME through the SLINK spy buffer in the Control FPGA...|
|Oct. 2002||Oct. 1st: SVT testRAM in the Control FPGA --> SVT output connector --> SVT input connector --> SVT spy buffers inside all three FPGAs: the full chain is working on Pulsar prototype. Oct. 3rd: Pulsar SLINK data output to P3 --> AUX card + LSC --> LDC + SLIDAD/LA working. Oct. 4th: SRAM access via VME is working. Oct. 7th: recorded SLINK data from Pulsar into a PC via SLINK_PCI interface! Two SLINK mezzanine cards plugged in at Pulsar front and with two SLIDAS sourcing data, the data has been successfully received by DataIO FPGA and merged inside Control FPGA. The full chain testing setup is working: SLIDASs --> LSCs --> Pulsar DataIO FPGA --> Control FPGA --> LSC on AUX card --> LDC/SLINK to PCI --> PC memory. Oct. 8-9th: completely resigned hotlink mezzanine card Tx and Rx cards (RevB), removed FPGAs on the mezzanine cards and improved performance. Oct.17th: L1 outputs from Pulsar2 --> L1 inputs on Pulsar1 --> DataIO/Control FPGAs working. Oct.21th: performed initial "speed test" on Pulsar, tested with on board clock up to 100 Mhz (default clock is 60Mhz), data processing and merging still works for all FPGAs. Oct. 25th: Rev B Hotlink mezzanine cards fully loaded and tested in BIST mode standalone. Oct. 28th: Hotlink Tx/Rx mezzanine cards tested with Pulsar motherboard and works. Oct. 29th: tested Pulsar with SLINK to Gigabit Ethernet interface (LSC) --> Netgear GA621 gigabit fiber ethernet card and works. Tested Trigger Supervisor interface connection and works. Tested 25 spare lines from Control FPGA to P3 and works. Oct. 30th: tested 5 Pulsar inter-communication lines on P2, works. Checked every CDF signal from P2 into all three FPGAs and works. *INITIAL PULSAR PROTOTYPE CHECK-OUT IS DONE*: have tested EVERY interface (including spare lines) on the Pulsar prototypes (together with SLINK mezzanine cards and custom Hotlink mezzanine cards), and so far no single problem found in the design.|
|Nov. 2002||Nov.1st: Presented the Summary of initial check-out results for the Pulsar prototypes at CDF Trigger Hardware meeting. Sakari went back to Finland on Nov.6th. Nov. 11th: have all 4 Tx mezzanine cards on Tx Pulsar sending data into Rx Pulsar with 4 Rx hotlink mezzanine cards and logged data into PC. Taxi mezzanine card PCBs ordered.|
|Dec. 2002||Received hotlink mezzanine card production PCBs. Received Taxi mezzanine card prototype PCBs. Finalized and ordered AUX card prototype PCBs. Explores the opportunity to use ATLAS RoIB board together with Pulsar boards for CDF RunIIb upgrade (see CDF note 6183 ).|
|Jan. 2003||Pulsar board PCB design won the 1st prize of the 17th Annual Mentor Graphics Systems Design Division PCB Technology Leadership Awards. Received and loaded one AUX card. Automating Pulsar testing procedures (full chain: Tx->Rx->SLINK to PCI or Gigabit Ethernet -> PC) work on going. Received two more fully loaded Pulsar boards from the prototype run. Pulsar prototyping phase ended. L2 upgrade project starts. Created L2 upgrade Pulsar project e-log .|
|Feb. 2003 to now||From now on, for project status, check RunIIb L2 upgrade meetings .|